6d63a531e2
[AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOPD instructions
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Differential Revision: https://reviews.llvm.org/D133414
2022-09-09 13:10:55 +03:00
c07ea46f21
[AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOP3P instructions
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Differential Revision: https://reviews.llvm.org/D133412
2022-09-09 13:06:44 +03:00
efa65ef281
[AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOP3 instructions
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Differential Revision: https://reviews.llvm.org/D133350
2022-09-07 13:55:27 +03:00
a95b45d380
[AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOP3.DPP8 instructions
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Differential Revision: https://reviews.llvm.org/D133353
2022-09-07 13:51:31 +03:00
c777c8f022
[AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOP3.DPP16 instructions
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Differential Revision: https://reviews.llvm.org/D133356
2022-09-07 13:47:55 +03:00
67d148b63c
[AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOPC and VOPC.DPP instructions
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Differential Revision: https://reviews.llvm.org/D132737
2022-08-26 21:38:55 +03:00
35e2107842
[AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOP2 and VOP2.DPP instructions
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Differential Revision: https://reviews.llvm.org/D132733
2022-08-26 21:32:55 +03:00
ad39f1fa8c
[AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOP1 and VOP1.DPP instructions
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Differential Revision: https://reviews.llvm.org/D132731
2022-08-26 21:30:08 +03:00
8ff3cea076
[AMDGPU][MC][GFX11][NFC] Add missing tests for SOP instructions
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Differential Revision: https://reviews.llvm.org/D132404
2022-08-24 13:45:20 +03:00
5e7d43ffef
[AMDGPU][MC][GFX11][NFC] Update tests for FLAT instructions
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Differential Revision: https://reviews.llvm.org/D132402
2022-08-24 13:38:09 +03:00
badf8aed30
[AMDGPU][MC][NFC] Rename disassembler tests
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Make test names more uniform.
Differential Revision: https://reviews.llvm.org/D132472
2022-08-24 13:26:57 +03:00
8f3c160b8b
[AMDGPU][MC][GFX8][NFC] Consolidate tests by encoding
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Differential Revision: https://reviews.llvm.org/D132469
2022-08-24 13:13:22 +03:00
4b9016da0a
[AMDGPU][MC][GFX9][NFC] Consolidate tests by encoding
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Differential Revision: https://reviews.llvm.org/D132409
2022-08-23 13:13:36 +03:00
0a8dd8ef79
[AMDGPU][MC][GFX10][NFC] Consolidate tests by encoding
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Differential Revision: https://reviews.llvm.org/D132235
2022-08-22 19:53:56 +03:00
e99f6df726
[AMDGPU][MC][GFX9][NFC] Split large test file
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Split gfx9_dasm_all.txt by instruction encoding.
Differential Revision: https://reviews.llvm.org/D132124
2022-08-19 14:01:42 +03:00
bdb859c9a7
[AMDGPU][MC][GFX8][NFC] Split large test file
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Split gfx8_dasm_all.txt by instruction encoding.
Differential Revision: https://reviews.llvm.org/D132126
2022-08-19 13:54:56 +03:00
7e29d5c04b
[AMDGPU][MC][GFX10][NFC] Split large test
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Split gfx10_dasm_all.txt by encoding.
Differential Revision: https://reviews.llvm.org/D132044
2022-08-18 12:39:34 +03:00
4e68834add
[AMDGPU][MC][GFX11][NFC] Add tests for VOP1 and VOP2 16 bit opcodes
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Differential Revision: https://reviews.llvm.org/D131588
2022-08-11 17:12:13 +03:00
eda6e49aa8
[AMDGPU][MC][GFX11][NFC] Correct tests for 16-bit VOP2 opcodes which use v128 or higher VGPRs
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Differential Revision: https://reviews.llvm.org/D131564
2022-08-11 15:55:58 +03:00
9d1eeefbfe
[AMDGPU][MC][GFX11][NFC] Rename tests
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Make test names more uniform.
Differential Revision: https://reviews.llvm.org/D131398
2022-08-09 13:56:05 +03:00
fc4c1a86f3
[AMDGPU][MC][GFX11][NFC] Split large tests
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Differential Revision: https://reviews.llvm.org/D131397
2022-08-09 13:24:23 +03:00
05b3aadfff
[AMDGPU][MC][GFX11] Correct v_dot2_f16_f16 and v_dot2_bf16_bf16
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Enable SGPRs for the following operands of these opcodes:
- src operands of VOP3 variant.
- src2 operand of DPP variants.
Differential Revision: https://reviews.llvm.org/D130989
2022-08-03 15:08:23 +03:00
ae553f9e49
[AMDGPU][MC][GFX10] Correct encoding of VOP3 v_cmpx* opcodes
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Encode dst=EXEC but allow disassembler accept any dst value.
Differential Revision: https://reviews.llvm.org/D130978
2022-08-03 15:03:44 +03:00
bb901dcc5a
[AMDGPU][MC][GFX940] Correct disassembly of MFMA opcodes
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Add a decoder table for GFX940 MFMA opcodes.
Differential Revision: https://reviews.llvm.org/D130759
2022-08-01 16:00:47 +03:00
e8d260753e
[AMDGPU] gfx11 allow dlc for MUBUF atomics
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Add MC support for dlc in gfx11 MUBUF atomic instructions.
Differential Revision: https://reviews.llvm.org/D129075
2022-08-01 12:18:01 +02:00
6a1aa627fa
[AMDGPU] Enable image_gather4h instruction for gfx10 and gfx11
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Differential Revision: https://reviews.llvm.org/D130764
2022-07-29 15:42:06 +02:00
0eb9f18520
[AMDGPU][MC][GFX11] Correct encoding of VOP3/VOP3_DPP v_cmpx* opcodes
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Encode dst=EXEC but allow disassembler accept any dst value.
Differential Revision: https://reviews.llvm.org/D130345
2022-07-26 17:36:22 +03:00
8de1f04c77
[AMDGPU] gfx11 Fix VOP3 dot instructions
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Fix src modifiers for operands with bf16 type.
op_sel[0:1] are ignored.
Differential Revision: https://reviews.llvm.org/D129084
2022-07-22 11:43:35 +02:00
523a99c0eb
[AMDGPU] Support for gfx940 fp8 smfmac
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Differential Revision: https://reviews.llvm.org/D129908
2022-07-18 12:12:41 -07:00
2695f0a688
[AMDGPU] Support for gfx940 fp8 mfma
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Differential Revision: https://reviews.llvm.org/D129906
2022-07-18 11:49:56 -07:00
9fa5a6b7e8
[AMDGPU] Support for gfx940 fp8 conversions
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Differential Revision: https://reviews.llvm.org/D129902
2022-07-18 11:48:43 -07:00
2a6532d542
[AMDGPU][MC][GFX11] Correct disassembly of *_e64_dpp opcodes which support op_sel
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These opcodes cannot be disassembled because op_sel operand is missing - it must be added manually.
See https://github.com/llvm/llvm-project/issues/56512 for detailed issue analysis.
Differential Revision: https://reviews.llvm.org/D129637
2022-07-15 13:11:59 +03:00
4874838a63
[AMDGPU] gfx11 WMMA instruction support
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gfx11 introduces new WMMA (Wave Matrix Multiply-accumulate)
instructions.
Reviewed By: arsenm, #amdgpu
Differential Revision: https://reviews.llvm.org/D128756
2022-06-30 11:13:45 -04:00
07b7fada73
[AMDGPU] gfx11 VOPD instructions MC support
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VOPD is a new encoding for dual-issue instructions for use in wave32.
This patch includes MC layer support only.
A VOPD instruction is constituted of an X component (for which there are
13 possible opcodes) and a Y component (for which there are the 13 X
opcodes plus 3 more). Most of the complexity in defining and parsing
a VOPD operation arises from the possible different total numbers of
operands and deferred parsing of certain operands depending on the
constituent X and Y opcodes.
Reviewed By: dp
Differential Revision: https://reviews.llvm.org/D128218
2022-06-24 11:08:39 -04:00
dcb24f93af
[AMDGPU][MC][GFX11] Correct disassembly of VOP3.DPP8 opcodes
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Fix bug #56163 .
Add W32/W64 tests for all VOP3.DPP opcodes.
Differential Revision: https://reviews.llvm.org/D128369
2022-06-23 13:07:45 +03:00
485e8b4f63
[AMDGPU][MC][GFX11] Correct disassembly of DPP variants of VOPC64 opcodes
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Fix bugs https://github.com/llvm/llvm-project/issues/56091 , https://github.com/llvm/llvm-project/issues/56065 .
Differential Revision: https://reviews.llvm.org/D128075
2022-06-20 14:23:07 +03:00
b26afab9d1
[AMDGPU][MC][GFX11] Correct src0 for dpp variants of v_cvt_*_e64
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Differential Revision: https://reviews.llvm.org/D127847
2022-06-16 13:48:43 +03:00
989bd57f98
[AMDGPU] gfx11 support add_f16
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The instruction was skipped in the earlier large patch adding
VOP2, https://reviews.llvm.org/D126917 .
Reviewed By: rampitec, #amdgpu
Differential Revision: https://reviews.llvm.org/D127697
2022-06-14 08:59:45 -04:00
365d827f65
[AMDGPU][MC][GFX11] Correct ds_swizzle_b32
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Enable offset parsing.
Differential Revision: https://reviews.llvm.org/D127404
2022-06-14 12:58:03 +03:00
fd3304ef85
[AMDGPU] gfx11 EXECZ and VCCZ are no longer allowed to be used as
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sources to SALU and VALU instructions.
Contributors:
Baptiste Saleil <baptiste.saleil@amd.com>
Patch 20/N for upstreaming of AMDGPU gfx11 architecture
Depends on D126989
Reviewed By: rampitec, foad, #amdgpu
Differential Revision: https://reviews.llvm.org/D127143
2022-06-10 10:03:43 -04:00
60d6fbb621
[AMDGPU][GFX9][GFX10] Support base+soffset+offset SMEM atomics.
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Resolves a part of
https://github.com/llvm/llvm-project/issues/38652
Reviewed By: dp
Differential Revision: https://reviews.llvm.org/D127314
2022-06-10 13:22:41 +01:00
be1082c6d5
[AMDGPU] gfx11 VOPC instructions
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Supports encoding existing instrutions on gfx11 and MC support for the new VOPC
dpp instructions.
Patch 19/N for upstreaming of AMDGPU gfx11 architecture
Depends on D126978
Reviewed By: rampitec, #amdgpu
Differential Revision: https://reviews.llvm.org/D126989
2022-06-09 15:22:42 -04:00
40f35cef89
[AMDGPU] gfx11 VOP3P instruction MC support
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Includes dpp versions of VOP3P instructions.
Patch 18/N for upstreaming of AMDGPU gfx11 architecture
Depends on D126917
Reviewed By: rampitec, #amdgpu
Differential Revision: https://reviews.llvm.org/D126978
2022-06-08 13:32:01 -04:00
086a9c1062
Reland [AMDGPU] gfx11 VOP1+VOP2 Instruction MC support
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The reverted dependent commit is now relanded, so reland this.
Includes dpp instructions and vop1/vop2 promoted to vop3
Patch 17/N for upstreaming of AMDGPU gfx11 architecture
Depends on D126483
Reviewed By: rampitec, #amdgpu
Differential Revision: https://reviews.llvm.org/D126917
2022-06-08 11:10:57 -04:00
e243ead6fc
Reland [AMDGPU] gfx11 vop3dpp instructions
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There was an issue with encoding wide (>64 bit) instructions on
BigEndian hosts, which is fixed in D127195. Therefore reland this.
gfx11 adds the ability to use dpp modifiers on vop3 instructions.
This patch adds machine code layer support for that. The MCCodeEmitter
is changed to use APInt instead of uint64_t to support these wider
instructions.
Patch 16/N for upstreaming of AMDGPU gfx11 architecture
Differential Revision: https://reviews.llvm.org/D126483
2022-06-07 14:49:13 -04:00
eaed07eb7e
Revert "[AMDGPU] gfx11 vop3dpp instructions"
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This reverts commit 99a83b1286
2022-06-06 17:12:09 -04:00
f617f89e5b
Revert "[AMDGPU] gfx11 VOP1+VOP2 Instruction MC support"
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This reverts commit 6079804498
2022-06-06 17:11:35 -04:00
facbfb121a
[AMDGPU][GFX9+] Support base+soffset+offset s_atc_probe's.
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Resolves part of
https://github.com/llvm/llvm-project/issues/38652
Reviewed By: dp
Differential Revision: https://reviews.llvm.org/D126791
2022-06-06 16:46:22 +01:00
79ec1e8fd6
[AMDGPU][GFX9][GFX10] Support base+soffset+offset s_dcache_discard's.
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Resolves part of
https://github.com/llvm/llvm-project/issues/38652
Reviewed By: dp
Differential Revision: https://reviews.llvm.org/D126766
2022-06-06 16:32:16 +01:00
6079804498
[AMDGPU] gfx11 VOP1+VOP2 Instruction MC support
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Includes dpp instructions and vop1/vop2 promoted to vop3
Patch 17/N for upstreaming of AMDGPU gfx11 architecture
Depends on D126483
Reviewed By: rampitec, #amdgpu
Differential Revision: https://reviews.llvm.org/D126917
2022-06-06 09:57:59 -04:00
Dmitry Preobrazhensky