Commit Graph

16 Commits

Author SHA1 Message Date
Nate Begeman 6e6514c47e Several fixes and enhancements to the PPC32 backend.
1. Fix an illegal argument to getClassB when deciding whether or not to
   sign extend a byte load.

2. Initial addition of isLoad and isStore flags to the instruction .td file
   for eventual use in a scheduler.

3. Rewrite of how constants are handled in emitSimpleBinaryOperation so
   that we can emit the PowerPC shifted immediate instructions far more
   often.  This allows us to emit the following code:

int foo(int x) { return x | 0x00F0000; }

_foo:
.LBB_foo_0:     ; entry
        ; IMPLICIT_DEF
        oris r3, r3, 15
        blr

llvm-svn: 16826
2004-10-07 22:30:03 +00:00
Misha Brukman 6b17bf7193 s/ISel/PPC64ISel/ to have unique class names for debugging via gdb because the
C++ front-end in gcc does not mangle classes in anonymous namespaces correctly.

llvm-svn: 16471
2004-09-21 18:22:33 +00:00
Nate Begeman 54bcf2db01 Add 64 bit divide instructions, and use them
llvm-svn: 16198
2004-09-06 18:46:59 +00:00
Reid Spencer 7c16caa336 Changes For Bug 352
Move include/Config and include/Support into include/llvm/Config,
include/llvm/ADT and include/llvm/Support. From here on out, all LLVM
public header files must be under include/llvm/.

llvm-svn: 16137
2004-09-01 22:55:40 +00:00
Nate Begeman 8cb6bd5f3c Improvements to int->float cast code for PPC-64
llvm-svn: 16105
2004-08-29 22:02:43 +00:00
Misha Brukman 170943a795 Stack space for argument passing is 32 regardless of 32- vs. 64-bit arch.
Thanks to Nate Begeman for pointing this out.

llvm-svn: 15930
2004-08-19 21:51:19 +00:00
Misha Brukman f35b35a926 On 64-bit PowerPC, pointers are 8 bytes, so parameter area offset is 48, not 24
llvm-svn: 15928
2004-08-19 21:34:05 +00:00
Misha Brukman a5543ac5fb Fix more remaining 32-bit vestiges of PowerPC
llvm-svn: 15919
2004-08-19 18:49:58 +00:00
Misha Brukman 2ff719f74f Fix another vestige of the 32-bit PowerPC backend.
llvm-svn: 15918
2004-08-19 16:50:30 +00:00
Misha Brukman 0010ea3042 * Eliminate global base register, r2 is used for that on AIX/PowerPC
* Fix bug from 32-bit PowerPC days of 2-register long split

llvm-svn: 15916
2004-08-19 16:29:25 +00:00
Nate Begeman e4e6d92d1d Clean up floating point instruction selection.
Change int->float cast code to put conversion constants in constant pool.
Shorten code sequence for constant pool fp loads.
Remove LOADLoDirect/LOADLoIndirect psuedo instructions and tweak asmwriter

llvm-svn: 15913
2004-08-19 05:20:54 +00:00
Misha Brukman ac0ae7c215 PowerPC 32-/64-bit split: Part II, 64-bit customizations on PowerPC
llvm-svn: 15851
2004-08-17 04:57:37 +00:00
Nate Begeman 2e8bfa2364 Longs are in one register on PowerPC 64; use appropriate instructions to operate on them.
llvm-svn: 15711
2004-08-13 02:20:47 +00:00
Misha Brukman 52a4abc299 * Correct 64-bit version: blr 1 (not 0)
* BuildMI() can build 0-param instructions (e.g., NOP)

llvm-svn: 15681
2004-08-12 03:30:03 +00:00
Misha Brukman 58040a63ee * Pointers are 8 bytes, hence cLong type on 64-bit PPC
* Fix loading of GlobalValues

llvm-svn: 15678
2004-08-12 02:53:01 +00:00
Misha Brukman c2a043488a 64-bit instruction selector and AIX-specific 64-bit asm printer
llvm-svn: 15669
2004-08-11 23:42:15 +00:00