llvm-project

Commit Graph

Author	SHA1	Message	Date
Sam Parker	43fa5911a1	[DAGCombine] Enable more srl -> load combines Change the calculation for the desired ValueType for non-sign extending loads, as in those cases we don't care about the higher bits. This creates a smaller ExtVT and allows for such combinations as: (srl (zextload i16, [addr]), 8) -> (zextload i8, [addr + 1]) Differential Revision: https://reviews.llvm.org/D40034 llvm-svn: 318390	2017-11-16 11:28:26 +00:00
Zijiao Ma	bf6007bd1b	Make the canonicalisation on shifts benifit to more case. 1.Fix pessimized case in FIXME. 2.Add tests for it. 3.The canonicalisation on shifts results in different sequence for tests of machine-licm.Correct some check lines. Differential Revision: https://reviews.llvm.org/D27916 llvm-svn: 290410	2016-12-23 02:56:07 +00:00

Author

SHA1

Message

Date

Sam Parker

43fa5911a1

[DAGCombine] Enable more srl -> load combines

Change the calculation for the desired ValueType for non-sign
extending loads, as in those cases we don't care about the
higher bits. This creates a smaller ExtVT and allows for such
combinations as:
(srl (zextload i16, [addr]), 8) -> (zextload i8, [addr + 1])

Differential Revision: https://reviews.llvm.org/D40034

llvm-svn: 318390

2017-11-16 11:28:26 +00:00

Zijiao Ma

bf6007bd1b

Make the canonicalisation on shifts benifit to more case.

1.Fix pessimized case in FIXME.
2.Add tests for it.
3.The canonicalisation on shifts results in different sequence for
  tests of machine-licm.Correct some check lines.

Differential Revision: https://reviews.llvm.org/D27916

llvm-svn: 290410

2016-12-23 02:56:07 +00:00

2 Commits