llvm-project

Commit Graph

Author	SHA1	Message	Date
Sanjay Patel	65d6780703	[x86] enable storeOfVectorConstantIsCheap() target hook This allows vector-sized store merging of constants in DAGCombiner using the existing code in MergeConsecutiveStores(). All of the twisted logic that decides exactly what vector operations are legal and fast for each particular CPU are handled separately in there using the appropriate hooks. For the motivating tests in merge-store-constants.ll, we already produce the same vector code in IR via the SLP vectorizer. So this is just providing a backend backstop for code that doesn't go through that pass (-O1). More details in PR24449: https://bugs.llvm.org/show_bug.cgi?id=24449 (this change should be the last step to resolve that bug) Differential Revision: https://reviews.llvm.org/D37451 llvm-svn: 313458	2017-09-16 13:29:12 +00:00
Sanjay Patel	8d7c8c7960	[x86] add tests for vector store merge opportunity; NFC llvm-svn: 312504	2017-09-04 22:01:25 +00:00

Author

SHA1

Message

Date

Sanjay Patel

65d6780703

[x86] enable storeOfVectorConstantIsCheap() target hook

This allows vector-sized store merging of constants in DAGCombiner using the existing code in MergeConsecutiveStores(). 
All of the twisted logic that decides exactly what vector operations are legal and fast for each particular CPU are 
handled separately in there using the appropriate hooks.

For the motivating tests in merge-store-constants.ll, we already produce the same vector code in IR via the SLP vectorizer. 
So this is just providing a backend backstop for code that doesn't go through that pass (-O1). More details in PR24449:
https://bugs.llvm.org/show_bug.cgi?id=24449 (this change should be the last step to resolve that bug)

Differential Revision: https://reviews.llvm.org/D37451

llvm-svn: 313458

2017-09-16 13:29:12 +00:00

Sanjay Patel

8d7c8c7960

[x86] add tests for vector store merge opportunity; NFC

llvm-svn: 312504

2017-09-04 22:01:25 +00:00

2 Commits