Craig Topper
a02e394872
[AVX-512] Split X86ISD::VFPROUND and X86ISD::VFPEXT into separate opcodes for each type constraint.
...
This revealed that scalar intrinsics could create nodes with a rounding mode of FROUND_CUR_DIRECTION, but the patterns didn't check for it. It just worked because isel doesn't check operand count and we had a pattern without the rounding mode argument at all.
llvm-svn: 282231
2016-09-23 06:24:43 +00:00
Craig Topper
3174b6e467
[AVX-512] Add separate ISD opcodes for each form of CVT instructions. Don't reuse non-X86 ISD opcodes with extra X86 specific arguments.
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llvm-svn: 282230
2016-09-23 06:24:39 +00:00
Craig Topper
d70ec9b25e
[AVX-512] Use different ISD opcodes for some of the scalar intrinsic lowering. Isel is not very robust against using the same ISD opcode with different number of operands so its better to separate.
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llvm-svn: 282229
2016-09-23 06:24:35 +00:00
Craig Topper
29f1a1f834
[AVX-512] Split the 3 different usages of the X86ISD::FSETCC opcode into 3 different opcodes.
...
It turns out isel is really not robust against having different type profiles for the same opcode. It turns out that if you put an illegal rounding mode(i.e. not CUR_DIRECTION or NO_EXC) on a comiss intrinsic we would generate the FSETCC form with the rounding mode added, but then pattern match to an instruction with ROUND_CUR_DIRECTION.
We can probably get away with just one FSETCCM opcode that always contains the rounding mode and explicitly put ROUND_CUR_DIRECTION in the pattern, but I'll leave that for future work.
With this change the clang tests for the comiss intrinsics that used an incorrect rounding mode of 3 properly fail isel instead of silently doing the wrong thing. Those clang tests will be fixed in a follow up commit and I also plan to add rounding mode checking to clang.
llvm-svn: 282055
2016-09-21 06:37:54 +00:00
Craig Topper
d868870f17
[AVX-512] Don't add an additional rounding mode operand to the avx512 vcvtps2ph intrinsic lowering.
...
There was no way to control its value so it was always FROUND_CURRENT making it unnecessary. The true rounding mode is encoded in the immediate operand of the instruction.
This also removes the pattern from the rb form of the instructions since there is no way to specify the FROUND_NO_EXC rounding mode it required.
llvm-svn: 282052
2016-09-21 03:58:44 +00:00
Craig Topper
e18258dc1c
[AVX-512] Don't lower avx512 vcvtps2ph/vcvtph2ps nodes to ISD::FP16_TO_FP/ISD::FP_TO_FP16 with an extra x86 specific rounding mode operand. We should use a target specific ISD opcode.
...
llvm-svn: 282046
2016-09-21 02:05:22 +00:00
Craig Topper
af5ee86bc9
[AVX-512] Don't lower CVTPD2PS intrinsics to ISD::FP_ROUND with an X86 rounding mode encoding in the second operand. This immediate should only be 0 or 1 and indicates if the truncation loses precision.
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Also enhance an assert in SelectionDAG::getNode to flag this sort of problem in the future.
llvm-svn: 281868
2016-09-18 21:49:32 +00:00
Craig Topper
c26cd68422
[AVX-512] Stop lowering avx512_mask_sqrt intrinsics to ISD:FSQRT with a second operand containing an X86 specific rounding mode encoding that doesn't belong.
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llvm-svn: 281867
2016-09-18 21:49:28 +00:00
Craig Topper
4e2d5a43cf
[X86] Remove the VCVTSI2SD32 with rounding intrinsic. It's not used by clang and not needed since 32-bit integer to double is always exact.
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llvm-svn: 281442
2016-09-14 06:27:46 +00:00
Craig Topper
4619c9e6a8
[X86] Remove masked shufpd/shufps intrinsics and autoupgrade to native vector shuffles. They were removed from clang previously but accidentally left in the backend.
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llvm-svn: 281300
2016-09-13 07:40:53 +00:00
Craig Topper
43fbd840dd
[X86] Remove unused encoding from IntrinsicType enum.
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llvm-svn: 280694
2016-09-06 05:45:24 +00:00
Craig Topper
4177345d7f
[AVX-512] Remove 128-bit and 256-bit masked floating point add/sub/mul/div intrinsics and upgrade to native IR.
...
llvm-svn: 280633
2016-09-04 18:13:33 +00:00
Craig Topper
af0d63d2e7
[AVX-512] Remove masked integer add/sub/mull intrinsics and upgrade to native IR.
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llvm-svn: 280611
2016-09-04 02:09:53 +00:00
Craig Topper
e75c49543c
[AVX-512] Remove floating point logical operation instrinsics and replace them with native IR.
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llvm-svn: 280466
2016-09-02 05:29:17 +00:00
Simon Pilgrim
6199b4fd49
[X86][SSE] Improve awareness of (v)cvtpd2ps implicit zeroing of upper 64-bits of xmm result
...
Associate x86_sse2_cvtpd2ps with X86ISD::VFPROUND to avoid inserting unnecessary zeroing shuffles.
Differential Revision: https://reviews.llvm.org/D23797
llvm-svn: 280249
2016-08-31 15:09:34 +00:00
Guy Blank
722caebdae
[X86] Add xgetbv/xsetbv intrinsics to non-windows platforms
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Differential Revision: https://reviews.llvm.org/D21958
llvm-svn: 278782
2016-08-16 06:41:00 +00:00
Craig Topper
a6e6febe2c
[AVX512] Remove masked logic op intrinsics and autoupgrade them to native IR.
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llvm-svn: 275155
2016-07-12 05:27:53 +00:00
Craig Topper
70610cf7b6
[X86] Remove and autoupgrade 512-bit non-temporal store intrinsics.
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llvm-svn: 274966
2016-07-09 04:38:27 +00:00
Craig Topper
f7bf6de0af
[AVX512] Remove and autoupgrade a duplicate set of 512-bit masked shift intrinsics.
...
I'm not sure if clang ever used these builtin names or not.
llvm-svn: 274827
2016-07-08 06:14:47 +00:00
Simon Pilgrim
9769428e08
[X86][AVX512] Remove vector BROADCAST builtins.
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llvm-svn: 274555
2016-07-05 14:49:58 +00:00
Craig Topper
5d16cd9d63
[AVX512] Remove masked VPERMD/VPERMQ/VPERMILPS/VPERMILPD intrinsics. They were autoupgraded to native IR in r274506 and r274506.
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llvm-svn: 274519
2016-07-04 19:58:38 +00:00
Simon Pilgrim
77dda7c2e0
[X86][AVX512] Converted the MOVDDUP/MOVSLDUP/MOVSHDUP masked intrinsics to generic IR
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llvm-svn: 274443
2016-07-02 17:16:41 +00:00
Craig Topper
597aa42fec
[AVX512] Remove masked unpack intrinsics and autoupgrade to vectorshuffle and selects.
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llvm-svn: 273543
2016-06-23 07:37:33 +00:00
Craig Topper
0a0fb0fda1
[AVX512] Remove the masked vpcmpeq/vcmpgt intrinsics and autoupgrade them to native icmps.
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llvm-svn: 273240
2016-06-21 03:53:24 +00:00
Igor Breger
e59165ca63
[AVX512] [AVX512/AVX][Intrinsics] Fix Variable Bit Shift Right Arithmetic intrinsic lowering.
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Differential Revision: http://reviews.llvm.org/D20897
llvm-svn: 273138
2016-06-20 07:05:43 +00:00
Sanjay Patel
0e9afea3c8
[x86] autoupgrade and remove AVX2 integer min/max intrinsics
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This will (hopefully very temporarily) break clang.
The clang side of this should be the next commit.
llvm-svn: 272932
2016-06-16 18:44:20 +00:00
Sanjay Patel
51ab757941
[x86] autoupgrade and remove SSE2/SSE41 integer min/max intrinsics
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Follow-up to:
http://reviews.llvm.org/rL272806
http://reviews.llvm.org/rL272807
llvm-svn: 272907
2016-06-16 15:48:30 +00:00
David Majnemer
248190ba69
[X86] Remove llvm.x86.bit.scan.{forward,reverse}.32
...
The need for these intrinsics has been obviated by r272564 which
reimplements their functionality using generic IR.
llvm-svn: 272566
2016-06-13 17:33:13 +00:00
Craig Topper
13cf7cac07
[AVX512] Remove maksed pshufd, pshuflw, and phufhw intrinsics and autoupgrade them to selects and shufflevector.
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llvm-svn: 272527
2016-06-13 02:36:48 +00:00
Craig Topper
1067986c5b
[X86] Remove sse2 pshufd/pshuflw/pshufhw intrinsics and upgrade them to shufflevector.
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llvm-svn: 272510
2016-06-12 14:11:32 +00:00
Craig Topper
251030babe
[AVX512] Remove the masked palignr intrinsics that I forgot to remove when I added auto-upgrade code to turn them into shufflevectors and selects.
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llvm-svn: 272497
2016-06-12 04:14:13 +00:00
Simon Pilgrim
f718682eb9
[X86][AVX512] Dropped avx512 VPSLLDQ/VPSRLDQ intrinsics
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Auto-upgrade to generic shuffles like sse/avx2 implementations now that we can lower to VPSLLDQ/VPSRLDQ
llvm-svn: 272308
2016-06-09 21:09:03 +00:00
Igor Breger
f635367e2b
[AVX512] Remove masked_move/blendm intrinsic from back-end.
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This is complement patch to D21060.
Differential Revision: http://reviews.llvm.org/D21174
llvm-svn: 272257
2016-06-09 11:46:55 +00:00
Craig Topper
6ae375c9ba
[X86] Use smaller types to shrink the intrinsic lowering tables by about 12K.
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llvm-svn: 271776
2016-06-04 04:32:17 +00:00
Craig Topper
5250634334
[X86] Use X86ISD::ABS for lowering pabs SSSE3/AVX intrinsics to match AVX512. Should allow those intrinsics to use the EVEX encoded instructions and get the extra registers when available.
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llvm-svn: 271775
2016-06-04 04:32:15 +00:00
Simon Pilgrim
e85506b6e0
[X86][XOP] Support for VPERMIL2PD/VPERMIL2PS 2-input shuffle instructions
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This patch begins adding support for lowering to the XOP VPERMIL2PD/VPERMIL2PS shuffle instructions - adding the X86ISD::VPERMIL2 opcode and cleaning up the usage.
The internal llvm intrinsics were assuming the shuffle mask operand was the same type as the float/double input operands (I guess to simplify the intrinsic definitions in X86InstrXOP.td to a single value type). These needed changing to integer types (matching the clang builtin and the AMD intrinsics definitions), an auto upgrade path is added to convert old calls.
Mask decoding/target shuffle support will be added in future patches.
Differential Revision: http://reviews.llvm.org/D20049
llvm-svn: 271633
2016-06-03 08:06:03 +00:00
Craig Topper
5bb9cda620
[AVX512] Remove LOADA/LOADU/STOREA/STOREU intrinsic types now that they are unused.
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llvm-svn: 271479
2016-06-02 04:19:40 +00:00
Craig Topper
f10fbfa738
[AVX512] Remove masked load intrinsics. Clang now emits generic masked load intrinsics instead.
...
The intrinsics will be autoupgraded to the same generic masked loads.
llvm-svn: 271478
2016-06-02 04:19:36 +00:00
Michael Zuckerman
6a894956fc
Adding back-end support to two bit scanning intrinsics
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Adding LLVM back-end support to two intrinsics dealing with bit scan: _bit_scan_forward and _bit_scan_reverse.
Their functionality is as described in Intel intrinsics guide:
https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bit_scan_forward&expand=371,370
https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bit_scan_reverse&expand=371,370
Commit on behalf of Omer Paparo Bivas
Differential Revision: http://reviews.llvm.org/D19915
llvm-svn: 271386
2016-06-01 12:02:37 +00:00
Craig Topper
4f2d5a68d3
Revert r271362 "[AVX512] Remove masked load intrinsics. Clang now emits generic masked load intrinsics instead."
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Looks like something isn't quite right still. Also forgot to move the test cases to an autoupgrade test.
llvm-svn: 271363
2016-06-01 05:57:55 +00:00
Craig Topper
dacd9d2bac
[AVX512] Remove masked load intrinsics. Clang now emits generic masked load intrinsics instead.
...
The intrinsics will be autoupgraded to the same generic masked loads.
llvm-svn: 271362
2016-06-01 05:35:16 +00:00
Igor Breger
52bd1d5fcc
Fix intrinsic vbroadcast{i32|f32}x2 lowering.
...
Differential Revision: http://reviews.llvm.org/D20780
llvm-svn: 271254
2016-05-31 07:43:39 +00:00
Craig Topper
50f85c22c5
[AVX512] Remove masked store intrinsics. Clang now emits generic masked store intrinsics instead.
...
The intrinsics will be autoupgraded to the same generic masked stores.
llvm-svn: 271245
2016-05-31 01:50:02 +00:00
Simon Pilgrim
9602d678cb
[X86][SSE] (Reapplied) Replace (V)PMOVSX and (V)PMOVZX integer extension intrinsics with generic IR (llvm)
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This patch removes the llvm intrinsics VPMOVSX and (V)PMOVZX sign/zero extension intrinsics and auto-upgrades to SEXT/ZEXT calls instead. We already did this for SSE41 PMOVSX sometime ago so much of that implementation can be reused.
Reapplied now that the the companion patch (D20684) removes/auto-upgrade the clang intrinsics has been committed.
Differential Revision: http://reviews.llvm.org/D20686
llvm-svn: 271131
2016-05-28 18:03:41 +00:00
Simon Pilgrim
4642a57fbf
Revert: r270973 - [X86][SSE] Replace (V)PMOVSX and (V)PMOVZX integer extension intrinsics with generic IR (llvm)
...
llvm-svn: 270976
2016-05-27 09:02:25 +00:00
Simon Pilgrim
c013e5737b
[X86][SSE] Replace (V)PMOVSX and (V)PMOVZX integer extension intrinsics with generic IR (llvm)
...
This patch removes the llvm intrinsics VPMOVSX and (V)PMOVZX sign/zero extension intrinsics and auto-upgrades to SEXT/ZEXT calls instead. We already did this for SSE41 PMOVSX sometime ago so much of that implementation can be reused.
A companion patch (D20684) removes/auto-upgrade the clang intrinsics.
Differential Revision: http://reviews.llvm.org/D20686
llvm-svn: 270973
2016-05-27 08:49:15 +00:00
Igor Breger
23c2090606
[llvm][AVX512][intrinsics] Fix vperm{b|w|d|q|ps|pd} intrinsics. Index is second argument to buildin function but it is first instruction operand.
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Differential Revision: http://reviews.llvm.org/D20515
llvm-svn: 270548
2016-05-24 11:06:22 +00:00
Michael Zuckerman
a63a129749
[Clang][AVX512][intrinsics] Fix rcp and sqrt intrinsics.
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Differential Revision: http://reviews.llvm.org/D20438
llvm-svn: 270322
2016-05-21 14:44:18 +00:00
Michael Zuckerman
11b55b29d1
[Clang][AVX512][intrinsics] Fix vscalef intrinsics.
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Differential Revision: http://reviews.llvm.org/D20324
llvm-svn: 270321
2016-05-21 11:09:53 +00:00
Craig Topper
b395105584
[X86] Convert some SSE2/AVX2 intrinsics to ISD opcodes during lowering instead of pattern matching the intrinsics. This unifies handling with AVX512 and allows these intrinsics to select EVEX encoded instructions to increase available registers.
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llvm-svn: 270310
2016-05-21 03:52:28 +00:00
Craig Topper
258f874bb9
[AVX512] Make the permd intrinsics take a 32-bit immediate to match the software spec.
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llvm-svn: 269579
2016-05-14 21:13:20 +00:00
Elena Demikhovsky
e79b716daf
Fixed lowering of _comi_ intrinsics from all sets - SSE/SSE2/AVX/AVX-512
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Differential revision http://reviews.llvm.org/D19261
llvm-svn: 269569
2016-05-14 15:06:09 +00:00
Craig Topper
d8a9c0d120
[AVX512] Fix types for pshufd intrinsics. The immediate is the second argument and the mask is the 4th argument. Also move the 128/256 tests to the right test file.
...
Prior to this the immediate was a strange 16-bits and the 512-bit intrinsic couldn't receive the full 16 mask bits it needs.
llvm-svn: 269526
2016-05-14 00:47:18 +00:00
Simon Pilgrim
cd0dfc93eb
[X86][SSE] Support for MOVMSK signbit extraction instructions
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Add support for lowering with the MOVMSK instruction to extract vector element signbits to a GPR.
This is an early step towards more optimal handling of vector comparison results.
Differential Revision: http://reviews.llvm.org/D18741
llvm-svn: 265266
2016-04-03 18:22:03 +00:00
Simon Pilgrim
572ca71573
[X86][XOP] Support for VPPERM byte shuffle instruction
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This patch begins adding support for lowering to the XOP VPPERM instruction - adding the X86ISD::VPPERM opcode.
Differential Revision: http://reviews.llvm.org/D18189
llvm-svn: 264260
2016-03-24 11:52:43 +00:00
Simon Pilgrim
abcee45b7a
[X86][AVX] Better support for the variable mask form of VPERMILPD/VPERMILPS
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The variable mask form of VPERMILPD/VPERMILPS were only partially implemented, with much of it still performed as an intrinsic.
This patch properly defines the instructions in terms of X86ISD::VPERMILPV, permitting the opcode to be easily combined as a target shuffle.
Differential Revision: http://reviews.llvm.org/D17681
llvm-svn: 262635
2016-03-03 18:13:53 +00:00
Michael Zuckerman
c4d054fa4a
[LLVM][AVX512] PSRLWI Chnage imm8 to int
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Differential Revision: http://reviews.llvm.org/D17753
llvm-svn: 262592
2016-03-03 08:54:05 +00:00
Michael Zuckerman
927fdaee88
[LLVM][AVX512]PSRAWI Change imm8 to int.
...
Differential Revision: http://reviews.llvm.org/D17705
llvm-svn: 262480
2016-03-02 12:05:07 +00:00
Michael Zuckerman
433b241570
[LLVM][AVX512] PSRL{DI|QI} Change imm8 to int
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Differential Revision: http://reviews.llvm.org/D17713
llvm-svn: 262353
2016-03-01 17:46:32 +00:00
Michael Zuckerman
7878888690
[AVX512][PSRAQ][PSRAD] Change imm8 to int.
...
Differential Revision: http://reviews.llvm.org/D17692
llvm-svn: 262320
2016-03-01 11:36:23 +00:00
Michael Zuckerman
96836fc81c
[AVX512][PSLLW ][PSLLV] Change imm8 to int
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Differential Revision: http://reviews.llvm.org/D17684
llvm-svn: 262176
2016-02-28 07:32:10 +00:00
Simon Pilgrim
3b42ca0760
Strip trailing whitespace. NFCI.
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llvm-svn: 262131
2016-02-27 11:49:16 +00:00
Michael Zuckerman
a1f2d27da2
[LLVM][AVX512][PSHUFHW ][PSHUFLW ] Change imm8 to int
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Differential Revision: http://reviews.llvm.org/D17538
llvm-svn: 261725
2016-02-24 08:39:05 +00:00
Michael Zuckerman
724dc3b20c
[AVX512][PRORQ][PRORD] Change imm8 to int
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Differential Revision: http://reviews.llvm.org/D17024
llvm-svn: 261198
2016-02-18 09:52:12 +00:00
Ahmed Bougacha
f3cccab1e0
[X86] Remove the now-unused X86ISD::PSIGN. NFC.
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llvm-svn: 261025
2016-02-16 22:14:12 +00:00
Michael Zuckerman
529c27f408
[AVX512][PROLQ][PROLD] Change imm8 to int
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Differential Revision: http://reviews.llvm.org/D16983
llvm-svn: 260101
2016-02-08 15:13:32 +00:00
Asaf Badouh
ad5c3fc47d
[X86][AVX512] add intrinsics of Scalar FP to integer conversion with rounding mode
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Differential Revision: http://reviews.llvm.org/D16629
llvm-svn: 260033
2016-02-07 14:59:13 +00:00
Igor Breger
0aeda37464
AVX512: VPBROADCASTB/W/D/Q from GPR intrinsics implementation.
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Differential Revision: http://reviews.llvm.org/D16813
llvm-svn: 260024
2016-02-07 08:30:50 +00:00
Michael Zuckerman
7d73360479
[AVX512] add vfmadd132ss and vfmadd132sd Intrinsic
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Differential Revision: http://reviews.llvm.org/D16589
llvm-svn: 259789
2016-02-04 14:41:08 +00:00
Asaf Badouh
5a3a0231f4
[X86][AVX512VBMI] add encoding and intrinsics for Multishift
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Differential Revision: http://reviews.llvm.org/D16399
llvm-svn: 259363
2016-02-01 15:48:21 +00:00
Asaf Badouh
42852d99e7
[X86][AVX512] small fix in ptestm intrinsics
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move ptestm{q|d} intrinsics from patterns form (in td file) to the intrinsics table
Differential Revision: http://reviews.llvm.org/D16633
llvm-svn: 259029
2016-01-28 08:33:22 +00:00
Benjamin Kramer
391be792f2
One more batch of self-containing headers.
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llvm-svn: 258974
2016-01-27 19:29:56 +00:00
Reid Kleckner
86ff2689a5
Sort intrinsics by LLVM intrinsic name, rather than tablegen def name
...
Step one towards using a simple binary search to lookup intrinsic IDs
instead of our crazy table generated switch+memcmp+startswith code that
makes Function.cpp take about a minute to compile. See PR24785 and
PR11951 for why we should do this.
The X86 backend contains tables that need to be sorted on intrinsic ID,
so reorder those.
llvm-svn: 258757
2016-01-26 00:55:00 +00:00
Michael Zuckerman
1bd7f993fc
[AVX512] Adding PTESTNMB/D/W/Q instruction
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Differential Revision: http://reviews.llvm.org/D16520
llvm-svn: 258688
2016-01-25 14:43:23 +00:00
Michael Zuckerman
19670d479a
[AVX512] Adding PTESTMB/W/D/Q instruction
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Differential Revision: http://reviews.llvm.org/D16519
llvm-svn: 258686
2016-01-25 13:27:32 +00:00
Asaf Badouh
655822ab7e
[X86][IFMA] adding intrinsics and encoding for multiply and add of unsigned 52bit integer
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VPMADD52LUQ - Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Qword Accumulators
VPMADD52HUQ - Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to 64-bit Accumulators
Differential Revision: http://reviews.llvm.org/D16407
llvm-svn: 258680
2016-01-25 11:14:24 +00:00
Igor Breger
1e5bafbc82
AVX512: VMOVDQU8/16/32/64 (load) intrinsic implementation.
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Differential Revision: http://reviews.llvm.org/D16137
llvm-svn: 258657
2016-01-24 08:04:33 +00:00
Igor Breger
7a000f5bb2
AVX512: Masked move intrinsic implementation.
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Implemented intrinsic for the follow instructions (reg move) : VMOVDQU8/16, VMOVDQA32/64, VMOVAPS/PD.
Differential Revision: http://reviews.llvm.org/D16316
llvm-svn: 258398
2016-01-21 14:18:11 +00:00
Michael Zuckerman
21a30a42a9
[AVX512] Adding VPERMT2B and VPERMI2B Intrinsics
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Differential Revision: http://reviews.llvm.org/D16398
llvm-svn: 258397
2016-01-21 13:36:01 +00:00
Michael Zuckerman
65c40afb03
[AVX512] Adding VPERMB Intrinsics
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Differential Revision: http://reviews.llvm.org/D16296
llvm-svn: 258316
2016-01-20 15:24:56 +00:00
Igor Breger
d3341f5021
AVX512: Store (MOVNTPD, MOVNTPS, MOVNTDQ) using non-temporal hint intrinsic implementation.
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Differential Revision: http://reviews.llvm.org/D16350
llvm-svn: 258309
2016-01-20 13:11:47 +00:00
Asaf Badouh
d4a0d9a78c
[X86][AVX512]fix dag & add intrinsics for fixupimm
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cover all width and types (pd/ps/sd/ss) of fixupimm instruction and inrtinsics
Differential Revision: http://reviews.llvm.org/D16313
llvm-svn: 258124
2016-01-19 14:21:39 +00:00
Igor Breger
239fda676c
AVX512: Masked store intrinsic implementation.
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Implemented intrinsic for the follow instructions (store) : VMOVDQU8/16/32/64, VMOVDQA32/64, VMOVAPS/PD, VMOVUPS/PD.
Differential Revision: http://reviews.llvm.org/D16271
llvm-svn: 258047
2016-01-18 13:52:57 +00:00
Michael Zuckerman
ac1b238b0a
[AVX512] Adding VPERMW/D/Q VPERMPS/D Intrinsics
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Differential Revision: http://reviews.llvm.org/D16189
llvm-svn: 258008
2016-01-17 11:33:29 +00:00
Michael Zuckerman
ede597c753
[AVX512] Adding VPERMQ VPERMPD Intrinsics
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Differential Revision: http://reviews.llvm.org/D16194
llvm-svn: 258006
2016-01-17 08:32:14 +00:00
Igor Breger
fc96331d88
AVX512: VMOVDQA32/64 (load) intrinsic implementation.
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Differential Revision: http://reviews.llvm.org/D16142
llvm-svn: 257749
2016-01-14 07:56:04 +00:00
Michael Zuckerman
0e31b22487
[AVX512] Adding PMOVSXBD/W/Q , PMOVZSDQ and PMOVZSWD/Q Intrinsics .
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Differential Revision: http://reviews.llvm.org/D16111
llvm-svn: 257604
2016-01-13 14:59:19 +00:00
Michael Zuckerman
43cea85db9
[AVX512] Adding PMOVZXBD/W/Q , PMOVZXDQ and PMOVZXWD/Q Intrinsics
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Differential Revision:http://reviews.llvm.org/D16071
llvm-svn: 257601
2016-01-13 14:25:21 +00:00
Michael Zuckerman
298a680c80
[AVX512] adding PRORQ , PRORD , PRORLVQ and PRORLVD Intrinsics
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Differential Revision: http://reviews.llvm.org/D16052
llvm-svn: 257594
2016-01-13 12:39:33 +00:00
Michael Zuckerman
2ddcbcf464
[AVX512] adding PROLQ and PROLD Intrinsics
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Differential Revision: http://reviews.llvm.org/D16048
llvm-svn: 257523
2016-01-12 21:19:17 +00:00
Igor Breger
ea8e8e9f97
AVX512: VPMOVAPS/PD and VPMOVUPS/PD (load) intrinsic implementation.
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Differential Revision: http://reviews.llvm.org/D16042
llvm-svn: 257463
2016-01-12 10:02:32 +00:00
Michael Zuckerman
885f61c534
[AVX512] add PRORVQ and PRORVD Intrinsic
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Differential Revision:http://reviews.llvm.org/D15955
llvm-svn: 257283
2016-01-10 09:16:41 +00:00
Michael Zuckerman
3aca221b31
[AVX512] add PSLLW and PSLLV Intrinsic
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Differential Revision: http://reviews.llvm.org/D15889
llvm-svn: 257070
2016-01-07 16:02:51 +00:00
Michael Zuckerman
354152d590
[AVX512] add PSRAV Intrinsic
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Differential Revision: http://reviews.llvm.org/D15856
llvm-svn: 257063
2016-01-07 14:42:20 +00:00
Michael Zuckerman
a6df006b50
[AVX512] add PSHUFHW and PSHUFLW Intrinsic
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Differential Revision: http://reviews.llvm.org/D15925
llvm-svn: 257056
2016-01-07 12:35:43 +00:00
Michael Zuckerman
4a1566827d
[AVX512] add PSHUFD Intrinsic
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Differential Revision: http://reviews.llvm.org/D15934
llvm-svn: 257044
2016-01-07 09:24:12 +00:00
Michael Zuckerman
5cbae95916
[AVX512] add PSLLD and PSLLQ Intrinsic
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Differential Revision: http://reviews.llvm.org/D15885
llvm-svn: 256840
2016-01-05 15:17:39 +00:00
Michael Zuckerman
cf0b6db9ef
[AVX512] add PSRAD and PSRAQ Intrinsic
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Differential Revision: http://reviews.llvm.org/D15851
llvm-svn: 256754
2016-01-04 13:45:45 +00:00
Michael Zuckerman
000fca44a8
[AVX512] add PSRAW Intrinsic
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Differential Revision: http://reviews.llvm.org/D15850
llvm-svn: 256751
2016-01-04 12:50:36 +00:00
Michael Zuckerman
068bc2f219
[AVX512] add PSRLV Intrinsic
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Differential Revision: http://reviews.llvm.org/D15838
llvm-svn: 256747
2016-01-04 11:39:06 +00:00