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Author SHA1 Message Date
Tim Northover fb26d9a286 MIR: remove explicit "noVRegs" property. 
We can infer this from the incoming MIR, so there's no reason to
represent it with a special flag.

llvm-svn: 304246
 2017-05-30 21:28:57 +00:00
Stanislav Mekhanoshin bd5394be3d [AMDGPU] Merge M0 initializations 
Merges equivalent initializations of M0 and hoists them into a common
dominator block. Technically the same code can be used with any
register, physical or virtual.

Differential Revision: https://reviews.llvm.org/D32279

llvm-svn: 301228
 2017-04-24 19:37:54 +00:00