llvm-project

Commit Graph

Author	SHA1	Message	Date
Artyom Skrobov	b43981076a	[ARM] Allow SP in rGPR, starting from ARMv8 Summary: This patch handles assembly and disassembly, but not codegen, as of yet. Additionally, it fixes a bug whereby SP and PC as shifted-reg operands were treated as predictable in ARMv7 Thumb; and it enables the tests for invalid and unpredictable instructions to run on both ARMv7 and ARMv8. Reviewers: jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14141 llvm-svn: 251516	2015-10-28 13:58:36 +00:00
Tim Northover	2fdbdc5870	Fix edge cases of ARM shift operands in arith instructions. As before with load instructions, oddities like "asr #32", "rrx" could be printed incorrectly. Patch by Chris Lidbury. llvm-svn: 164456	2012-09-22 11:18:19 +00:00

Author

SHA1

Message

Date

Artyom Skrobov

b43981076a

[ARM] Allow SP in rGPR, starting from ARMv8

Summary:
This patch handles assembly and disassembly, but not codegen, as of yet.

Additionally, it fixes a bug whereby SP and PC as shifted-reg operands
were treated as predictable in ARMv7 Thumb; and it enables the tests
for invalid and unpredictable instructions to run on both ARMv7 and ARMv8.

Reviewers: jmolloy, rengolin

Subscribers: aemerson, rengolin, llvm-commits

Differential Revision: http://reviews.llvm.org/D14141

llvm-svn: 251516

2015-10-28 13:58:36 +00:00

Tim Northover

2fdbdc5870

Fix edge cases of ARM shift operands in arith instructions.

As before with load instructions, oddities like "asr #32", "rrx" could
be printed incorrectly.

Patch by Chris Lidbury.

llvm-svn: 164456

2012-09-22 11:18:19 +00:00

2 Commits