Commit Graph

6 Commits

Author SHA1 Message Date
Mihai Popa 1c7be576c5 This patch adds support for FPINST/FPINST2 as operands to vmsr/vmrs. These are optional registers that may be supported some ARM implementations to aid with resolution of floating point exceptions. The manual pages for vmsr and vmrs do not detail their use. Encodings and other information can be found in ARM Architecture Reference Manual section F, chapter 6, paragraph 3.
llvm-svn: 183733
2013-06-11 09:39:51 +00:00
Tim Northover 4173e29a98 ARM: add fstmx and fldmx instructions for assembly
These instructions are deprecated oddities, but we still need to be able to
disassemble (and reassemble) them if and when they're encountered.

Patch by Amaury de la Vieuville.

llvm-svn: 183011
2013-05-31 15:55:51 +00:00
Silviu Baranga 9560af848c Fixed disassembler for vstm/vldm ARM VFP instructions.
llvm-svn: 156077
2012-05-03 16:38:40 +00:00
Evan Cheng 8a8e9d1b63 Specify cpu to unbreak tests.
llvm-svn: 155604
2012-04-26 01:38:10 +00:00
Jim Grosbach 3e2c6f380c ARM VLDR/VSTR instructions don't need a size suffix.
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.

llvm-svn: 144583
2011-11-14 23:03:21 +00:00
Owen Anderson 5286bd2d01 Add some more comprehensive VFP decoding tests.
llvm-svn: 137657
2011-08-15 21:29:01 +00:00