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40 Commits

Author SHA1 Message Date
Simon Dardis b3fd189cb5 [mips] Fix aui/daui/dahi/dati for MIPSR6 
For compatiblity with binutils, define these instructions to take
two registers with a 16bit unsigned immediate. Both of the registers
have to be same for dahi and dati.

Reviewers: dsanders, zoran.jovanovic

Differential Review: https://reviews.llvm.org/D21473

llvm-svn: 284218
 2016-10-14 09:31:42 +00:00
Simon Dardis 515e8699f4 [mips] Add IAS support for dvp, evp 
These instructions were only defined for microMIPSR6 previously. Add
definitions for MIPSR6, correct definitions for microMIPSR6, flag these
instructions as having unmodelled side effects (they disable/enable
virtual processors) and add missing disassember tests for microMIPSR6.

Reviewers: vkalintiris

Differential Review: https://reviews.llvm.org/D24291

llvm-svn: 284115
 2016-10-13 12:12:56 +00:00
Simon Dardis e53cfa73e4 Revert "[mips] Fix aui/daui/dahi/dati for MIPSR6" 
This reverts r281724. Still need dsanders to accept this.

llvm-svn: 281726
 2016-09-16 13:56:05 +00:00
Simon Dardis cf060794cd [mips] Fix aui/daui/dahi/dati for MIPSR6 
For compatiblity with binutils, define these instructions to take
two registers with a 16bit unsigned immediate. Both of the registers
have to be same for dahi and dati.

Reviewers: vkalintiris, dsanders, zoran.jovanovic
 
Differential Review: https://reviews.llvm.org/D21473

llvm-svn: 281724
 2016-09-16 13:50:43 +00:00
Hrvoje Varga dbe4d96b4f [mips][microMIPS] Implement DBITSWAP, DLSA and LWUPC and add tests for AUI instructions 
Differential Revision: https://reviews.llvm.org/D16452

llvm-svn: 280909
 2016-09-08 07:41:43 +00:00
Hrvoje Varga f0ed16eae5 [mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations 
Differential Revision: https://reviews.llvm.org/D22667

llvm-svn: 279429
 2016-08-22 12:17:59 +00:00
Hrvoje Varga 846bdb746d [mips][microMIPS] Implement CFC1, CFC2, CTC1 and CTC2 instructions 
Differential Revision: https://reviews.llvm.org/D22347

llvm-svn: 277719
 2016-08-04 11:22:52 +00:00
Zlatko Buljan cba9f80ba8 [mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support 
Differential Revision: http://reviews.llvm.org/D18824

llvm-svn: 275050
 2016-07-11 07:41:56 +00:00
Hrvoje Varga 24b975dc66 [mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV instructions 
Differential Revision: http://reviews.llvm.org/D16625

llvm-svn: 273850
 2016-06-27 08:23:28 +00:00
Hrvoje Varga f1e0a03d08 [mips][micromips] Implement DCLO, DCLZ, DROTR, DROTR32 and DROTRV instructions 
Differential Revision: http://reviews.llvm.org/D16917

llvm-svn: 272876
 2016-06-16 07:06:25 +00:00
Zlatko Buljan d2ed9c6c2c [mips][microMIPS] Add CodeGen support for AND*, OR16, OR*, XOR*, NOT16 and NOR instructions 
Differential Revision: http://reviews.llvm.org/D16719

llvm-svn: 272764
 2016-06-15 07:46:24 +00:00
Zlatko Buljan e663e34e79 [mips][microMIPS] Implement BC1EQZC, BC1NEZC, BC2EQZC and BC2NEZC instructions 
Differential Revision: http://reviews.llvm.org/D18352

llvm-svn: 270030
 2016-05-19 07:31:28 +00:00
Zlatko Buljan 6afea51a58 [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions and add CodeGen support 
Differential Revision: http://reviews.llvm.org/D15418

llvm-svn: 269883
 2016-05-18 06:54:59 +00:00
Hrvoje Varga aeb1fe8f20 [mips][micromips] Implement DSBH, DSHD, DSLL, DSLL32, DSLLV, DSRA, DSRA32 and DSRAV instructions 
Differential Revision: http://reviews.llvm.org/D16800

llvm-svn: 269169
 2016-05-11 11:17:04 +00:00
Zlatko Buljan ba553a6e0a [mips][microMIPS] Implement LWP and SWP instructions 
Differential Revision: http://reviews.llvm.org/D10640

llvm-svn: 268896
 2016-05-09 08:07:28 +00:00
Zlatko Buljan 31c9ebe281 [mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructions 
Differential Revision: http://reviews.llvm.org/D15744

llvm-svn: 268714
 2016-05-06 08:24:14 +00:00
Zlatko Buljan 4807f829b4 [mips][microMIPS] Add CodeGen support for microMIPSr6 ROTR and ROTRV and add tests for LL, SC, SYSCALL, ROTR, ROTRV, LWM32, SWM32 and MOVEP instructions 
Differential Revision: http://reviews.llvm.org/D19857

llvm-svn: 268491
 2016-05-04 12:02:12 +00:00
Zlatko Buljan de0bbe6d1c [mips][microMIPS] Add CodeGen support for SUBU16, SUB, SUBU, DSUB and DSUBU instructions 
Differential Revision: http://reviews.llvm.org/D16676

llvm-svn: 267694
 2016-04-27 11:31:44 +00:00
Zlatko Buljan 29813620bc [mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, SRAV, SRL and SRLV instructions 
Differential Revision: http://reviews.llvm.org/D17989

llvm-svn: 267693
 2016-04-27 11:02:23 +00:00
Zlatko Buljan b43d4bcbd5 [mips][microMIPS] Revert commit r266977 
Commit r266977 was reason for failing LLVM test suite with error message: fatal error: error in backend: Cannot select: t17: i32 = rotr t2, t11 ...

llvm-svn: 267418
 2016-04-25 15:34:57 +00:00
Zlatko Buljan ae720dbbb6 [mips][microMIPS] Implement DVP, EVP and JALRC.HB instructions 
Differential Revision: http://reviews.llvm.org/D18687

llvm-svn: 267114
 2016-04-22 06:44:34 +00:00
Zoran Jovanovic 9360c10a88 [mips][microMIPS] Implement ldpc instruction 
Differential Revision: http://reviews.llvm.org/D15009

llvm-svn: 266990
 2016-04-21 14:32:12 +00:00
Zlatko Buljan dd4151504a [mips][microMIPS] Implement TLBP, TLBR, TLBWI and TLBWR instructions 
Differential Revision: http://reviews.llvm.org/D18855

llvm-svn: 266980
 2016-04-21 11:32:40 +00:00
Zlatko Buljan d370f440e2 [mips][microMIPS] Implement LL, SC, MOVEP, ROTR, ROTRV and SYSCALL instructions and add tests for LWM32 and SWM32 
Differential Revision: http://reviews.llvm.org/D19150

llvm-svn: 266977
 2016-04-21 11:01:51 +00:00
Zlatko Buljan 58d6a959be [mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, DDIVU and DMODU instructions 
Differential Revision: http://reviews.llvm.org/D17137

This patch was reverted after the revertion of dependant patch http://reviews.llvm.org/D17068.
There was the problem with test-suite failure.
The problem is hopefully solved with dependant patch so this patch is commited again.

llvm-svn: 266179
 2016-04-13 08:02:26 +00:00
Zlatko Buljan 53a037f5cc [mips][microMIPS] Add CodeGen support for ADD, ADDIU*, ADDU* and DADD* instructions 
Differential Revision: http://reviews.llvm.org/D16454

llvm-svn: 265772
 2016-04-08 07:27:26 +00:00
Zoran Jovanovic 2b7cc5a4ae [mips][microMIPS] Revert commits r264245 and r264248. 
Commit r264245 was the reason for failing tests in LLVM test suite.
Commit r264248 depends on the first one.

llvm-svn: 265249
 2016-04-02 23:06:13 +00:00
Zlatko Buljan 6221be8e46 [mips][microMIPS] Implement MFC*, MFHC* and DMFC* instructions 
Differential Revision: http://reviews.llvm.org/D17334

llvm-svn: 265002
 2016-03-31 08:51:24 +00:00
Zlatko Buljan 94af4cbcf4 [mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, DDIVU and DMODU instructions 
Differential Revision: http://reviews.llvm.org/D17137

llvm-svn: 264248
 2016-03-24 09:22:45 +00:00
Hrvoje Varga 2cb74ac3c3 [mips][microMIPS] Implement MTC*, MTHC* and DMTC* instructions 
Differential Revision: http://reviews.llvm.org/D17328

llvm-svn: 264246
 2016-03-24 08:02:09 +00:00
Daniel Sanders 03a8d2f8ec [mips] Range check uimm20 and fixed a bug this revealed. 
Summary:
The bug was that dextu's operand 3 would print 0-31 instead of 32-63 when
printing assembly. This came up when replacing
MipsInstPrinter::printUnsignedImm() with a version that could handle arbitrary
bit widths.

MipsAsmPrinter::printUnsignedImm*() don't seem to be used so they have been
removed.

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D15521

llvm-svn: 262231
 2016-02-29 16:06:38 +00:00
Hrvoje Varga 46458d0bcc [mips][microMIPS] Implement DINSU, DINSM, DINS instructions 
Differential Revision: http://reviews.llvm.org/D16181

llvm-svn: 261860
 2016-02-25 12:53:29 +00:00
Zlatko Buljan f034021443 [mips][microMIPS] Implement TLBINV and TLBINVF instructions 
Differential Revision: http://reviews.llvm.org/D16849

llvm-svn: 261211
 2016-02-18 14:10:52 +00:00
Zlatko Buljan 5da2f6cd03 [mips][microMIPS] Implement DERET and DI instructions and check size operand for EXT and DEXT* instructions 
Differential Revision: http://reviews.llvm.org/D15570

llvm-svn: 256152
 2015-12-21 13:08:58 +00:00
Zlatko Buljan 48f1f39bfe Revert r254897 "[mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions" 
Commited patch was intended to implement LH, LHE, LHU and LHUE instructions.
After commit test-suite failed with error message in the form of:
fatal error: error in backend: Cannot select: t124: i32,ch = load<LD2[%d](tbaa=<0x94acc48>), sext from i16> t0, t2, undef:i32
For that reason I decided to revert commit r254897 and make new patch which besides implementation and standard regression tests will also have dedicated tests (CodeGen) for the above error. 

llvm-svn: 255109
 2015-12-09 13:07:45 +00:00
Zlatko Buljan 1a01c15027 [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions 
Differential Revision: http://reviews.llvm.org/D9824

llvm-svn: 254897
 2015-12-07 08:29:31 +00:00
Hrvoje Varga e51b0e13f3 [mips][microMIPS] Implement RECIP.fmt, RINT.fmt, ROUND.L.fmt, ROUND.W.fmt, SEL.fmt, SELEQZ.fmt, SELNEQZ.fmt and CLASS.fmt 
Differential Revision: http://reviews.llvm.org/D13885

llvm-svn: 254405
 2015-12-01 11:59:21 +00:00
Zlatko Buljan 797c2aec6b [mips][microMIPS] Implement LWM16, SB16, SH16, SW16, SWSP and SWM16 instructions 
Differential Revision: http://reviews.llvm.org/D11406

llvm-svn: 252885
 2015-11-12 13:21:33 +00:00
Hrvoje Varga 3a3c4b8a39 [mips][microMIPS] Implement BREAK16, LI16, MOVE16, SDBBP16, SUBU16 and XOR16 instructions 
Differential Revision: http://reviews.llvm.org/D11292#inline-103143

llvm-svn: 250381
 2015-10-15 08:39:07 +00:00
Daniel Sanders d245267be0 [mips][disassembler] Merged disassembler tests into the corresponding ISA/ASE subdirectories. 
llvm-svn: 249384
 2015-10-06 10:02:35 +00:00