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253 Commits

Author SHA1 Message Date
Zlatko Buljan 53a037f5cc [mips][microMIPS] Add CodeGen support for ADD, ADDIU*, ADDU* and DADD* instructions 
Differential Revision: http://reviews.llvm.org/D16454

llvm-svn: 265772
 2016-04-08 07:27:26 +00:00
Zoran Jovanovic 2b7cc5a4ae [mips][microMIPS] Revert commits r264245 and r264248. 
Commit r264245 was the reason for failing tests in LLVM test suite.
Commit r264248 depends on the first one.

llvm-svn: 265249
 2016-04-02 23:06:13 +00:00
Zlatko Buljan 6221be8e46 [mips][microMIPS] Implement MFC*, MFHC* and DMFC* instructions 
Differential Revision: http://reviews.llvm.org/D17334

llvm-svn: 265002
 2016-03-31 08:51:24 +00:00
Zlatko Buljan 94af4cbcf4 [mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, DDIVU and DMODU instructions 
Differential Revision: http://reviews.llvm.org/D17137

llvm-svn: 264248
 2016-03-24 09:22:45 +00:00
Hrvoje Varga 2cb74ac3c3 [mips][microMIPS] Implement MTC*, MTHC* and DMTC* instructions 
Differential Revision: http://reviews.llvm.org/D17328

llvm-svn: 264246
 2016-03-24 08:02:09 +00:00
Daniel Sanders 03a8d2f8ec [mips] Range check uimm20 and fixed a bug this revealed. 
Summary:
The bug was that dextu's operand 3 would print 0-31 instead of 32-63 when
printing assembly. This came up when replacing
MipsInstPrinter::printUnsignedImm() with a version that could handle arbitrary
bit widths.

MipsAsmPrinter::printUnsignedImm*() don't seem to be used so they have been
removed.

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D15521

llvm-svn: 262231
 2016-02-29 16:06:38 +00:00
Hrvoje Varga 46458d0bcc [mips][microMIPS] Implement DINSU, DINSM, DINS instructions 
Differential Revision: http://reviews.llvm.org/D16181

llvm-svn: 261860
 2016-02-25 12:53:29 +00:00
Zlatko Buljan f034021443 [mips][microMIPS] Implement TLBINV and TLBINVF instructions 
Differential Revision: http://reviews.llvm.org/D16849

llvm-svn: 261211
 2016-02-18 14:10:52 +00:00
Daniel Sanders f8bb23e509 [mips] Range check uimm16 and fix several bugs this revealed. 
Summary:
The bugs were:
* teq and similar take 4-bit unsigned immediates on microMIPS.
* teqi and similar have side-effects like teq do.
* shll_s.w and shra_r.w take 5-bit unsigned immediates.
* The various DSP ext* instructions take a 5-bit immediate.
* repl.qh takes an 8-bit unsigned immediate.
* repl.ph takes a 10-bit unsigned immediate.
* rddsp/wrdsp take a 10-bit unsigned immediate.
* teqi and similar take signed 16-bit immediates (10-bit for microMIPS).
* Out-of-range immediate macros for or/xor take a simm32/simm64 depending
  on architecture. I'll fix the simm64 case properly when I reach simm32.

lui is a bit more lenient than GAS and accepts signed immediates in addition
to unsigned. This is because MipsMCExpr can produce signed values when
constant folding and it currently lacks a way of knowing it should fold to
an unsigned value.

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D15446

llvm-svn: 259360
 2016-02-01 15:13:31 +00:00
Daniel Sanders 4d32300cfd [mips] Never select JAL for calls to an absolute immediate address. 
Summary:
It actually takes an offset into the current PC-region.

This fixes the 'expr' command in lldb.

Reviewers: vkalintiris, jaydeep, bhushan

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D16054

llvm-svn: 257339
 2016-01-11 15:57:46 +00:00
Dimitry Andric 227b928abc Fix several accidental DOS line endings in source files 
Summary:
There are a number of files in the tree which have been accidentally checked in with DOS line endings.  Convert these to native line endings.

There are also a few files which have DOS line endings on purpose, and I have set the svn:eol-style property to 'CRLF' on those.

Reviewers: joerg, aaron.ballman

Subscribers: aaron.ballman, sanjoy, dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D15848

llvm-svn: 256707
 2016-01-03 17:22:03 +00:00
Zlatko Buljan 5da2f6cd03 [mips][microMIPS] Implement DERET and DI instructions and check size operand for EXT and DEXT* instructions 
Differential Revision: http://reviews.llvm.org/D15570

llvm-svn: 256152
 2015-12-21 13:08:58 +00:00
Zlatko Buljan 252cca555f [mips][microMIPS][DSP] Implement PACKRL.PH, PICK.PH, PICK.QB, SHILO, SHILOV and WRDSP instructions 
Differential Revision: http://reviews.llvm.org/D14429

llvm-svn: 255991
 2015-12-18 08:59:37 +00:00
Zlatko Buljan 48f1f39bfe Revert r254897 "[mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions" 
Commited patch was intended to implement LH, LHE, LHU and LHUE instructions.
After commit test-suite failed with error message in the form of:
fatal error: error in backend: Cannot select: t124: i32,ch = load<LD2[%d](tbaa=<0x94acc48>), sext from i16> t0, t2, undef:i32
For that reason I decided to revert commit r254897 and make new patch which besides implementation and standard regression tests will also have dedicated tests (CodeGen) for the above error. 

llvm-svn: 255109
 2015-12-09 13:07:45 +00:00
Zlatko Buljan 1a01c15027 [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions 
Differential Revision: http://reviews.llvm.org/D9824

llvm-svn: 254897
 2015-12-07 08:29:31 +00:00
Zlatko Buljan 0f1223053c [mips][DSP] Add DSPr1 and DSPr2 tests for the standard encodings 
Differential Revision: http://reviews.llvm.org/D15141

llvm-svn: 254598
 2015-12-03 09:56:39 +00:00
Hrvoje Varga 672b0f5582 [mips][microMIPS] Implement PREPEND, RADDU.W.QB, RDDSP, REPL.PH, REPL.QB, REPLV.PH, REPLV.QB and MTHLIP instructions 
Differential Revision: http://reviews.llvm.org/D14527

llvm-svn: 254496
 2015-12-02 09:31:24 +00:00
Hrvoje Varga e51b0e13f3 [mips][microMIPS] Implement RECIP.fmt, RINT.fmt, ROUND.L.fmt, ROUND.W.fmt, SEL.fmt, SELEQZ.fmt, SELNEQZ.fmt and CLASS.fmt 
Differential Revision: http://reviews.llvm.org/D13885

llvm-svn: 254405
 2015-12-01 11:59:21 +00:00
Hrvoje Varga c03957f049 [mips][microMIPS] Implement LBUX, LHX, LWX, MAQ_S[A].W.PHL, MAQ_S[A].W.PHR, MFHI, MFLO, MTHI and MTLO instructions 
Differential Revision: http://reviews.llvm.org/D14436

llvm-svn: 254297
 2015-11-30 12:58:39 +00:00
Zoran Jovanovic a887b36167 [mips][microMIPS] Fix issue with offset operand of BALC and BC instructions 
Value of offset operand for microMIPS BALC and BC instructions is currently shifted 2 bits, but it should be 1 bit.
Differential Revision: http://reviews.llvm.org/D14770

llvm-svn: 254296
 2015-11-30 12:56:18 +00:00
Zlatko Buljan 56f3b0e410 [mips][microMIPS] Implement PRECR.QB.PH, PRECR_SRA[_R].PH.W, PRECRQ.PH.W, PRECRQ.QB.PH, PRECRQU_S.QB.PH and PRECRQ_RS.PH.W instructions 
Differential Revision: http://reviews.llvm.org/D14605

llvm-svn: 254291
 2015-11-30 08:37:38 +00:00
Hrvoje Varga b65518c15c [mips][microMIPS] Implement MUL[_S].PH, MULEQ_S.W.PHL, MULEQ_S.W.PHR, MULEU_S.PH.QBL, MULEU_S.PH.QBR, MULQ_RS.PH, MULQ_RS.W, MULQ_S.PH and MULQ_S.W instructions 
Differential Revision: http://reviews.llvm.org/D14280

llvm-svn: 253651
 2015-11-20 07:14:52 +00:00
Hrvoje Varga 78409019d9 [mips][microMIPS] Implement DPS.W.PH, DPSQ_S.W.PH, DPSQ_SA.L.W, DPSQX_S.W.PH, DPSQX_SA.W.PH, DPSU.H.QBL, DPSU.H.QBR and DPSX.W.PH instructions 
Differential Revision: http://reviews.llvm.org/D14058

llvm-svn: 253443
 2015-11-18 07:41:35 +00:00
Zlatko Buljan 72a7f9c1f5 [mips][microMIPS] Implement EXTP, EXTPDP, EXTPDPV, EXTPV, EXTR[_RS].W, EXTR_S.H, EXTRV[_RS].W and EXTRV_S.H instructions 
Differential Revision: http://reviews.llvm.org/D14174

llvm-svn: 253332
 2015-11-17 12:54:15 +00:00
Zlatko Buljan 246b21f66a [mips][microMIPS] Implement SUBQ[_S].PH, SUBQ_S.W, SUBQH[_R].PH, SUBQH[_R].W, SUBU[_S].PH, SUBU[_S].QB and SUBUH[_R].QB instructions 
Differential Revision: http://reviews.llvm.org/D14114

llvm-svn: 253329
 2015-11-17 10:11:22 +00:00
Zlatko Buljan 3e0588d033 [mips][microMIPS] Implement PRECEQ.W.PHL, PRECEQ.W.PHR, PRECEQU.PH.QBL, PRECEQU.PH.QBLA, PRECEQU.PH.QBR, PRECEQU.PH.QBRA, PRECEU.PH.QBL, PRECEU.PH.QBLA, PRECEU.PH.QBR and PRECEU.PH.QBRA instructions 
Differential Revision: http://reviews.llvm.org/D14279

llvm-svn: 253326
 2015-11-17 09:43:29 +00:00
Zlatko Buljan d1dea944b1 Added microMIPSDSPr1 assembler and disassembler tests to existing microMIPSDSPr2 test files. 
llvm-svn: 253320
 2015-11-17 07:58:27 +00:00
Zlatko Buljan 32fb5c40d2 [mips][microMIPS] Implement SHRA[_R].PH, SHRAV[_R].PH, SHRAV[_R].QB, SHRAV_R.W, SHRA_R.W, SHRL.PH, SHRL.QB, SHRLV.PH and SHRLV.QB instructions 
Differential Revision: http://reviews.llvm.org/D14010

llvm-svn: 253041
 2015-11-13 13:14:25 +00:00
Zlatko Buljan 797c2aec6b [mips][microMIPS] Implement LWM16, SB16, SH16, SW16, SWSP and SWM16 instructions 
Differential Revision: http://reviews.llvm.org/D11406

llvm-svn: 252885
 2015-11-12 13:21:33 +00:00
Daniel Sanders ea4f653d18 [mips][ias] Range check uimm2 operands and fix a bug this revealed. 
Summary:
The bug was that the MIPS32R6/MIPS64R6/microMIPS32R6 versions of LSA and DLSA
(unlike the MSA version) failed to account for the off-by-one encoding of the
immediate. The range is actually 1..4 rather than 0..3.

Reviewers: vkalintiris

Subscribers: atanasyan, dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D14015

llvm-svn: 252295
 2015-11-06 12:22:31 +00:00
Hrvoje Varga 18148671ee [mips][microMIPS] Implement PAUSE, RDHWR, RDPGPR, SDBBP, SSNOP, SYNC, SYNCI and WAIT instructions 
Differential Revision: http://reviews.llvm.org/D12628

llvm-svn: 251510
 2015-10-28 11:04:29 +00:00
Zlatko Buljan 2cf61020b8 [mips][microMIPS] Implement SHLL.PH, SHLL_S.PH, SHLL.QB, SHLLV.PH, SHLLV_S.PH, SHLLV.QB, SHLLV_S.W, SHLL_S.W, SHRA.QB and SHRA_R.QB instructions 
Differential Revision: http://reviews.llvm.org/D13929

llvm-svn: 251098
 2015-10-23 06:39:29 +00:00
Daniel Sanders 0f596814e9 [mips][msa] Remove copy_u.d and move copy_u.w to MSA64. 
Summary:
The forwards compatibility strategy employed by MIPS is to consider registers
to be infinitely sign-extended. Then on ISA's with a wider register, the result
of existing instructions are sign-extended to register width and zero-extended
counterparts are added. copy_u.w on MSA32 and copy_u.w on MSA64 violate this
strategy and we have therefore corrected the MSA specs to fix this.

We still keep track of sign/zero-extension during legalization but we now
match copy_s.[wd] where required.

No change required to clang since __builtin_msa_copy_u_[wd] will map to
copy_s.[wd] where appropriate for the target.

Reviewers: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D13472

llvm-svn: 250887
 2015-10-21 09:58:54 +00:00
Zlatko Buljan 5292083584 [mips][microMIPS] Implement ADDQ.PH, ADDQ_S.W, ADDQH.PH, ADDQH.W, ADDSC, ADDU.PH, ADDU_S.QB, ADDWC and ADDUH.QB instructions 
Differential Revision: http://reviews.llvm.org/D13130

llvm-svn: 250685
 2015-10-19 07:16:26 +00:00
Zlatko Buljan d0a7d6e4ee [mips][microMIPS] Implement ABSQ.QB, ABSQ_S.PH, ABSQ_S.W, ABSQ_S.QB, INSV, MADD, MADDU, MSUB, MSUBU, MULT and MULTU instructions 
Differential Revision: http://reviews.llvm.org/D13721

llvm-svn: 250683
 2015-10-19 06:34:44 +00:00
Zlatko Buljan 4c4f21b971 Commited two test files which are forgotten during commit of patch for http://reviews.llvm.org/D13376 
llvm-svn: 250512
 2015-10-16 13:03:10 +00:00
Hrvoje Varga 3c88fbd367 [mips][microMIPS] Implement LB, LBE, LBU and LBUE instructions 
Differential Revision: http://reviews.llvm.org/D11633

llvm-svn: 250511
 2015-10-16 12:24:58 +00:00
Zlatko Buljan 54b1eb4c73 [mips][microMIPS] Implement DPA.W.PH, DPAQ_S.W.PH, DPAQ_SA.L.W, DPAQX_S.W.PH, DPAQX_SA.W.PH, DPAU.H.QBL, DPAU.H.QBR and DPAX.W.PH instructions 
Differential Revision: http://reviews.llvm.org/D13376

llvm-svn: 250382
 2015-10-15 08:59:45 +00:00
Hrvoje Varga 3a3c4b8a39 [mips][microMIPS] Implement BREAK16, LI16, MOVE16, SDBBP16, SUBU16 and XOR16 instructions 
Differential Revision: http://reviews.llvm.org/D11292#inline-103143

llvm-svn: 250381
 2015-10-15 08:39:07 +00:00
Hrvoje Varga 3ef4dd7bc8 [mips][microMIPS] Implement LLE and SCE instructions 
Differential Revision: http://reviews.llvm.org/D11630

llvm-svn: 250379
 2015-10-15 08:11:50 +00:00
Hrvoje Varga a766eff5a0 [mips][microMIPS] Implement LWLE, LWRE, SWLE and SWRE instructions 
Differential Revision: http://reviews.llvm.org/D11631

llvm-svn: 250377
 2015-10-15 07:23:06 +00:00
Zoran Jovanovic 2e386d3d07 [mips][micromips] Initial support for micrmomips DSP instructions and addu.qb implementation 
Differential Revision: http://reviews.llvm.org/D12798

llvm-svn: 250058
 2015-10-12 16:07:25 +00:00
Daniel Sanders bb65d730bf [mips][disassembler] Changed CHECK-EB directives to CHECK so div/divu are tested. 
llvm-svn: 249386
 2015-10-06 10:08:14 +00:00
Daniel Sanders d245267be0 [mips][disassembler] Merged disassembler tests into the corresponding ISA/ASE subdirectories. 
llvm-svn: 249384
 2015-10-06 10:02:35 +00:00
Daniel Sanders 31bfdb5a82 [mips][disassembler] Moved DSP tests into proper place and corrected formatting. 
llvm-svn: 249383
 2015-10-06 09:28:48 +00:00
Zoran Jovanovic 5a8dffc618 [mips][microMIPS] Implement JALRC16, JRCADDIUSP and JRC16 instructions 
Differential Revision: http://reviews.llvm.org/D11219

llvm-svn: 249317
 2015-10-05 14:00:09 +00:00
Zoran Jovanovic 2960f3a346 [mips][microMIPS] Implement CACHEE, WRPGPR and WSBH instructions 
Differential Revision: http://reviews.llvm.org/D10337

llvm-svn: 249004
 2015-10-01 12:49:27 +00:00
Daniel Sanders df19a5e605 [mips][microMIPS] Fix an invalid read for lwm32 and reserved reglist values. 
Summary:
Some values of 'reglist' are reserved and cause the disassembler to read past
the end of the Regs array. Treat lwm32's containing reserved values as invalid
instructions.

Reviewers: zoran.jovanovic

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D12959

llvm-svn: 247990
 2015-09-18 14:20:54 +00:00
Zoran Jovanovic 7ba636cb4c [mips][microMIPS] Implement TEQ, TGE, TGEU, TLT, TLTU and TNE instructions 
Differential Revision: http://reviews.llvm.org/D9658

llvm-svn: 247880
 2015-09-17 10:14:09 +00:00
Zoran Jovanovic 6e6a2c9cd7 [mips][microMIPS] Implement PREFX, LHUE, LBE, LBUE, LHE, LWE, SBE, SHE and SWE instructions 
Differential Revision: http://reviews.llvm.org/D9189

llvm-svn: 247780
 2015-09-16 09:14:35 +00:00
Zoran Jovanovic dc4b8c2761 [mips][microMIPS] Fix an issue with disassembling lwm32 instruction 
Fixed microMIPS disassembler crash on test case generated by llvm-mc-fuzzer.
Differential Revision: http://reviews.llvm.org/D12881

llvm-svn: 247698
 2015-09-15 15:21:27 +00:00
Zoran Jovanovic 7beb737b46 [mips][microMIPS] Implement CACHEE and PREFE instructions for microMIPS32r6 
Differential Revision: http://reviews.llvm.org/D11632

llvm-svn: 247670
 2015-09-15 10:05:10 +00:00
Daniel Sanders e4e83a7bc1 [mips] Added support for various EVA ASE instructions. 
Summary:
Added support for the following instructions:

CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE,
SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF

This required adding some infrastructure for the EVA ASE.

Patch by Scott Egerton.

Reviewers: vkalintiris, dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11139

llvm-svn: 247669
 2015-09-15 10:02:16 +00:00
Daniel Sanders 715f8f1332 [mips] Add missing disassembler tests for MIPS64-MIPS64R5. 
llvm-svn: 247422
 2015-09-11 16:24:11 +00:00
Daniel Sanders 9676db005e [mips] Add missing MIPS32 - MIPS32R5 disassembler tests. 
llvm-svn: 247420
 2015-09-11 15:28:19 +00:00
Daniel Sanders aba4daab10 [mips] Attempt to fix llvm-s390x-linux1 
It doesn't seem to like the '|&' in the test command.

llvm-svn: 247418
 2015-09-11 14:57:54 +00:00
Daniel Sanders 9bbda77006 [mips] Add missing MIPS-IV disassembler tests. 
llvm-svn: 247417
 2015-09-11 14:54:58 +00:00
Daniel Sanders ff338fa355 [mips] Add missing MIPS-III disassembler tests. 
llvm-svn: 247416
 2015-09-11 14:48:46 +00:00
Daniel Sanders 3b571d05f8 [mips] Add missing MIPS-II disassembler tests. 
These tests were found by llvm-mc-fuzzer (see http://reviews.llvm.org/D12723)
and were verified by checking the disassembler output is accepted by GAS.

llvm-svn: 247414
 2015-09-11 14:34:41 +00:00
Daniel Sanders 44c1d0c4f1 Re-commit r247405: [mips] Add missing MIPS-I disassembler tests. 
These tests were found by llvm-mc-fuzzer (see http://reviews.llvm.org/D12723)
and verified by checking the disassembler output is accepted by GAS.

The problematic tests from the previous commit have been moved to
valid-xfail.txt for now.

Also, give invalid instructions some coverage. invalid-xfail.txt contains
instructions that should be invalid but successfully disassemble.

llvm-svn: 247407
 2015-09-11 12:59:03 +00:00
Daniel Sanders c6a2034d0f Revert r247405: [mips] Add missing MIPS-I disassembler tests. 
A small number of the added tests have operands that change on each round trip.

llvm-svn: 247406
 2015-09-11 12:42:38 +00:00
Daniel Sanders f05bf32b38 [mips] Add missing MIPS-I disassembler tests. 
These tests were found by llvm-mc-fuzzer (see http://reviews.llvm.org/D12723)
and verified by checking the disassembler output is accepted by GAS.

llvm-svn: 247405
 2015-09-11 12:24:06 +00:00
Zoran Jovanovic 6b28f09d67 [mips][microMIPS] Implement ADDU16, AND16, ANDI16, NOT16, OR16, SLL16 and SRL16 instructions 
Differential Revision: http://reviews.llvm.org/D11178

llvm-svn: 247146
 2015-09-09 13:55:45 +00:00
Zoran Jovanovic d9790793d6 [mips][microMIPS] Implement CACHEE and PREFE instructions 
Differential Revision: http://reviews.llvm.org/D11628

llvm-svn: 247125
 2015-09-09 09:10:46 +00:00
Zoran Jovanovic 2da1437d62 [mips][microMIPS] Implement LLE, LUI, LW and LWE instructions 
Differential Revision: http://reviews.llvm.org/D1179

llvm-svn: 247017
 2015-09-08 15:02:50 +00:00
Zoran Jovanovic 9eaa30d2bf [mips][microMIPS] Implement SB, SBE, SCE, SH and SHE instructions 
Differential Revision: http://reviews.llvm.org/D11801

llvm-svn: 246999
 2015-09-08 10:18:38 +00:00
Zoran Jovanovic 68be5f21a9 [mips][microMIPS] Add microMIPS32r6 and microMIPS64r6 tests for existing 16-bit LBU16, LHU16, LW16, LWGP and LWSP instructions 
Differential Revision: http://reviews.llvm.org/D10956

llvm-svn: 246987
 2015-09-08 08:25:34 +00:00
Zoran Jovanovic 7b85682541 [mips][microMIPS] Implement ABS.fmt, CEIL.L.fmt, CEIL.W.fmt, FLOOR.L.fmt, FLOOR.W.fmt, TRUNC.L.fmt, TRUNC.W.fmt, RSQRT.fmt and SQRT.fmt instructions 
Differential Revision: http://reviews.llvm.org/D11674

llvm-svn: 246968
 2015-09-07 13:01:04 +00:00
Zoran Jovanovic ada7091812 [mips][microMIPS] Implement BC16, BEQZC16 and BNEZC16 instructions 
Differential Revision: http://reviews.llvm.org/D11181

llvm-svn: 246963
 2015-09-07 11:56:37 +00:00
Zoran Jovanovic 14f308e44f [mips][microMIPS] Implement CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, MAX.fmt, MIN.fmt, MAXA.fmt, MINA.fmt and CMP.condn.fmt instructions 
Differential Revision: http://reviews.llvm.org/D12141

llvm-svn: 246960
 2015-09-07 10:31:31 +00:00
Zoran Jovanovic 89ca2b982e [mips][microMIPS] Implement ADD.fmt, SUB.fmt, MOV.fmt, MUL.fmt, DIV.fmt, MADDF.fmt, MSUBF.fmt and NEG.fmt instructions 
Differential Revision: http://reviews.llvm.org/D11978

llvm-svn: 246919
 2015-09-05 09:25:30 +00:00
Zoran Jovanovic 56585d517b [mips][microMIPS] Add microMIPS32r6 and microMIPS64r6 tests for existing 16-bit ADDIUR1SP, ADDIUR2, ADDIUS5 and ADDIUSP instructions 
Differential Revision: http://reviews.llvm.org/D10955

llvm-svn: 245554
 2015-08-20 11:51:49 +00:00
Zoran Jovanovic 2fe8466f6e [mips][microMIPS] Implement DDIV, DMOD, DDIVU and DMODU instructions 
Differential Revision: http://reviews.llvm.org/D10953

llvm-svn: 245297
 2015-08-18 14:40:43 +00:00
Zoran Jovanovic a6593ff613 [mips][microMIPS] Implement SW and SWE instructions 
Differential Revision: http://reviews.llvm.org/D10869

llvm-svn: 245293
 2015-08-18 12:53:08 +00:00
Zoran Jovanovic 366783e14c [mips][microMIPS] Create microMIPS64r6 subtarget and implement DALIGN, DAUI, DAHI, DATI, DEXT, DEXTM and DEXTU instructions 
Differential Revision: http://reviews.llvm.org/D10923

llvm-svn: 244744
 2015-08-12 12:45:16 +00:00
Vasileios Kalintiris 1c78ca6a09 [mips] Remap move as or. 
Summary:
This patch remaps the assembly idiom 'move' to 'or' instead of 'daddu' or
'addu'. The use of addu/daddu instead of or as move was highlighted as a
performance issue during the analysis of a recent 64bit design. Originally
move was encoded as 'or' by binutils but was changed for the r10k cpu family
due to their pipeline which had 2 arithmetic units and a single logical unit,
and so could issue multiple (d)addu based moves at the same time but only 1
logical move.

This patch preserves the disassembly behaviour so that disassembling a old style
(d)addu move still appears as move, but assembling move always gives an or

Patch by Simon Dardis.

Reviewers: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11796

llvm-svn: 244579
 2015-08-11 08:56:25 +00:00
Vasileios Kalintiris 974d409259 [mips] Added support for the ERETNC instruction. 
Summary: This required adding the instruction predicate HasMips32r5.

Patch by Scott Egerton.

Reviewers: dsanders, vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11136

llvm-svn: 242666
 2015-07-20 12:28:56 +00:00
Zoran Jovanovic 2a47d08afd [mips][microMIPS] Implement SLL and NOP instructions 
http://reviews.llvm.org/D10474

llvm-svn: 241150
 2015-07-01 09:54:51 +00:00
Daniel Sanders b2fa8add82 [mips] Fold duplicate big-endian disassembler tests together. 
llvm-svn: 240887
 2015-06-27 17:56:44 +00:00
Daniel Sanders abe7d840b9 [mips] Sort big-endian disassembler tests by opcode. 
llvm-svn: 240885
 2015-06-27 16:13:59 +00:00
Daniel Sanders de692cae9d [mips] Make little-endian disassembler test filenames consistent. 
Most are named *-el.txt. Renamed the three that were *-le.txt

llvm-svn: 240884
 2015-06-27 15:42:25 +00:00
Daniel Sanders a3134fae17 [mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0. 
Summary:
Previously it (incorrectly) used GPR's.

Patch by Simon Dardis. A couple small corrections by myself.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10567

llvm-svn: 240883
 2015-06-27 15:39:19 +00:00
Zoran Jovanovic 67e04be640 [mips][microMIPS] Implement BREAK, EHB and EI instructions 
http://reviews.llvm.org/D10090

llvm-svn: 240531
 2015-06-24 10:32:16 +00:00
Zoran Jovanovic cdfcbe41f2 [mips][microMIPS] Implement ERET and ERETNC instructions 
http://reviews.llvm.org/D10091

llvm-svn: 239522
 2015-06-11 10:22:46 +00:00
Zoran Jovanovic fcecf26092 [mips][microMIPSr6] Change disassembler tests to one line format 
llvm-svn: 239519
 2015-06-11 09:42:10 +00:00
Zoran Jovanovic 85a53a1ed5 [mips][microMIPSr6] Implement SEB and SEH instructions 
Differential Revision: http://reviews.llvm.org/D9739

llvm-svn: 238333
 2015-05-27 15:39:47 +00:00
Jozef Kolek 888830adfe [mips][microMIPSr6] Implement BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC and BNEZALC instructions 
This patch implements microMIPS32r6 BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC
and BNEZALC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D10031

llvm-svn: 238325
 2015-05-27 14:19:22 +00:00
Zoran Jovanovic dde61c00c3 [mips][microMIPSr6] Implement NOR, OR, ORI, XOR and XORI instructions 
Differential Revision: http://reviews.llvm.org/D8800

llvm-svn: 237697
 2015-05-19 14:12:55 +00:00
Zoran Jovanovic 299fed6b7d [mips][microMIPSr6] Implement AND and ANDI instructions 
Differential Revision: http://reviews.llvm.org/D8772

llvm-svn: 237696
 2015-05-19 13:32:31 +00:00
Zoran Jovanovic 3825261572 [mips][microMIPSr6] Implement DIV, DIVU, MOD and MODU instructions 
Differential Revision: http://reviews.llvm.org/D8769

llvm-svn: 237685
 2015-05-19 11:21:37 +00:00
Jozef Kolek cc0c0fc926 [mips][microMIPSr6] Implement LSA instruction 
This patch implements LSA instruction using mapping.

Differential Revision: http://reviews.llvm.org/D8919

llvm-svn: 237634
 2015-05-18 23:12:10 +00:00
Jozef Kolek cbb227b48d [mips][microMIPSr6] Implement ALIGN and AUI instructions 
This patch implements ALIGN and AUI instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8782

llvm-svn: 237563
 2015-05-18 11:44:30 +00:00
Jozef Kolek 6fec325d10 [mips][microMIPSr6] Implement CLO and CLZ instructions 
This patch implements CLO and CLZ instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8553

llvm-svn: 237257
 2015-05-13 14:18:11 +00:00
Jozef Kolek 38bb81db85 [mips][microMIPSr6] Implement SELEQZ and SELNEZ instructions 
This patch implements SELEQZ and SELNEZ instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8497

llvm-svn: 237158
 2015-05-12 17:39:32 +00:00
Jozef Kolek 8abad7bacc [mips][microMIPSr6] Implement ALUIPC and AUIPC instructions 
This patch implements ALUIPC and AUIPC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8441

llvm-svn: 236858
 2015-05-08 14:25:11 +00:00
Jozef Kolek 9ce6e0a926 [mips][microMIPSr6] Implement ADDIUPC and LWPC instructions 
This patch implements ADDIUPC and LWPC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8415

llvm-svn: 236852
 2015-05-08 13:52:04 +00:00
Jozef Kolek cf98462818 [mips][microMIPSr6] Implement JIALC and JIC instructions 
This patch implements JIALC and JIC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8389

llvm-svn: 236748
 2015-05-07 17:12:23 +00:00
Daniel Sanders 4160c802d9 [mips][msa] Test basic operations for the N32 ABI too. 
Summary:
This required adding instruction aliases for dneg.

N64 will be enabled shortly but requires additional bugfixes.

Reviewers: vkalintiris

Reviewed By: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9341

llvm-svn: 236489
 2015-05-05 08:48:35 +00:00
Daniel Sanders 4d532b5617 [mips] Sorted instructions in mips64r6 disassembly tests. NFC. 
llvm-svn: 236223
 2015-04-30 10:52:42 +00:00
Zoran Jovanovic 387ce30685 [mips][microMIPSr6] Implement MUL, MUH, MULU and MUHU instructions 
Differential Revision: http://reviews.llvm.org/D8894

llvm-svn: 236131
 2015-04-29 17:23:22 +00:00