Commit Graph

266348 Commits

Author SHA1 Message Date
Zachary Turner 8120ebf4c7 [llvm-pdbutil] Add the ability to truncate stream purpose names.
This will be useful for aligning fields to a fixed with in
subsequent patches.

llvm-svn: 307204
2017-07-05 21:54:58 +00:00
Brendon Cahoon cb8c7b912d [DependenceAnalysis] Make sure base objects are the same when comparing GEPs
The dependence analysis was returning incorrect information when using the GEPs
to compute dependences. The analysis uses the GEP indices under certain
conditions, but was doing it incorrectly when the base objects of the GEP are
aliases, but pointing to different locations in the same array.

This patch adds another check for the base objects. If the base pointer SCEVs
are not equal, then the dependence analysis should fall back on the path
that uses the whole SCEV for the dependence check. This fixes PR33567.

Differential Revision: https://reviews.llvm.org/D34702

llvm-svn: 307203
2017-07-05 21:35:47 +00:00
Douglas Gregor c0fe1f211a Fix test case in pre-C++11 mode; address Aaron Ballman's code review.
llvm-svn: 307202
2017-07-05 21:12:37 +00:00
Michael Zolotukhin f70de9caa2 Fix one more reference to lit.util.capture()
The capture method was removed in r306643.

llvm-svn: 307201
2017-07-05 21:06:11 +00:00
Galina Kistanova 0d1990e2e7 Added more info on silent master to the doc.
llvm-svn: 307200
2017-07-05 20:45:44 +00:00
Craig Topper cc418b656a [InstCombine] Use CmpInst::Predicate with m_Cmp instead of ICmpInst::Predicate. NFC
There isn't really an ICmpInst version so we're just accessing the CmpInst version through inheritance.

llvm-svn: 307199
2017-07-05 20:31:00 +00:00
Sam Clegg 9bf73c078b [WebAssembly] Fix types for address taken functions
Differential Revision: https://reviews.llvm.org/D34966

llvm-svn: 307198
2017-07-05 20:25:08 +00:00
Douglas Gregor bb33f57045 Cope with Range-v3's CONCEPT_REQUIRES idiom
llvm-svn: 307197
2017-07-05 20:20:15 +00:00
Douglas Gregor 00fa10b43f Customize the SFINAE diagnostics for enable_if to provide the failed condition.
When enable_if disables a particular overload resolution candidate,
rummage through the enable_if condition to find the specific condition
that caused the failure. For example, if we have something like:

    template<
      typename Iter,
      typename = std::enable_if_t<Random_access_iterator<Iter> &&
                                  Comparable<Iterator_value_type<Iter>>>>
    void mysort(Iter first, Iter last) {}

and we call "mysort" with "std::list<int>" iterators, we'll get a
diagnostic saying that the "Random_access_iterator<Iter>" requirement
failed. If we call "mysort" with
"std::vector<something_not_comparable>", we'll get a diagnostic saying
that the "Comparable<...>" requirement failed.

llvm-svn: 307196
2017-07-05 20:20:14 +00:00
Alexander Shaposhnikov d968f6f423 [tablegen] Avoid creating temporary strings
If a method / function returns a StringRef but the 
variable is of type const std::string& a temporary string is
created (StringRef has a cast operator to std::string),
which is a suboptimal behavior.

Differential revision: https://reviews.llvm.org/D34994

Test plan: make check-all

llvm-svn: 307195
2017-07-05 20:14:54 +00:00
Sam Clegg 8c4baa00de [WebAssembly] MC: Don't generate extra types for weak alias
Previously we were generating a void(void) function type
for a weak alias.  Update the weak-alias test case to
catch this.

Differential Revision: https://reviews.llvm.org/D34734

llvm-svn: 307194
2017-07-05 20:09:26 +00:00
Brian Gesiak bb83ce4678 Add docs for -foptimization-record-file=
Summary: The Clang option was previously not included in the User's Manual.

Reviewers: anemet, davidxl, hfinkel

Reviewed By: hfinkel

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D34928

llvm-svn: 307193
2017-07-05 19:55:51 +00:00
Rafael Espindola 243288a488 Add a test for relocation addend on mips.
An lld test found a bug in a llvm patch I am working on. It is better
to have test coverage for that in llvm too.

llvm-svn: 307192
2017-07-05 19:31:07 +00:00
Eric Beckmann 1d50926e71 Revert "Revert "Replace trivial use of external rc.exe by writing our own .res file.""
This reverts commit 8c8dce3b8f15d6ebaefc35ce88f15a85c8cdbd6e.

llvm-svn: 307191
2017-07-05 19:04:48 +00:00
Eric Beckmann 0eafa581a3 Revert "Revert "Switch external cvtres.exe for llvm's own resource library.""
This reverts commit 165e578e47f1cd38191120aad23a9020fb5476dd.

Forgot to run tests on this.

llvm-svn: 307190
2017-07-05 19:04:33 +00:00
Eric Beckmann 36793a0ecf Revert "Switch external cvtres.exe for llvm's own resource library."
This reverts commit 600d52c278e123dd08bee24c1f00932b55add8de.

This patch still seems to break CrWinClangLLD, reverting until I can
find root problem.

llvm-svn: 307189
2017-07-05 18:59:16 +00:00
Eric Beckmann 8cc9fd31e6 Revert "Replace trivial use of external rc.exe by writing our own .res file."
This patch still seems to break CrWinClangLLD, reverting this once more
until I can discover root problem.

This reverts commit 3dbbc8ce43be50ffde2b1c655c6d3a25796fe78b.

llvm-svn: 307188
2017-07-05 18:59:01 +00:00
Zachary Turner eae44dfee9 [PDB] Add a test that verifies every known type record.
We had a lot of one-off tests for this type and that type,
or "every type that happens to be generated by this program
I built".  Eventually I got a bug report filed where we were
crashing on a type that was not covered by any of these tests.
So this test carefully constructs a minimal C++ program that
will cause every type we support to be emitted.  This ensures
full coverage for type records.

Differential Revision: https://reviews.llvm.org/D34915

llvm-svn: 307187
2017-07-05 18:43:25 +00:00
Quentin Colombet f3f7d4d64b [AMDGPU] Move GISel accessor initialization from TargetMachine to Subtarget.
NFC

llvm-svn: 307186
2017-07-05 18:40:56 +00:00
Sean Fertile 3cd1a0368c [Power9] Disable removing extra swaps on P9.
On power 8 we sometimes insert swaps to deal with the difference between
Little-Endian and Big-Endian. The swap removal pass is supposed to clean up
these swaps. On power 9 we don't need this pass since we do not need to insert
the swaps in the first place.

Commiting on behalf of Stefan Pintilie.
Differential Revision: https://reviews.llvm.org/D34627

llvm-svn: 307185
2017-07-05 18:37:10 +00:00
Simon Pilgrim ac78daf517 {DAGCombiner] Fold (rot x, 0) -> x
llvm-svn: 307184
2017-07-05 18:27:11 +00:00
Simon Pilgrim 49123d4bb0 [X86] Test bitfield loadstore tests on i686 as well
llvm-svn: 307182
2017-07-05 18:09:30 +00:00
Sean Fertile d44cb1838f [PowerPC] Make sure that we remove dead PHI nodes after the PPCCTRLoops pass.
Commiting on behalf of Stefan Pintilie.
Differential Revision: https://reviews.llvm.org/D34829

llvm-svn: 307180
2017-07-05 17:57:57 +00:00
Andrew Zhogin 45d192823e [DAGCombiner] visitRotate patch to optimize pair of ROTR/ROTL instructions into one with combined shift operand.
For two ROTR operations with shifts C1, C2; combined shift operand will be (C1 + C2) % bitsize.

Differential revision: https://reviews.llvm.org/D12833

llvm-svn: 307179
2017-07-05 17:55:42 +00:00
Rafael Espindola d7faa9165f Merge createOrphanCommands into addOrphanSections.
This is a bit simpler and avoids a walk over OutputSections.

llvm-svn: 307178
2017-07-05 17:50:43 +00:00
Simon Pilgrim 55006b407b [X86][SSE] Dropped -mcpu from bitcast+setcc mask tests
Use triple and attribute only for consistency

llvm-svn: 307176
2017-07-05 17:30:30 +00:00
Erik Pilkington 4042f3cf8e [Sema] Don't allow -Wunguarded-availability to be silenced with redecls
Differential revision: https://reviews.llvm.org/D33816

llvm-svn: 307175
2017-07-05 17:08:56 +00:00
Tony Jiang aa5a6a1c30 [Power9] Exploit vector extract with variable index.
This patch adds the exploitation for new power 9 instructions which extract
variable elements from vectors:
VEXTUBLX
VEXTUBRX
VEXTUHLX
VEXTUHRX
VEXTUWLX
VEXTUWRX

Differential Revision: https://reviews.llvm.org/D34032
Commit on behalf of Zaara Syeda (syzaara@ca.ibm.com)

llvm-svn: 307174
2017-07-05 16:55:00 +00:00
Singapuram Sanjay Srivallabh 79f13b9a80 Prefix the name of the calling host function in the name of callee GPU kernel
Summary:
Provide more context to the name of a GPU kernel by prefixing its name with the host function that calls it. E.g. The first kernel called by `gemm` would be `FUNC_gemm_KERNEL_0`.

Kernels currently follow the "kernel_#" (# = 0,1,2,3,...) nomenclature. This patch makes it easier to map host caller and device callee, especially when there are many kernels produced by Polly-ACC.

Reviewers: grosser, Meinersbur, bollu, philip.pfaffe, kbarton!

Reviewed By: grosser

Subscribers: nemanjai, pollydev

Tags: #polly

Differential Revision: https://reviews.llvm.org/D33985

llvm-svn: 307173
2017-07-05 16:48:21 +00:00
Erich Keane 7538b35cef Address comments that escaped D33333
Patch By: Jen Yu

Differential Revision:https://reviews.llvm.org/D34671

llvm-svn: 307172
2017-07-05 16:43:45 +00:00
Marshall Clow 52f4f72fa9 Fix a bug in regex_Iterator where it would report zero-length matches forever. Reported as http://llvm.org/PR33681. Thanks to Karen Arutyunov for the report.
llvm-svn: 307171
2017-07-05 16:37:19 +00:00
Kuba Mracek c40ca13519 [lldb] Add a testcase for MainThreadCheckerRuntime plugin
This adds a simple testcase for MainThreadCheckerRuntime. The tool (Main Thread Checker) is only available on Darwin, so the test also detects the presence of libMainThreadChecker.dylib and is skipped if the tool is not available.

llvm-svn: 307170
2017-07-05 16:29:36 +00:00
Tony Jiang 9a91a18110 [Power9] Exploit vector integer extend instructions when indices aren't correct.
This patch adds on to the exploitation added by https://reviews.llvm.org/D33510.
This now catches build vector nodes where the inputs are coming from sign
extended vector extract elements where the indices used by the vector extract
are not correct. We can still use the new hardware instructions by adding a
shuffle to move the elements to the correct indices. I introduced a new PPCISD
node here because adding a vector_shuffle and changing the elements of the
vector_extracts was getting undone by another DAG combine.

Commit on behalf of Zaara Syeda (syzaara@ca.ibm.com)
Differential Revision: https://reviews.llvm.org/D34009

llvm-svn: 307169
2017-07-05 16:00:38 +00:00
Daniel Sanders d560a64e42 [globalisel][tablegen] Fix another unused variable warning introduced by r307159
llvm-svn: 307168
2017-07-05 15:34:16 +00:00
David Blaikie 15309044ba Use LoadedObjectInfoHelper to simplify/delegate the implementation of 'clone'
llvm-svn: 307167
2017-07-05 15:24:42 +00:00
David Blaikie 8713157747 DebugInfo: Generalize LoadedObjectInfoHelper from RuntimeDyld
Make it usable by any class derived (even indirectly) from
LoadedObjectInfo by allowing a custom base class to be specified and
perfect forwarding to the ctor.

llvm-svn: 307166
2017-07-05 15:23:56 +00:00
Siddharth Bhat de0a534c75 [NFC] Fix breaking build by adding REQUIRES: pollyacc
llvm-svn: 307165
2017-07-05 15:20:28 +00:00
Siddharth Bhat 47c7237bd8 [NFC] [ScopInfo] fix warning about construction order
llvm-svn: 307164
2017-07-05 15:07:28 +00:00
Siddharth Bhat a82f2d264a [PPCGCodeGeneration] Teach Polly to start using live range reordering.
Polly did not use PPCG's live range reordering feature. Teach
PPCGCodeGeneration to use this.

Documentation on this is sparse, so much of the code is conservative.

We currently kill all phi nodes in a Scop by appending them to the
must_kill map we pass to PPCG. I do not have a proof of correctness,
but it seems to be intuitively correct.

We also do not handle `array_order`, which, quoting PPCG, is:
PPCG/gpu.h: "Order dependences on non-scalars."
It seems to consist of RAW dependences between arrays. We need to
pass this information for more complex privatization cases.

Differential Revision: https://reviews.llvm.org/D34941

llvm-svn: 307163
2017-07-05 14:57:04 +00:00
Sean Eveson d54759b236 [ELF] Fix nullptr dereference when creating an error message for a synthetic section.
Differential Revision: https://reviews.llvm.org/D34752

llvm-svn: 307162
2017-07-05 14:55:43 +00:00
Pavel Labath ef7aff507b Fix assorted compiler warnings (mismatched signedness and printf specifiers)
llvm-svn: 307161
2017-07-05 14:54:46 +00:00
Pavel Labath d37c946991 Fix "process load" on new android targets
Summary:
On older android targets, we needed a dlopen rename workaround to get
"process load" working. Since API 26 this is not required as the targets
have a proper libdl so with the function names one would expect.

To make this work I've had to remove the const qualifier from the
GetLibdlFunctionDeclarations function (as now the declarations can
depend on the connected target). Since I was already modifying the
prototype (and the lower levels were already converted to StringRef) I
took the oportunity to convert this function as well.

llvm-svn: 307160
2017-07-05 14:54:41 +00:00
Daniel Sanders a6cfce6863 [globalisel][tablegen] Finish fixing compile-time regressions by merging the matcher and emitter state machines.
Summary:
Also, made a few minor tweaks to shave off a little more cumulative memory consumption:
* All rules share a single NewMIs instead of constructing their own. Only one
  will end up using it.
* Use MIs.resize(1) instead of MIs.clear();MIs.push_back(I) and prevent
  GIM_RecordInsn from changing MIs[0].

Depends on D33764

Reviewers: rovka, vitalybuka, ab, t.p.northover, qcolombet, aditya_nandakumar

Reviewed By: ab

Subscribers: kristof.beyls, igorb, llvm-commits

Differential Revision: https://reviews.llvm.org/D33766

llvm-svn: 307159
2017-07-05 14:50:18 +00:00
Dinar Temirbulatov b78adec638 [SLPVectorizer] Add an extra parameter to cancelScheduling function, NFCI.
llvm-svn: 307158
2017-07-05 13:53:03 +00:00
David Green b26a0a460c [IndVarSimplify] Add AShr exact flags using induction variables ranges.
This adds exact flags to AShr/LShr flags where we can statically
prove it is valid using the range of induction variables. This
allows further optimisations to remove extra loads.

Differential Revision: https://reviews.llvm.org/D34207

llvm-svn: 307157
2017-07-05 13:25:58 +00:00
Ulrich Weigand 6d6c4808ef [SystemZ] Simplify handling of ISA revisions
This moves determination of the ISA revision from the CPU name to
one single place, removing a bunch of duplicated code.  It also
makes the supported ISA revisions available as feature strings.

No functional change.

llvm-svn: 307156
2017-07-05 13:19:47 +00:00
Ulrich Weigand 43579cf4a0 [SystemZ] Simplify handling of 128-bit multiply/divide instruction
Several integer multiply/divide instructions require use of a
register pair as input and output.  This patch moves setting
up the input register pair from C++ code to TableGen, simplifying
the whole process and making it more easily extensible.

No functional change.

llvm-svn: 307155
2017-07-05 13:17:31 +00:00
Ulrich Weigand e2a68e96f0 [SystemZ] Small cleanups to SystemZScheduleZ13.td
Fixes a couple of whitespace errors, re-sorts the vector floating-point
instructions to make them more easily extensible, and adds a missing
pseudo instruction.

No functional change.

llvm-svn: 307154
2017-07-05 13:14:43 +00:00
Nirav Dave 65b7ab1be4 [Hexagon] Preclude non-memory test from being optimized away. NFC.
llvm-svn: 307153
2017-07-05 13:08:03 +00:00
Simon Atanasyan 6a9570c282 [driver][mips] Use AddTargetFeature to check arguments and add feature flags. NFC
llvm-svn: 307152
2017-07-05 12:57:37 +00:00