Evan Cheng
|
5bb93ce769
|
Watch out for empty BB.
llvm-svn: 78562
|
2009-08-10 08:10:13 +00:00 |
|
Evan Cheng
|
8a640ae504
|
rev, rev16, and revsh do not set CPSR.
llvm-svn: 78561
|
2009-08-10 07:58:45 +00:00 |
|
Evan Cheng
|
f16a1d5b79
|
Duh. Most 16-bit Thumb rr instructions are two-address. Fix table.
llvm-svn: 78560
|
2009-08-10 07:20:37 +00:00 |
|
Evan Cheng
|
1f5bee14a1
|
CPSR can be livein; transfer predicate operands correctly; tMUL is two-address.
llvm-svn: 78559
|
2009-08-10 06:57:42 +00:00 |
|
Evan Cheng
|
51cbd2d6c4
|
Add support to reduce most of 32-bit Thumb2 arithmetic instructions.
llvm-svn: 78550
|
2009-08-10 02:37:24 +00:00 |
|
Evan Cheng
|
d461c1c559
|
Add support to convert 32-bit instructions to 16-bit non-two-address ones.
llvm-svn: 78540
|
2009-08-09 19:17:19 +00:00 |
|
Evan Cheng
|
1be453b462
|
Add a skeleton Thumb2 instruction size reduction pass.
llvm-svn: 78456
|
2009-08-08 03:21:23 +00:00 |