This fixes the following two warnings in code that's only compiled on
arm64:
- warning: cast from 'const void *' to 'unsigned char *' drops const
qualifier [-Wcast-qual]
- warning: embedding a directive within macro arguments has undefined
behavior [-Wembedded-directive]
A lot of comments in LLDB are surrounded by an ASCII line to delimit the
begging and end of the comment.
Its use is not really consistent across the code base, sometimes the
lines are longer, sometimes they are shorter and sometimes they are
omitted. Furthermore, it looks kind of weird with the 80 column limit,
where the comment actually extends past the line, but not by much.
Furthermore, when /// is used for Doxygen comments, it looks
particularly odd. And when // is used, it incorrectly gives the
impression that it's actually a Doxygen comment.
I assume these lines were added to improve distinguishing between
comments and code. However, given that todays editors and IDEs do a
great job at highlighting comments, I think it's worth to drop this for
the sake of consistency. The alternative is fixing all the
inconsistencies, which would create a lot more churn.
Differential revision: https://reviews.llvm.org/D60508
llvm-svn: 358135
to reflect the new license.
We understand that people may be surprised that we're moving the header
entirely to discuss the new license. We checked this carefully with the
Foundation's lawyer and we believe this is the correct approach.
Essentially, all code in the project is now made available by the LLVM
project under our new license, so you will see that the license headers
include that license only. Some of our contributors have contributed
code under our old license, and accordingly, we have retained a copy of
our old license notice in the top-level files in each project and
repository.
llvm-svn: 351636
This renames the LLDB error class to Status, as discussed
on the lldb-dev mailing list.
A change of this magnitude cannot easily be done without
find and replace, but that has potential to catch unwanted
occurrences of common strings such as "Error". Every effort
was made to find all the obvious things such as the word "Error"
appearing in a string, etc, but it's possible there are still
some lingering occurences left around. Hopefully nothing too
serious.
llvm-svn: 302872
*** to conform to clang-format’s LLVM style. This kind of mass change has
*** two obvious implications:
Firstly, merging this particular commit into a downstream fork may be a huge
effort. Alternatively, it may be worth merging all changes up to this commit,
performing the same reformatting operation locally, and then discarding the
merge for this particular commit. The commands used to accomplish this
reformatting were as follows (with current working directory as the root of
the repository):
find . \( -iname "*.c" -or -iname "*.cpp" -or -iname "*.h" -or -iname "*.mm" \) -exec clang-format -i {} +
find . -iname "*.py" -exec autopep8 --in-place --aggressive --aggressive {} + ;
The version of clang-format used was 3.9.0, and autopep8 was 1.2.4.
Secondly, “blame” style tools will generally point to this commit instead of
a meaningful prior commit. There are alternatives available that will attempt
to look through this change and find the appropriate prior commit. YMMV.
llvm-svn: 280751
debugserver to match. "gcc" is now "ehframe" and "gdb" is now
"debugserver". Because this is debugserver, what we call the Process
Plugin register numbers up in lldb are the debugserver register
numbers down here - they are the register numbers that debugserver
will use to refer to these registers over the gdb-remote protocol.
debugserver was already reporting the registers with the key
"ehframe"; this change is just cleaning up the internal variable
names to match.
llvm-svn: 247751
Summary:
This replaces (void)x; usages where they x was subsequently
involved in an assertion with this macro to make the
intent more clear.
Reviewers: clayborg
Subscribers: lldb-commits
Differential Revision: http://reviews.llvm.org/D11451
llvm-svn: 243074
the register state when debugging AArch32 programs (armv7
programs running on an armv8 processor). Most notably,
there is no "fpscr" register in the register context -
there is an fpsr and an fpcr.
Also fix a bug where the floating point values could not
be written in armv7 processes.
<rdar://problem/18977767>
llvm-svn: 226244
The issue with Thumb IT (if/then) instructions is the IT instruction preceeds up to four instructions that are made conditional. If a breakpoint is placed on one of the conditional instructions, the instruction either needs to match the thumb opcode size (2 or 4 bytes) or a BKPT instruction needs to be used as these are always unconditional (even in a IT instruction). If BKPT instructions are used, then we might end up stopping on an instruction that won't get executed. So if we do stop at a BKPT instruction, we need to continue if the condition is not true.
When using the BKPT isntructions are easy in that you don't need to detect the size of the breakpoint that needs to be used when setting a breakpoint even in a thumb IT instruction. The bad part is you will now always stop at the opcode location and let LLDB determine if it should auto-continue. If the BKPT instruction is used, the BKPT that is used for ARM code should be something that also triggers the BKPT instruction in Thumb in case you set a breakpoint in the middle of code and the code is actually Thumb code. A value of 0xE120BE70 will work since the lower 16 bits being 0xBE70 happens to be a Thumb BKPT instruction.
The alternative is to use trap or illegal instructions that the kernel will translate into breakpoint hits. On Mac this was 0xE7FFDEFE for ARM and 0xDEFE for Thumb. The darwin kernel currently doesn't recognize any 32 bit Thumb instruction as a instruction that will get turned into a breakpoint exception (EXC_BREAKPOINT), so we had to use the BKPT instruction on Mac. The linux kernel recognizes a 16 and a 32 bit instruction as valid thumb breakpoint opcodes. The benefit of using 16 or 32 bit instructions is you don't stop on opcodes in a IT block when the condition doesn't match.
To further complicate things, single stepping on ARM is often implemented by modifying the BCR/BVR registers and setting the processor to stop when the PC is not equal to the current value. This means single stepping is another way the ARM target can stop on instructions that won't get executed.
This patch does the following:
1 - Fix the internal debugserver for Apple to use the BKPT instruction for ARM and Thumb
2 - Fix LLDB to catch when we stop in the middle of a Thumb IT instruction and continue if we stop at an instruction that won't execute
3 - Fixes this in a way that will work for any target on any platform as long as it is ARM/Thumb
4 - Adds a patch for ignoring conditions that don't match when in ARM mode (see below)
This patch also provides the code that implements the same thing for ARM instructions, though it is disabled for now. The ARM patch will check the condition of the instruction in ARM mode and continue if the condition isn't true (and therefore the instruction would not be executed). Again, this is not enable, but the code for it has been added.
<rdar://problem/19145455>
llvm-svn: 223851
Replace adhoc inline implementation of llvm::array_lengthof in favour of the
implementation in LLVM. This is simply a cleanup change, no functional change
intended.
llvm-svn: 211868
These changes were written by Greg Clayton, Jim Ingham, Jason Molenda.
It builds cleanly against TOT llvm with xcodebuild. I updated the
cmake files by visual inspection but did not try a build. I haven't
built these sources on any non-Mac platforms - I don't think this
patch adds any code that requires darwin, but please let me know if
I missed something.
In debugserver, MachProcess.cpp and MachTask.cpp were renamed to
MachProcess.mm and MachTask.mm as they picked up some new Objective-C
code needed to launch processes when running on iOS.
llvm-svn: 205113
Added two new GDB server packets to debugserver: "QSaveRegisterState" and "QRestoreRegiterState".
"QSaveRegisterState" makes the remote GDB server save all register values and it returns a save identifier as an unsigned integer. This packet can be used prior to running expressions to save all registers.
All registers can them we later restored with "QRestoreRegiterState:SAVEID" what SAVEID is the integer identifier that was returned from the call to QSaveRegisterState.
Cleaned up redundant code in lldb_private::Thread, lldb_private::ThreadPlanCallFunction.
Moved the lldb_private::Thread::RegisterCheckpoint into its own header file and it is now in the lldb_private namespace. Trimmed down the RegisterCheckpoint class to omit stuff that wasn't used (the stack ID).
Added a few new virtual methods to lldb_private::RegisterContext that allow subclasses to efficiently save/restore register states and changed the RegisterContextGDBRemote to take advantage of these new calls.
llvm-svn: 194621
- removed all gaps from the g/G packets
- optimized registers for x86_64 to not send/receive xmm0-xmm15 as well as ymm0-ymm15, now we only send ymm0-15 and xmm0-15 are now pseudo regs
- Fixed x86_64 floating point register gaps
- Fixed x86_64 so that xmm8-xmm15 don't overlap with ymm0-ymm3. This could lead to bad values showing in the debugger and was due to bad register info structure contents
- Fixed i386 so we only send ymm0-ymm7 and xmm0-xmm7 are now pseudo regs.
- Fixed ARM register definitions to not have any gaps
- Fixed it so value registers and invalidation registers are specified using register names which avoid games we had to play with register numbering in the ARM plugin.
llvm-svn: 194302
take for threads created while the program is running. Remove the testcase skips from TestConcurrentEvents.py,
since they all pass now, and fix TestWatchpointMultipleThreads.py - which should have caught this problem -
so it doesn't artificially break on new thread creation before the watchpoint triggers.
llvm.org/pr16566
<rdar://problem/14383244>
llvm-svn: 186132
support files for debugserver to fix a build failure for arm. Also
remove some of the code used for software-driven single instruction
stepping; this is slowly being yanked out and these particular bits
overlap with the nub_break_t going away.
llvm-svn: 184828
Drop the old f registers from debugserver's register list. Add the
NEON 128-bit q registers to debugserver, support reading and writing.
Add the new contains / invalidates mappings for the s, d, and q
registers so lldb will know what registers overlay what other registers.
Change the default format of s and d registers to be floating point
instead of hex. Remove some UTF-8 hyphen chars in comments in the ARM
register number definition headers.
<rdar://problem/13121797>
llvm-svn: 176915
own port namepsace) as the thread identifier to using the system-wide
globally unique thread id as the thread identifier number.
MachThread.cpp keeps both the unique id and the mach port number
for each thread. All layers outside MachThread class use the unique
id with three exceptions: (1) Mach exceptions come in with the port
number (thread_port) which needs to be translated, (2) any calls to
low-level thread_get_state/thread_set_state/thread_suspend etc need
to use the mach port number, (3) MachThreadList::UpdateThreadList
which creates the MachThread objects gets the unique id and passes
it to the MachThread ctor as an argument.
In general, any time nub_thread_t is used, it is now referring to a
unique thread id. Any time a thread_t is used, it is now referring
to a mach port number. There was some interchangability of these
types previously. nub_thread_t has also been changed to a 64-bit
type which necessitated some printf specification string changes.
I haven't been able to test these changes extensively yet but want
to checkpoint the work. The scenarios I've been testing are all
working correctly so while there may be some corner cases I haven't
hit yet, I think it is substantially correct.
<rdar://problem/12931414>
llvm-svn: 175870
We do this by delegating to two available Watchpoint Register Pairs (wvr, wcr). With
each pair handling the 4 bytes of (uint64_t)variable.
llvm-svn: 153300
that the inferior cannot execute past the watchpoint-triggering instruction.
The solution is disable the watchpoint before resuming the inferior and make it hardware single step;
when the inferior stops again due to single step, re-enable the watchpoint and disable the single step
to make the inferior able to continue again without obstacle.
rdar://problem/9667960
llvm-svn: 153273
However, the debugserver cannot get past the instruction which triggered the watchpoint.
So a workaround is in place for the time being which disables the triggered watchpoint
before resuming.
Lots of commented out printf's remain in the source which needs to be cleaned up.
WIP rdar://problem/9667960
llvm-svn: 153228
- If you download and build the sources in the Xcode project, x86_64 builds
by default using the "llvm.zip" checkpointed LLVM.
- If you delete the "lldb/llvm.zip" and the "lldb/llvm" folder, and build the
Xcode project will download the right LLVM sources and build them from
scratch
- If you have a "lldb/llvm" folder already that contains a "lldb/llvm/lib"
directory, we will use the sources you have placed in the LLDB directory.
Python can now be disabled for platforms that don't support it.
Changed the way the libllvmclang.a files get used. They now all get built into
arch specific directories and never get merged into universal binaries as this
was causing issues where you would have to go and delete the file if you wanted
to build an extra architecture slice.
llvm-svn: 143678
parse NOP instructions. I added the new table entries for the NOP for the
plain NOP, Yield, WFE, WFI, and SEV variants. Modified the opcode emulation
function EmulateInstructionARM::EmulateMOVRdSP(...) to notify us when it is
creating a frame. Also added an abtract way to detect the frame pointer
register for both the standard ARM ABI and for Darwin.
Fixed GDBRemoteRegisterContext::WriteAllRegisterValues(...) to correctly be
able to individually write register values back if case the 'G' packet is
not implemented or returns an error.
Modified the StopInfoMachException to "trace" stop reasons. On ARM we currently
use the BVR/BCR register pairs to say "stop when the PC is not equal to the
current PC value", and this results in a EXC_BREAKPOINT mach exception that
has 0x102 in the code.
Modified debugserver to create the short option string from long option
definitions to make sure it doesn't get out of date. The short option string
was missing many of the newer short option values due to a modification of
the long options defs, and not modifying the short option string.
llvm-svn: 131911
Jonas Devlieghere