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Author SHA1 Message Date
Sanjay Patel 68264558f9 [DAGCombiner] try to convert opposing shifts to casts 
This reverses a questionable IR canonicalization when a truncate
is free:

sra (add (shl X, N1C), AddC), N1C -->
sext (add (trunc X to (width - N1C)), AddC')

https://rise4fun.com/Alive/slRC

More details in PR42644:
https://bugs.llvm.org/show_bug.cgi?id=42644

I limited this to pre-legalization for code simplicity because that
should be enough to reverse the IR patterns. I don't have any
evidence (no regression test diffs) that we need to try this later.

Differential Revision: https://reviews.llvm.org/D65607

llvm-svn: 367710
 2019-08-02 19:33:46 +00:00
Sanjay Patel 8560ea5534 [AArch64][x86] adjust tests with shift-add-shift; NFC 
Prevent folding away the math completely.

llvm-svn: 367612
 2019-08-01 21:08:08 +00:00
Sanjay Patel cb3140b7bf [AArch64][x86] add tests for shift-add-shift; NFC (PR42644) 
llvm-svn: 367607
 2019-08-01 20:32:27 +00:00
Eli Friedman 23e60c7893 [AArch64] Add patterns for zext/sext of shift amount. 
Not sure this is the best fix, but it saves an instruction for certain
constructs involving variable shifts.

Differential Revision: https://reviews.llvm.org/D55572

llvm-svn: 351768
 2019-01-22 00:21:35 +00:00
Geoff Berry 98150e3a62 [AArch64] Take advantage of variable shift/rotate amount implicit mod operation. 
Summary:
Optimize code generated for variable shifts/rotates by taking advantage
of the implicit and/mod done on the variable shift amount register.

Resolves bug 27582 and bug 37421.

Reviewers: t.p.northover, qcolombet, MatzeB, javed.absar

Subscribers: rengolin, kristof.beyls, mcrosier, llvm-commits

Differential Revision: https://reviews.llvm.org/D46844

llvm-svn: 333214
 2018-05-24 18:29:42 +00:00