4 Commits

Author	SHA1	Message	Date
Craig Topper	12d0753aca	[RISCV] Use bitsLE instead of strict == MVT::i32 in assertsexti32 and assertzexti32. ... The patterns that use this really want to know if the operand has at least 32 sign/zero bits. This increases opportunities to use W instructions when the original source used i8/i16. Not sure how much this matters for performance, but it makes i8/i16 code more consistent with i32.	2021-01-24 13:58:14 -08:00
Craig Topper	60ebf6408e	[RISCV] Add test cases for missed opportunities to use fcvt.*.w(u) instructions on RV64 when input is known to be extended from i8/i16.	2021-01-24 13:48:29 -08:00
Michael Munday	e28b6a60bc	[RISCV][NFC] Regenerate RISCV CodeGen tests ... Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841	2020-12-09 19:42:49 +00:00
Hsiangkai Wang	f7bc7c2981	[RISCV] Support Zfh half-precision floating-point extension. ... Support "Zfh" extension according to https://github.com/riscv/riscv-isa-manual/blob/zfh/src/zfh.tex Differential Revision: https://reviews.llvm.org/D90738	2020-12-03 09:16:33 +08:00