llvm-project

Commit Graph

Author	SHA1	Message	Date
Craig Topper	efcdd598b7	[RISCV] Teach VSETVLI inserter to use VSETIVLI when possible. We always create the VL operand using a register, but if we can determine that it came from an ADDI X0, imm with a sufficiently small immediate, we can use VSETIVLI. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D97332	2021-02-24 16:07:33 -08:00
Craig Topper	07ca13fe07	[RISCV] Add support for fixed vector mask logic operations. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D96741	2021-02-16 09:34:00 -08:00

Author

SHA1

Message

Date

Craig Topper

efcdd598b7

[RISCV] Teach VSETVLI inserter to use VSETIVLI when possible.

We always create the VL operand using a register, but if we can
determine that it came from an ADDI X0, imm with a sufficiently
small immediate, we can use VSETIVLI.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D97332

2021-02-24 16:07:33 -08:00

Craig Topper

07ca13fe07

[RISCV] Add support for fixed vector mask logic operations.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D96741

2021-02-16 09:34:00 -08:00

2 Commits