llvm-project

Commit Graph

Author	SHA1	Message	Date
Hsiangkai Wang	6e360460f1	[RISCV] Use v8-v23 as argument registers to conform to the proposal. The maximum LMUL is 8. We need 16 vector registers for two LMUL-8 arguments. The modification follows the proposal of psABI in https://github.com/riscv/riscv-elf-psabi-doc/pull/171 Differential Revision: https://reviews.llvm.org/D95134	2021-01-22 07:55:24 +08:00
Fraser Cormack	9ecc991c55	[RISCV] Add scalable vector vselect ISel patterns Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D94294	2021-01-11 22:41:34 +00:00

Author

SHA1

Message

Date

Hsiangkai Wang

6e360460f1

[RISCV] Use v8-v23 as argument registers to conform to the proposal.

The maximum LMUL is 8. We need 16 vector registers for two LMUL-8
arguments. The modification follows the proposal of psABI in
https://github.com/riscv/riscv-elf-psabi-doc/pull/171

Differential Revision: https://reviews.llvm.org/D95134

2021-01-22 07:55:24 +08:00

Fraser Cormack

9ecc991c55

[RISCV] Add scalable vector vselect ISel patterns

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D94294

2021-01-11 22:41:34 +00:00

2 Commits