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Author SHA1 Message Date
Hsiangkai Wang 6e360460f1 [RISCV] Use v8-v23 as argument registers to conform to the proposal. 
The maximum LMUL is 8. We need 16 vector registers for two LMUL-8
arguments. The modification follows the proposal of psABI in
https://github.com/riscv/riscv-elf-psabi-doc/pull/171

Differential Revision: https://reviews.llvm.org/D95134
 2021-01-22 07:55:24 +08:00
Hsiangkai Wang b7ab6726b6 [RISCV] New vector load/store in V extension v1.0 
Upgrade RISC-V V extension to v1.0-08a0b46.
Indexed load/store have ordered and unordered form.
New whole vector load/store.

Differential Revision: https://reviews.llvm.org/D93614
 2021-01-22 07:30:09 +08:00