Commit Graph

6 Commits

Author SHA1 Message Date
David Green d96161a179 [ARM/AArch64] Move REQUIRES after update_cc_test_checks line. NFC
c17d9b4b12 added REQUIRES lines to a lot of Arm and AArch64
test, but added them to the very beginning, before the existing
update_cc_test_checks lines. This just moves them later so as to not
mess up the existing ordering when the checks are regenerated.
2021-11-13 19:09:01 +00:00
Saleem Abdulrasool c17d9b4b12 headers: optionalise some generated resource headers
This splits out the generated headers and conditonalises them upon the
target being enabled.

The motivation here is that the RISCV header alone added 10MB to the
resource directory, which was previously at 10MB, increasing the build
size and time. This header is contributing ~50% of the size of the
resource headers (~10MB).

The ARM generated headers are contributing about ~10% or 1MB.

This could be extended further adding only the static resource headers
for the targets that the LLVM build supports.

The changes to the tests for ARM mirror what the RISCV target already
did and rnk identified as a possible issue.

Testing:
  cmake -G Ninja -D LLVM_TARGETS_TO_BUILD=X86 -D LLVM_ENABLE_PROJECTS="clang;lld" ../clang
  ninja check-clang

Differential Revision: https://reviews.llvm.org/D112890
Reviewed By: craig.topper
2021-11-09 22:30:29 +00:00
Bradley Smith 0ce46a1d43 [AArch64][Driver][SVE] Allow -msve-vector-bits=<n>+ syntax to mean no maximum vscale
This patch splits the existing SveVectorBits LangOpt into VScaleMin and
VScaleMax LangOpts such that we can represent such an option. The cc1
option has also been split into -mvscale-{min,max}=<n> options so that the
cc1 arguments better reflect the vscale_range IR attribute.

Differential Revision: https://reviews.llvm.org/D111790
2021-10-25 11:10:52 +00:00
Joe Ellis 3c696a212b [AArch64][SVE] Allow lax conversion between VLATs and GNU vectors
Previously, lax conversions were only allowed between SVE vector-length
agnostic types and vector-length specific types. This meant that code
such as the following:

    #include <arm_sve.h>
    #define N __ARM_FEATURE_SVE_BITS
    #define FIXED_ATTR __attribute__ ((vector_size (N/8)))
    typedef float fixed_float32_t FIXED_ATTR;

    void foo() {
        fixed_float32_t fs32;
        svfloat64_t s64;
        fs32 = s64;
    }

was not allowed.

This patch makes a minor change to areLaxCompatibleSveTypes to allow for
lax conversions to be performed between SVE vector-length agnostic types
and GNU vectors.

Differential Revision: https://reviews.llvm.org/D91696
2020-11-23 10:47:17 +00:00
Joe Ellis 1d7abcf99e [AArch64][SVE] Add tests for VLST -> VLAT lax conversions
These were previously missing from the SVE lax conversions tests
introduced in this commit:

    23a96b84a8
    (https://reviews.llvm.org/D91067)

Differential Revision: https://reviews.llvm.org/D91642
2020-11-17 18:03:42 +00:00
Joe Ellis 23a96b84a8 [AArch64][SVE] Support implicit lax vector conversions for SVE types
Lax vector conversions was behaving incorrectly for implicit casts
between scalable and fixed-length vector types. For example, this:

    #include <arm_sve.h>

    #define N __ARM_FEATURE_SVE_BITS
    #define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))

    typedef svfloat32_t fixed_float32_t FIXED_ATTR;

    void allowed_depending() {
      fixed_float32_t fs32;
      svfloat64_t s64;

      fs32 = s64;
    }

... would fail because the vectors have differing lane sizes. This patch
implements the correct behaviour for
-flax-vector-conversions={none,all,integer}. Specifically:

- -flax-vector-conversions=none prevents all lax vector conversions
  between scalable and fixed-sized vectors.
- -flax-vector-conversions=integer allows lax vector conversions between
  scalable and fixed-size vectors whose element types are integers.
- -flax-vector-conversions=all allows all lax vector conversions between
  scalable and fixed-size vectors (including those with floating point
  element types).

The implicit conversions are implemented as bitcasts.

Reviewed By: fpetrogalli

Differential Revision: https://reviews.llvm.org/D91067
2020-11-17 14:50:17 +00:00