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4 Commits

Author SHA1 Message Date
Kazushi (Jam) Marukawa 38621c45a8 [VE] Add lvm/svm intrinsic instructions 
Add lvm/svm intrinsic instructions and a regression test.  Change
RegisterInfo to specify that VM0/VMP0 are constant and reserved
registers.  This modifies a vst regression test, so update it.
Also add pseudo instructions for VM512 register classes
and mechanism to expand them after register allocation.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D91541
 2020-11-17 07:05:36 +09:00
Kazushi (Jam) Marukawa 44a4f93925 [VE] Optimize leaf functions 
Optimize leaf functions by not generating save/restore for callee saved
registers.  Update regression tests also.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D91539
 2020-11-17 00:38:01 +09:00
Simon Moll 1c00d096a6 [VE] LVLGen sets VL before vector insts 
The VE backend represents vector instructions with an explicit 'i32'
vector length operand.  In the VE ISA, the vector length is always read
from the VL hardware register.  The LVLGen pass inserts 'lvl'
instructions as necessary to set VL to the right value before each
vector instruction.

Reviewed By: kaz7

Differential Revision: https://reviews.llvm.org/D91416
 2020-11-16 09:19:14 +01:00
Kazushi (Jam) Marukawa 02ab46ef73 [VE] Add vst intrinsic instructions 
Add vst intrinsic instructions and a regression test.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D91406
 2020-11-13 19:11:57 +09:00