OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 6
Code Issues Packages Projects Releases Wiki Activity
433,172 Commits 32 Branches 0 Tags 2.2 GiB
Commit Graph

5 Commits

Author SHA1 Message Date
Craig Topper eec05bfeaf [RISCV] Add {{$}} to some CHECK lines in MC tests. 
This adds {{$}} to most of the CHECK lines for errors about what
extension an instruction requires. This ensures we check all the
extensions when there is a list.

Differential Revision: https://reviews.llvm.org/D131436
 2022-08-08 14:38:11 -07:00
ping.deng 880ac5189d [RISCV][NFC] Add load/store instructions in rv64*-invalid.s 
Reviewed By: benshi001, sunshaoce

Differential Revision: https://reviews.llvm.org/D127721
 2022-06-17 06:53:19 +00:00
Shao-Ce SUN 0e38b29543 [RISCV] add the MC layer support of Zfinx extension 
This patch added the MC layer support of Zfinx extension.

Authored-by: StephenFan
Co-Authored-by: Shao-Ce Sun

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D93298
 2022-03-02 14:25:19 +08:00
Nikita Popov c7fe6f9c92 Revert "[RISCV] add the MC layer support of Zfinx extension" 
This reverts commit 7798ecca9c.

As reported in https://reviews.llvm.org/D93298#3331641 and
following, this causes assertion failures with inline assembly.
 2022-02-24 12:14:31 +01:00
Shao-Ce SUN 7798ecca9c [RISCV] add the MC layer support of Zfinx extension 
This patch added the MC layer support of Zfinx extension.

Authored-by: StephenFan
Co-Authored-by: Shao-Ce Sun

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D93298
 2022-02-17 21:54:13 +08:00