Commit Graph

5 Commits

Author SHA1 Message Date
Fangrui Song e27e3ba9c9 [RISCVAsmParser] Allow a SymbolRef operand to be a complex expression
So that instructions like `lla a5, (0xFF + end) - 4` (supported by GNU as) can
be parsed.

Add a missing test that an operand like `foo + foo` is not allowed.

Reviewed By: jrtc27

Differential Revision: https://reviews.llvm.org/D92293
2020-12-01 16:08:09 -08:00
Sam Elliott 404551ac64 [RISCV][NFC] Correct RUN in rvi-pseudos-invalid.s
This test should test both riscv32 and riscv64.

llvm-svn: 366825
2019-07-23 17:14:42 +00:00
Lewis Revill aa79a3fe8e [RISCV] Support assembling TLS add and associated modifiers
This patch adds support in the MC layer for parsing and assembling the
4-operand add instruction needed for TLS addressing. This also involves
parsing the %tprel_hi, %tprel_lo and %tprel_add operand modifiers.

Differential Revision: https://reviews.llvm.org/D55341

llvm-svn: 357698
2019-04-04 14:13:37 +00:00
Kito Cheng 303217e8b4 [RISCV] Implement pseudo instructions for load/store from a symbol address.
Summary:
Those pseudo-instructions are making load/store instructions able to
load/store from/to a symbol, and its always using PC-relative addressing
to generating a symbol address.

Reviewers: asb, apazos, rogfer01, jrtc27

Differential Revision: https://reviews.llvm.org/D50496

llvm-svn: 354430
2019-02-20 03:31:32 +00:00
Alex Bradbury 22531c4a14 [RISCV] Add assembler support for LA pseudo-instruction
This patch also introduces the emitAuipcInstPair helper, which is then used
for both emitLoadAddress and emitLoadLocalAddress.

Differential Revision: https://reviews.llvm.org/D55325
Patch by James Clarke.

llvm-svn: 354111
2019-02-15 09:53:32 +00:00