Commit Graph

1733 Commits

Author SHA1 Message Date
Chris Lattner de339fa55d eliminate more redundant constraint type analysis
llvm-svn: 36546
2007-04-28 21:03:16 +00:00
Chris Lattner b2e55562ed merge constraint type analysis stuff together.
llvm-svn: 36545
2007-04-28 21:01:43 +00:00
Chris Lattner d7e3b6c442 Significant refactoring of the inline asm stuff, to support future changes.
No functionality change.

llvm-svn: 36544
2007-04-28 20:49:53 +00:00
Chris Lattner 1deacd61f4 memory inputs to an inline asm are required to have an address available.
If the operand is not already an indirect operand, spill it to a constant
pool entry or a stack slot.

This fixes PR1356 and CodeGen/X86/2007-04-27-InlineAsm-IntMemInput.ll

llvm-svn: 36536
2007-04-28 06:42:38 +00:00
Chris Lattner d102ed0ac6 Fix CodeGen/Generic/2007-04-27-LargeMemObject.ll and
CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll

llvm-svn: 36534
2007-04-28 06:08:13 +00:00
Chris Lattner 4df3e8093b Fix this to match change to InlineAsm class.
llvm-svn: 36524
2007-04-28 04:05:59 +00:00
Chris Lattner 1cbe208cda Fix incorrect legalization of EHSELECTOR. This fixes
CodeGen/Generic/2007-04-14-EHSelectorCrash.ll and PR1326

llvm-svn: 36510
2007-04-27 17:12:52 +00:00
Evan Cheng bf535fc8bd Expand UINT_TO_FP in turns of SINT_TO_FP when UINTTOFP_* libcalls are not available.
llvm-svn: 36501
2007-04-27 07:33:31 +00:00
Chris Lattner 784fe9dbbb improve EH global handling, patch by Duncan Sands.
llvm-svn: 36499
2007-04-27 01:20:11 +00:00
Chris Lattner 8131ab7c0f enable Anton's shift/and switch lowering stuff! It now passes ppc bootstrap
successfully! woohoo...

llvm-svn: 36496
2007-04-26 21:09:43 +00:00
Anton Korobeynikov d7ae7f1659 Fixx off-by-one bug, which prevents llvm-gcc bootstrap on ppc32
llvm-svn: 36490
2007-04-26 20:44:04 +00:00
Dan Gohman e131e3ac02 Fix a typo in a comment.
llvm-svn: 36485
2007-04-26 19:40:56 +00:00
Evan Cheng 15f269afa3 This was lefted out. Fixed sumarray-dbl.
llvm-svn: 36445
2007-04-25 18:33:21 +00:00
Chris Lattner cb0ed0cfbd allow support for 64-bit stack objects
llvm-svn: 36420
2007-04-25 04:08:28 +00:00
Chris Lattner 01a26c74ae Be more careful about folding op(x, undef) when we have vector operands.
This fixes CodeGen/X86/2007-04-24-VectorCrash.ll

llvm-svn: 36413
2007-04-25 00:00:45 +00:00
Bill Wendling 47917b697f Assertion when using a 1-element vector for an add operation. Get the
real vector type in this case.

llvm-svn: 36402
2007-04-24 21:13:23 +00:00
Scott Michel 4cfa616cee Use '-1U' where '-1UL' is obvious overkill, eliminating gcc warnings about
tests always being true in the process.

llvm-svn: 36387
2007-04-24 01:24:20 +00:00
Christopher Lamb 8af6d5896f PR400 phase 2. Propagate attributed load/store information through DAGs.
llvm-svn: 36356
2007-04-22 23:15:30 +00:00
Lauro Ramos Venancio 4e91908f17 X86 TLS: Implement review feedback.
llvm-svn: 36318
2007-04-21 20:56:26 +00:00
Reid Spencer 0c1349e6bc Revert Christopher Lamb's load/store alignment changes.
llvm-svn: 36309
2007-04-21 18:36:27 +00:00
Christopher Lamb bff50208c8 add support for alignment attributes on load/store instructions
llvm-svn: 36301
2007-04-21 08:16:25 +00:00
Lauro Ramos Venancio 94314be0e0 Allow the lowering of ISD::GLOBAL_OFFSET_TABLE.
llvm-svn: 36290
2007-04-20 23:02:39 +00:00
Lauro Ramos Venancio 2518889872 Implement "general dynamic", "initial exec" and "local exec" TLS models for
X86 32 bits.

llvm-svn: 36283
2007-04-20 21:38:10 +00:00
Chris Lattner f03c90bee6 allow SRL to simplify its operands, as it doesn't demand all bits as input.
llvm-svn: 36245
2007-04-18 03:06:49 +00:00
Chris Lattner bf14f20632 When replacing a node in SimplifyDemandedBits, if the old node used any
single-use nodes, they will be dead soon.  Make sure to remove them before
processing other nodes.  This implements CodeGen/X86/shl_elim.ll

llvm-svn: 36244
2007-04-18 03:05:22 +00:00
Chris Lattner 15c1b820cc fix a pasto
llvm-svn: 36242
2007-04-18 03:01:40 +00:00
Chris Lattner 4aff52bf3d Fix a bug in my previous patch, grabbing the shift amount width from the
wrong operand.

llvm-svn: 36223
2007-04-17 22:53:02 +00:00
Chris Lattner 9a861a8550 Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used.
This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }

into:
_baz:
        srwi r2, r3, 1
        extsh r3, r2
        blr

on PPC, instead of:
_baz:
        slwi r2, r3, 8
        srwi r2, r2, 9
        extsh r3, r2
        blr

GCC produces:
_baz:
        srwi r10,r4,24
        insrwi r10,r3,24,0
        srawi r9,r3,24
        srawi r3,r10,9
        extsh r3,r3
        blr

This implements CodeGen/PowerPC/shl_elim.ll

llvm-svn: 36221
2007-04-17 21:14:16 +00:00
Chris Lattner 9ad5915559 SIGN_EXTEND_INREG does not demand its top bits. Give SimplifyDemandedBits
a chance to hack on it.  This compiles:

int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }

into:
_baz:
        slwi r2, r3, 8
        srwi r2, r2, 9
        extsh r3, r2
        blr

instead of:

_baz:
        srwi r2, r4, 24
        rlwimi r2, r3, 8, 0, 23
        srwi r2, r2, 9
        extsh r3, r2
        blr

This implements CodeGen/PowerPC/sign_ext_inreg1.ll

llvm-svn: 36212
2007-04-17 19:03:21 +00:00
Anton Korobeynikov fb80151c42 Removed tabs everywhere except autogenerated & external files. Add make
target for tabs checking.

llvm-svn: 36146
2007-04-16 18:10:23 +00:00
Chris Lattner 6bd7b7b30b disable switch lowering using shift/and. It still breaks ppc bootstrap for
some reason.  :(  Will investigate.

llvm-svn: 36011
2007-04-14 19:39:41 +00:00
Anton Korobeynikov 8a1a84f96e Fix PR1325: Case range optimization was performed in the case it
shouldn't. Also fix some "latent" bug on 64-bit platforms

llvm-svn: 35990
2007-04-14 13:25:55 +00:00
Chris Lattner 7196f09edc disable shift/and lowering to work around PR1325 for now.
llvm-svn: 35985
2007-04-14 02:26:56 +00:00
Anton Korobeynikov e288040abf Fix PR1323 : we haven't updated phi nodes in good manner :)
llvm-svn: 35963
2007-04-13 06:53:51 +00:00
Chris Lattner 5111499136 the result of an inline asm copy can be an arbitrary VT that the register
class supports.  In the case of vectors, this means we often get the wrong
type (e.g. we get v4f32 instead of v8i16).  Make sure to convert the vector
result to the right type.  This fixes CodeGen/X86/2007-04-11-InlineAsmVectorResult.ll

llvm-svn: 35944
2007-04-12 06:00:20 +00:00
Chris Lattner a77cb3ce68 fold noop vbitconvert instructions
llvm-svn: 35943
2007-04-12 05:58:43 +00:00
Chris Lattner 784a68a702 Fix weirdness handling single element vectors.
llvm-svn: 35941
2007-04-12 04:44:28 +00:00
Reid Spencer c6251a7dfd For PR1284:
Implement the "part_set" intrinsic.

llvm-svn: 35938
2007-04-12 02:48:46 +00:00
Chris Lattner 18e4ac4107 fix an infinite loop compiling ldecod, notice by JeffC.
llvm-svn: 35910
2007-04-11 16:51:53 +00:00
Chris Lattner a083ffcad7 Fix this harder.
llvm-svn: 35888
2007-04-11 06:50:51 +00:00
Chris Lattner c5f85d3738 don't create shifts by zero, fix some problems with my previous patch
llvm-svn: 35887
2007-04-11 06:43:25 +00:00
Chris Lattner 65786b078c Teach the codegen to turn [aez]ext (setcc) -> selectcc of 1/0, which often
allows other simplifications.  For example, this compiles:
int isnegative(unsigned int X) {
   return !(X < 2147483648U);
}

Into this code:

x86:
        movl 4(%esp), %eax
        shrl $31, %eax
        ret
arm:
        mov r0, r0, lsr #31
        bx lr
thumb:
        lsr r0, r0, #31
        bx lr

instead of:

x86:
        cmpl $0, 4(%esp)
        sets %al
        movzbl %al, %eax
        ret

arm:
        mov r3, #0
        cmp r0, #0
        movlt r3, #1
        mov r0, r3
        bx lr

thumb:
        mov r2, #1
        mov r1, #0
        cmp r0, #0
        blt LBB1_2      @entry
LBB1_1: @entry
        cpy r2, r1
LBB1_2: @entry
        cpy r0, r2
        bx lr

Testcase here: test/CodeGen/Generic/ispositive.ll

llvm-svn: 35883
2007-04-11 05:32:27 +00:00
Chris Lattner 41189c63cc Codegen integer abs more efficiently using the trick from the PPC CWG. This
improves codegen on many architectures.  Tests committed as CodeGen/*/iabs.ll

X86 Old:			X86 New:
_test:				_test:
   movl 4(%esp), %ecx		   movl 4(%esp), %eax
   movl %ecx, %eax		   movl %eax, %ecx
   negl %eax			   sarl $31, %ecx
   testl %ecx, %ecx		   addl %ecx, %eax
   cmovns %ecx, %eax		   xorl %ecx, %eax
   ret				   ret

PPC Old:			PPC New:
_test:				_test:
   cmpwi cr0, r3, -1		   srawi r2, r3, 31
   neg r2, r3			   add r3, r3, r2
   bgt cr0, LBB1_2 ;		   xor r3, r3, r2
LBB1_1: ;			   blr
   mr r3, r2
LBB1_2: ;
   blr

ARM Old:			ARM New:
_test:				_test:
   rsb r3, r0, #0		   add r3, r0, r0, asr #31
   cmp r0, #0			   eor r0, r3, r0, asr #31
   movge r3, r0			   bx lr
   mov r0, r3
   bx lr

Thumb Old:			Thumb New:
_test:				_test:
   neg r2, r0			   asr r2, r0, #31
   cmp r0, #0			   add r0, r0, r2
   bge LBB1_2			   eor r0, r2
LBB1_1: @			   bx lr
   cpy r0, r2
LBB1_2: @
   bx lr


Sparc Old:			Sparc New:
test:				test:
   save -96, %o6, %o6		   save -96, %o6, %o6
   sethi 0, %l0			   sra %i0, 31, %l0
   sub %l0, %i0, %l0		   add %i0, %l0, %l1
   subcc %i0, -1, %l1		   xor %l1, %l0, %i0
   bg .BB1_2			   restore %g0, %g0, %g0
   nop				   retl
.BB1_1:				   nop
   or %g0, %l0, %i0
.BB1_2:
   restore %g0, %g0, %g0
   retl
   nop

It also helps alpha/ia64 :)

llvm-svn: 35881
2007-04-11 05:11:38 +00:00
Reid Spencer a472f66dd0 For PR1146:
Put the parameter attributes in their own ParamAttr name space. Adjust the
rest of llvm as a result.

llvm-svn: 35877
2007-04-11 02:44:20 +00:00
Chris Lattner f269d84ca0 apparently some people commit without building the tree, or they forget to
commit a LOT of files.

llvm-svn: 35858
2007-04-10 03:20:39 +00:00
Jeff Cohen e0bbbd3774 No longer needed.
llvm-svn: 35850
2007-04-09 23:42:32 +00:00
Chris Lattner 35f0417ec1 remove dead target hooks.
llvm-svn: 35847
2007-04-09 23:34:08 +00:00
Chris Lattner 39f65335d5 remove some dead target hooks, subsumed by isLegalAddressingMode
llvm-svn: 35840
2007-04-09 22:27:04 +00:00
Anton Korobeynikov da964a2852 Use integer log for metric calculation
llvm-svn: 35834
2007-04-09 21:57:03 +00:00
Jeff Cohen 0475f3b4e9 Unbreak VC++ build.
llvm-svn: 35817
2007-04-09 14:32:59 +00:00
Anton Korobeynikov 506eaf7915 Next stage into switch lowering refactoring
1. Fix some bugs in the jump table lowering threshold
2. Implement much better metric for optimal pivot selection
3. Tune thresholds for different lowering methods
4. Implement shift-and trick for lowering small (<machine word
length) cases with few destinations. Good testcase will follow.

llvm-svn: 35816
2007-04-09 12:31:58 +00:00
Reid Spencer 71b79e3d99 For PR1146:
Adapt handling of parameter attributes to use the new ParamAttrsList class.

llvm-svn: 35814
2007-04-09 06:17:21 +00:00
Chris Lattner 7b2decfa0a implement CodeGen/X86/inline-asm-x-scalar.ll:test3
llvm-svn: 35802
2007-04-09 05:31:20 +00:00
Chris Lattner 18d6718e78 add some assertions
llvm-svn: 35800
2007-04-09 05:23:13 +00:00
Chris Lattner b49917da92 Fix PR1316
llvm-svn: 35783
2007-04-09 00:33:58 +00:00
Chris Lattner e55ecfb870 Fix for CodeGen/X86/2007-04-08-InlineAsmCrash.ll and PR1314
llvm-svn: 35779
2007-04-08 22:23:26 +00:00
Chris Lattner 1c741e95d3 minor comment fix
llvm-svn: 35696
2007-04-06 17:47:14 +00:00
Reid Spencer 85460acfbf Change the bit_part_select (non)implementation from "return 0" to abort.
llvm-svn: 35679
2007-04-05 01:20:18 +00:00
Reid Spencer cce90f55ed Implement the llvm.bit.part_select.iN.iN.iN overloaded intrinsic.
llvm-svn: 35678
2007-04-04 23:48:25 +00:00
Anton Korobeynikov 915e61736b Properly emit range comparisons for switch cases, where neighbour cases
go to the same destination. Now we're producing really good code for
switch-lower-feature.ll testcase

llvm-svn: 35672
2007-04-04 21:14:49 +00:00
Scott Michel 16627a542f 1. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL.
2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL
patterns. This was motivated by the X86/rotate.ll testcase, which should now
generate code for other platforms (and soon-to-come platforms.) Rewrote code
slightly to make it easier to read.

llvm-svn: 35605
2007-04-02 21:36:32 +00:00
Reid Spencer 3a0843e734 For PR1297:
Adjust for changes in the bit counting intrinsics. They all return i32
now so we have to trunc/zext the DAG node accordingly.

llvm-svn: 35546
2007-04-01 07:34:11 +00:00
Reid Spencer a090ffb2ab For PR1297:
Change getOperationName to return std::string instead of const char*

llvm-svn: 35545
2007-04-01 07:32:19 +00:00
Chris Lattner f6a6d3c8b0 move a bunch of code out of the sdisel pass into its own opt pass "codegenprepare".
llvm-svn: 35529
2007-03-31 04:18:03 +00:00
Chris Lattner f2d71d49e2 switch TL::getValueType to use MVT::getValueType.
llvm-svn: 35527
2007-03-31 04:05:24 +00:00
Chris Lattner ac3f81508c add one addressing mode description hook to rule them all.
llvm-svn: 35520
2007-03-30 23:14:50 +00:00
Dale Johannesen 4bbd2eefba Fix incorrect combination of different loads. Reenable zext-over-truncate
combination.

llvm-svn: 35517
2007-03-30 21:38:07 +00:00
Evan Cheng ccee35fd0d Disable load width reduction xform of variant (zext (truncate load x)) for
big endian targets until llvm-gcc build issue has been resolved.

llvm-svn: 35449
2007-03-29 07:56:46 +00:00
Evan Cheng 4388043b25 Scale 1 is always ok.
llvm-svn: 35407
2007-03-28 01:55:52 +00:00
Evan Cheng c2cba18f2b Remove isLegalAddressImmediate.
llvm-svn: 35406
2007-03-28 01:53:55 +00:00
Evan Cheng 07c42d43a2 GEP index sinking fixes:
1) Take address scale into consideration. e.g. i32* -> scale 4.
2) Examine all the users of GEP.
3) Generalize to inter-block GEP's (no longer uses loopinfo).
4) Don't do xform if GEP has other variable index(es).

llvm-svn: 35403
2007-03-28 01:49:39 +00:00
Anton Korobeynikov 37a0bfe128 Remove dead code
llvm-svn: 35380
2007-03-27 12:05:48 +00:00
Anton Korobeynikov 3a9d68181a Split big monster into small helpers. No functionality change.
llvm-svn: 35379
2007-03-27 11:29:11 +00:00
Evan Cheng c42406b5ad SDISel does not preserve all, it changes CFG and other info.
llvm-svn: 35376
2007-03-27 00:53:36 +00:00
Evan Cheng 8275f0e0af SIGN_EXTEND_INREG requires one extra operand, a ValueType node.
llvm-svn: 35350
2007-03-26 07:12:51 +00:00
Anton Korobeynikov 7037826c86 First step of switch lowering refactoring: perform worklist-driven
strategy, emit JT's where possible.

llvm-svn: 35338
2007-03-25 15:07:15 +00:00
Chris Lattner 77f0479833 Implement support for vector operands to inline asm, implementing
CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll

llvm-svn: 35332
2007-03-25 05:00:54 +00:00
Chris Lattner 3d7efa2586 implement initial support for the silly X constraint. Testcase here: CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll
llvm-svn: 35327
2007-03-25 04:35:41 +00:00
Chris Lattner 843e44503c Implement CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll
llvm-svn: 35324
2007-03-25 02:18:14 +00:00
Chris Lattner d685514e2e switch TargetLowering::getConstraintType to take the entire constraint,
not just the first letter.  No functionality change.

llvm-svn: 35322
2007-03-25 02:14:49 +00:00
Chris Lattner 2a991268f7 don't rely on ADL
llvm-svn: 35299
2007-03-24 17:37:03 +00:00
Evan Cheng b7051f596a Adjust offset to compensate for big endian machines.
llvm-svn: 35293
2007-03-24 00:02:43 +00:00
Evan Cheng a883b58caf Make sure SEXTLOAD of the specific type is supported on the target.
llvm-svn: 35289
2007-03-23 22:13:36 +00:00
Evan Cheng e2f5f24e8e Also replace uses of SRL if that's also folded during ReduceLoadWidth().
llvm-svn: 35286
2007-03-23 20:55:21 +00:00
Evan Cheng a824e79f06 A couple of bug fixes for reducing load width xform:
1. Address offset is in bytes.
2. Make sure truncate node uses are replaced with new load.

llvm-svn: 35274
2007-03-23 02:16:52 +00:00
Dan Gohman dcb291faa4 Change uses of Function::front to Function::getEntryBlock for readability.
llvm-svn: 35265
2007-03-22 16:38:57 +00:00
Evan Cheng 464dc9b74c More opportunities to reduce load size.
llvm-svn: 35254
2007-03-22 01:54:19 +00:00
Dale Johannesen 0c6bb5eab7 repair x86 performance, dejagnu problems from previous change
llvm-svn: 35245
2007-03-21 21:51:52 +00:00
Evan Cheng d63baead9b fold (truncate (srl (load x), c)) -> (smaller load (x+c/vt bits))
llvm-svn: 35239
2007-03-21 20:14:05 +00:00
Dale Johannesen bacf4acf65 do not share old induction variables when this would result in invalid
instructions (that would have to be split later)

llvm-svn: 35227
2007-03-20 21:54:54 +00:00
Jeff Cohen 1baf5c84ab Fix some VC++ warnings.
llvm-svn: 35224
2007-03-20 20:43:18 +00:00
Lauro Ramos Venancio 971aa18867 Code clean up.
llvm-svn: 35220
2007-03-20 20:09:03 +00:00
Evan Cheng 550cf0369c Minor bug.
llvm-svn: 35219
2007-03-20 19:32:11 +00:00
Lauro Ramos Venancio 25878b45f5 CopyToReg source operand can be a physical register.
llvm-svn: 35213
2007-03-20 16:46:44 +00:00
Evan Cheng a2465dfc07 Use SmallSet instead of std::set.
llvm-svn: 35133
2007-03-17 08:53:30 +00:00
Evan Cheng be22235790 If sdisel has decided to sink GEP index expression into any BB. Replace all uses
in that BB.

llvm-svn: 35132
2007-03-17 08:22:49 +00:00
Evan Cheng c5bc763f50 Turn on GEP index sinking by default.
llvm-svn: 35127
2007-03-16 18:32:30 +00:00
Evan Cheng 0a9d0cabaf Stupid bug.
llvm-svn: 35126
2007-03-16 17:50:20 +00:00
Evan Cheng 009ea54262 Sink a binary expression into its use blocks if it is a loop invariant
computation used as GEP indexes and if the expression can be folded into
target addressing mode of GEP load / store use types.

llvm-svn: 35123
2007-03-16 08:46:27 +00:00
Evan Cheng a2a2fd1e55 Added isLegalAddressExpression hook to test if the given expression can be
folded into target addressing mode for the given type.

llvm-svn: 35121
2007-03-16 08:42:32 +00:00
Evan Cheng b9e3db67fb Estimate a cost using the possible number of scratch registers required and use
it as a late BURR scheduling tie-breaker.
Intuitively, it's good to push down instructions whose results are liveout so
their long live ranges won't conflict with other values which are needed inside
the BB. Further prioritize liveout instructions by the number of operands which
are calculated within the BB.

llvm-svn: 35109
2007-03-14 22:43:40 +00:00
Evan Cheng 2874855302 Try schedule def + use closer whne Sethi-Ullman numbers are the same.
e.g.
t1 = op t2, c1
t3 = op t4, c2
and the following instructions are both ready.
t2 = op c3
t4 = op c4

Then schedule t2 = op first.
i.e.
t4 = op c4
t2 = op c3
t1 = op t2, c1
t3 = op t4, c2

This creates more short live intervals which work better with the register
allocator.

llvm-svn: 35089
2007-03-13 23:25:11 +00:00
Evan Cheng b7004fd889 More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale.
llvm-svn: 35076
2007-03-12 23:37:10 +00:00
Chris Lattner ce8aba03ee implement support for floating point constants used as inline asm memory operands.
llvm-svn: 35033
2007-03-08 22:29:47 +00:00
Chris Lattner b7bc3f2d30 make this fail even in non-assert builds.
llvm-svn: 35025
2007-03-08 07:07:03 +00:00
Anton Korobeynikov ed4b303c10 Refactoring of formal parameter flags. Enable properly use of
zext/sext/aext stuff.

llvm-svn: 35008
2007-03-07 16:25:09 +00:00
Evan Cheng 8a1d09d079 Avoid combining indexed load further.
llvm-svn: 35005
2007-03-07 08:07:03 +00:00
Chris Lattner 13780ac7db big endian 32-bit systems (e.g. ppc32) want to return the high reg first, not
the lo-reg first.  This is fallout from my ppc calling conv change yesterday,
it fixes test/ExecutionEngine/2003-05-06-LivenessClobber.llx

llvm-svn: 34983
2007-03-06 20:01:06 +00:00
Anton Korobeynikov f0b9316552 Enumerate SDISel formal parameter attributes. Make use of new
enumeration.

llvm-svn: 34960
2007-03-06 06:10:33 +00:00
Jeff Cohen b622c11f77 Unbreak VC++ build.
llvm-svn: 34917
2007-03-05 00:00:42 +00:00
Chris Lattner 47206667c0 fold away addc nodes when we know there cannot be a carry-out.
llvm-svn: 34913
2007-03-04 20:40:38 +00:00
Chris Lattner 2dcc6e7f58 generalize
llvm-svn: 34910
2007-03-04 20:08:45 +00:00
Chris Lattner e2e13caeb2 canonicalize constants to the RHS of addc/adde. If nothing uses the carry out of
addc, turn it into add.

This allows us to compile:

long long test(long long A, unsigned B) {
  return (A + ((long long)B << 32)) & 123;
}

into:

_test:
        movl $123, %eax
        andl 4(%esp), %eax
        xorl %edx, %edx
        ret

instead of:
_test:
        xorl %edx, %edx
        movl %edx, %eax
        addl 4(%esp), %eax   ;; add of zero
        andl $123, %eax
        ret

llvm-svn: 34909
2007-03-04 20:03:15 +00:00
Chris Lattner 362621c7ae eliminate some ops if they have an undef RHS
llvm-svn: 34908
2007-03-04 20:01:46 +00:00
Chris Lattner ca401aac31 Fix CodeGen/Generic/fpowi-promote.ll and PR1239
llvm-svn: 34893
2007-03-03 23:43:21 +00:00
Chris Lattner 567b9254cd Add an expand action for ISD label which just deletes the label.
This "fixes" PR1238.

llvm-svn: 34890
2007-03-03 19:21:38 +00:00
Jim Laskey d5453d7b56 Lower eh filter intrinsic.
llvm-svn: 34802
2007-03-01 20:24:30 +00:00
Jim Laskey 644af6b68f Chain is on second operand.
llvm-svn: 34759
2007-02-28 20:43:58 +00:00
Jim Laskey cf465fcebc MERGE_VALUES unnecessary.
llvm-svn: 34750
2007-02-28 18:37:04 +00:00
Chris Lattner 74bb92902e add methods for analysis of call results and return nodes.
llvm-svn: 34738
2007-02-28 07:09:40 +00:00
Chris Lattner e74744143f add methods to analyze calls and formals.
llvm-svn: 34736
2007-02-28 06:56:37 +00:00
Chris Lattner 9f059194a7 Minor refactoring of CC Lowering interfaces
llvm-svn: 34656
2007-02-27 05:13:54 +00:00
Chris Lattner dc3adc83e7 move CC Lowering stuff to its own public interface
llvm-svn: 34655
2007-02-27 04:43:02 +00:00
Chris Lattner fce448f856 Fold (sext (truncate x)) more aggressively, by avoiding creation of a
sextinreg if not needed.   This is useful in two cases: before legalize,
it avoids creating a sextinreg that will be trivially removed.  After legalize
if the target doesn't support sextinreg, the trunc/sext would not have been
removed before.

llvm-svn: 34621
2007-02-26 03:13:59 +00:00
Chris Lattner ab5d0ac02c track signedness of formal argument, though we have a fixme here.
llvm-svn: 34620
2007-02-26 02:56:58 +00:00
Jim Laskey 14059d958a Fix for PR1224.
llvm-svn: 34610
2007-02-25 21:43:59 +00:00
Chris Lattner 8c504cf9a0 optimize duplicate ValueMap lookups
llvm-svn: 34599
2007-02-25 18:40:32 +00:00
Chris Lattner 387f464121 fold trivial token factor nodes. This allows us to compile
test/CodeGen/X86/fp-stack-ret.ll into:

        movl 4(%esp), %eax
        fldl (%eax)
        ret

instead of:

        subl $12, %esp
        movl 16(%esp), %eax
        movsd (%eax), %xmm0
        movsd %xmm0, (%esp)
        fldl (%esp)
        addl $12, %esp
        ret

by eliminating a token factor that blocked a check.

llvm-svn: 34584
2007-02-25 08:24:27 +00:00
Chris Lattner 168c5856bf initialize a instance variable
llvm-svn: 34567
2007-02-25 01:28:05 +00:00
Jim Laskey e1d1c0590f Deal with cases when MMI is not requested.
llvm-svn: 34556
2007-02-24 09:45:44 +00:00
Jim Laskey b869ab6f31 Drop unused operand.
llvm-svn: 34555
2007-02-24 09:44:17 +00:00
Chris Lattner d7ef3f804d Fix CodeGen/Generic/2007-02-23-DAGCombine-Miscompile.ll and PR1219
llvm-svn: 34551
2007-02-24 02:09:29 +00:00
Jim Laskey 31fef788eb Handle improper cast.
llvm-svn: 34535
2007-02-23 21:45:01 +00:00
Jim Laskey 3e3a65b764 Need to init.
llvm-svn: 34499
2007-02-22 18:04:49 +00:00
Jim Laskey 44c37e7dbf Tighten up error checking of args.
llvm-svn: 34493
2007-02-22 16:10:05 +00:00
Jim Laskey 504e99479c Handle lowering invoke to call correctly.
llvm-svn: 34492
2007-02-22 15:38:06 +00:00
Jim Laskey 7f5872c455 Simplify lowering and selection of exception ops.
llvm-svn: 34491
2007-02-22 15:37:19 +00:00
Jim Laskey 4b37a4c712 Selection and lowering for exception handling.
llvm-svn: 34481
2007-02-21 22:53:45 +00:00
Chris Lattner 56e5fea163 print target nodes nicely
llvm-svn: 34369
2007-02-17 06:38:37 +00:00
Chris Lattner a9f917af59 Implement i/n/s constraints correctly. This fixes
test/CodeGen/PowerPC/2007-02-16-InlineAsmNConstraint.ll

llvm-svn: 34368
2007-02-17 06:00:35 +00:00
Chris Lattner 68dcec6fea fix indentation
llvm-svn: 34307
2007-02-15 18:19:15 +00:00
Chris Lattner 21ebae3394 Apply B Scott Michel's patch for PR1184, which improves diagnostics in an
abort case.

llvm-svn: 34306
2007-02-15 18:17:56 +00:00
Reid Spencer 09575bac2e For PR1195:
Change use of "packed" term to "vector" in comments, strings, variable
names, etc.

llvm-svn: 34300
2007-02-15 03:39:18 +00:00
Reid Spencer d84d35ba70 For PR1195:
Rename PackedType -> VectorType, ConstantPacked -> ConstantVector, and
PackedTyID -> VectorTyID. No functional changes.

llvm-svn: 34293
2007-02-15 02:26:10 +00:00
Chris Lattner ab1812f806 fix a warning
llvm-svn: 34272
2007-02-14 07:34:56 +00:00
Chris Lattner 1cf84d2745 Refix CodeGen/Generic/switch-lower.ll. In contrast to my previous patch,
this doesn't miscompile lots of programs :)

llvm-svn: 34268
2007-02-14 07:18:16 +00:00
Chris Lattner 945e437c65 Generalize TargetData strings, to support more interesting forms of data.
Patch by Scott Michel.

llvm-svn: 34266
2007-02-14 05:52:17 +00:00
Chris Lattner 59b27fa371 implement expand of truncate. This allows truncates from i128 to i64 to
be supported on 32-bit hosts.

llvm-svn: 34257
2007-02-13 23:55:16 +00:00
Chris Lattner d08d31f68a Fix PR1198, by adding initial i128 support. Patch by Dan Gohman.
llvm-svn: 34256
2007-02-13 23:41:38 +00:00
Chris Lattner 2fbff4d2dc revert my previous switch lowering change, which miscompiles a few programs.
This will break a dj test until I have time to investigate.

llvm-svn: 34247
2007-02-13 20:09:07 +00:00