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36 Commits

Author SHA1 Message Date
Evan Cheng 9d41b311fb Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. 
llvm-svn: 38501
 2007-07-10 18:08:01 +00:00
Evan Cheng 881248c4e1 No need for ccop anymore. 
llvm-svn: 37965
 2007-07-06 23:34:09 +00:00
Evan Cheng aa3b8014bd Each ARM use predicate operand is now made up of two components. The new component is the CPSR register. 
llvm-svn: 37895
 2007-07-05 07:13:32 +00:00
Dan Gohman e8c1e428f2 Revert the earlier change that removed the M_REMATERIALIZABLE machine 
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728
 2007-06-26 00:48:07 +00:00
Dan Gohman 9e82064924 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad 
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644
 2007-06-19 01:48:05 +00:00
Evan Cheng a7ca624028 Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit. 
llvm-svn: 37643
 2007-06-19 01:26:51 +00:00
Evan Cheng f62a5afb98 tBcc is not a barrier. 
llvm-svn: 37516
 2007-06-08 09:13:23 +00:00
Evan Cheng e8c3cbf971 Mark these instructions clobbersPred. They modify the condition code register. 
llvm-svn: 37468
 2007-06-06 10:17:05 +00:00
Evan Cheng 1634e7186b ARM::tB is also predicable. 
llvm-svn: 37125
 2007-05-16 21:53:43 +00:00
Evan Cheng 0f7cbe8370 Add PredicateOperand to all ARM instructions that have the condition field. 
llvm-svn: 37066
 2007-05-15 01:29:07 +00:00
Evan Cheng 9c031c0ddf Switch BCC, MOVCCr, etc. to PredicateOperand. 
llvm-svn: 36948
 2007-05-08 21:08:43 +00:00
Evan Cheng fa34bc9623 Doh. PC displacement is between the constantpool and the add instruction. 
llvm-svn: 36630
 2007-05-01 20:27:19 +00:00
Lauro Ramos Venancio c39c12a3fa ARM TLS: implement "general dynamic", "initial exec" and "local exec" models. 
llvm-svn: 36506
 2007-04-27 13:54:47 +00:00
Evan Cheng e54018687d Back out previous check-in. Incorrect. 
llvm-svn: 36503
 2007-04-27 07:50:02 +00:00
Evan Cheng 68ec63b3d7 tLEApcrel is a AddrModeTs, i.e. pc relative. 
llvm-svn: 36502
 2007-04-27 07:37:22 +00:00
Lauro Ramos Venancio 6be85337b0 - Divides the comparisons in two types: comparisons that only use N and Z 
flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).

llvm-svn: 35573
 2007-04-02 01:30:03 +00:00
Evan Cheng cc44b1e743 Can't re-materialize mov r, imm in thumb since mov would clobber the condition code. 
llvm-svn: 35479
 2007-03-29 21:38:31 +00:00
Lauro Ramos Venancio 143b0dff31 bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK. 
llvm-svn: 35381
 2007-03-27 16:19:21 +00:00
Lauro Ramos Venancio a88c4a74f3 bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted: 
mov lr, pc
    bx lr
So, the function was not called.

llvm-svn: 35218
 2007-03-20 17:57:23 +00:00
Evan Cheng 9bb01c9f4f Fix naming inconsistencies. 
llvm-svn: 35163
 2007-03-19 07:48:02 +00:00
Evan Cheng ee2763f76f Special LDR instructions to load from non-pc-relative constantpools. These are 
rematerializable. Only used for constant generation for now.

llvm-svn: 35162
 2007-03-19 07:20:03 +00:00
Evan Cheng 5be3e09a30 Constant generation instructions are re-materializable. 
llvm-svn: 35161
 2007-03-19 07:09:02 +00:00
Evan Cheng ec13f826a2 Spill / restore should avoid modifying the condition register. 
llvm-svn: 33971
 2007-02-07 00:06:56 +00:00
Evan Cheng 06736d0f88 .set pc relative displacement bug: label should be moved down one instruction 
to just before the add r1, pc:

Before:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        mov r1, #PCRELV0
        add r1, pc

Now:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
        mov r1, #PCRELV0
LPCRELL0:
        add r1, pc

llvm-svn: 33744
 2007-02-01 03:04:49 +00:00
Evan Cheng e7e966de5e Special epilogue for vararg functions. We cannot do a pop to pc because 
there follows a sp increment for the va register save region. Instead issue
a separate pop to another register, increment sp, and then return:
        pop {r4, r5, r6, r7}
        pop {r3}
        add sp, #3 * 4
        bx r3

llvm-svn: 33739
 2007-02-01 01:49:46 +00:00
Evan Cheng 0584836340 Thumb asm syntax does not want 's' suffix for flag setting opcodes. 
llvm-svn: 33717
 2007-01-31 20:12:31 +00:00
Evan Cheng 83f35170fa - Fix codegen for pc relative constant (e.g. JT) in thumb mode: 
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        add r1, pc, #PCRELV0
This is not legal since add r1, pc, #c requires the constant be a multiple of 4.
Do the following instead:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        mov r1, #PCRELV0
        add r1, pc

- In thumb mode, it's not possible to use .set generate a pc relative stub
  address. The stub is ARM code which is in a different section from the thumb
  code. Load the value from a constpool instead.
- Some asm printing clean up.

llvm-svn: 33664
 2007-01-30 20:37:08 +00:00
Evan Cheng 1cd3c0efb8 Change the operand orders to t_addrmode_s* to make it easier to morph 
instructions that use these address modes to instructions that use
t_addrmode_sp.

llvm-svn: 33651
 2007-01-30 02:35:32 +00:00
Evan Cheng 863736b0ad Use BL to implement Thumb far jumps. 
llvm-svn: 33649
 2007-01-30 01:13:37 +00:00
Evan Cheng 0701c5a074 Thumb jumptable support. 
llvm-svn: 33568
 2007-01-27 02:29:45 +00:00
Evan Cheng f40b9006a8 Thumb add / sub with carry. 
llvm-svn: 33562
 2007-01-27 00:07:15 +00:00
Evan Cheng add7f164a1 Represent tADDspi and tSUBspi as two-address instructions. 
llvm-svn: 33551
 2007-01-26 21:33:19 +00:00
Evan Cheng d02d75c295 extload -> zextload 
llvm-svn: 33542
 2007-01-26 19:13:16 +00:00
Evan Cheng 1526ba50d9 Use PC relative ldr to load from a constantpool in Thumb mode. 
llvm-svn: 33484
 2007-01-24 08:53:17 +00:00
Evan Cheng c0b7366cf9 - Reorg Thumb load / store instructions. Combine each rr and ri pair of 
instructions into one (e.g. tLDRrr, tLDRri -> tLDR).
- Thumb ldrsb and ldrsh only have the [reg, reg] address format. If the
  address is not an add, materialize a 0 immediate into a register and use
  it as the offset field.

llvm-svn: 33470
 2007-01-23 22:59:13 +00:00
Evan Cheng 10043e215b ARM backend contribution from Apple. 
llvm-svn: 33353
 2007-01-19 07:51:42 +00:00