Evan Cheng
|
9d41b311fb
|
Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
llvm-svn: 38501
|
2007-07-10 18:08:01 +00:00 |
|
Evan Cheng
|
881248c4e1
|
No need for ccop anymore.
llvm-svn: 37965
|
2007-07-06 23:34:09 +00:00 |
|
Evan Cheng
|
aa3b8014bd
|
Each ARM use predicate operand is now made up of two components. The new component is the CPSR register.
llvm-svn: 37895
|
2007-07-05 07:13:32 +00:00 |
|
Evan Cheng
|
e8c3cbf971
|
Mark these instructions clobbersPred. They modify the condition code register.
llvm-svn: 37468
|
2007-06-06 10:17:05 +00:00 |
|
Evan Cheng
|
19eeee41ca
|
For VFP2 fldm, fstm instructions, the condition code is printed after the address mode and size specifier. e.g. fstmiaseq, not fstmeqias.
llvm-svn: 37351
|
2007-05-29 23:34:19 +00:00 |
|
Evan Cheng
|
0f7cbe8370
|
Add PredicateOperand to all ARM instructions that have the condition field.
llvm-svn: 37066
|
2007-05-15 01:29:07 +00:00 |
|
Evan Cheng
|
9c031c0ddf
|
Switch BCC, MOVCCr, etc. to PredicateOperand.
llvm-svn: 36948
|
2007-05-08 21:08:43 +00:00 |
|
Evan Cheng
|
d37c23745f
|
This is no longer needed after enabling the DAG combiner xform.
llvm-svn: 36909
|
2007-05-07 21:29:41 +00:00 |
|
Dale Johannesen
|
89200ce0f0
|
Evan's patch to avoid FPreg->intreg copy for cvt; store to mem
llvm-svn: 36693
|
2007-05-03 20:54:42 +00:00 |
|
Chris Lattner
|
1c1082133c
|
match a reassociated form of fnmul. This implements CodeGen/ARM/fnmul.ll
llvm-svn: 36660
|
2007-05-03 00:32:00 +00:00 |
|
Evan Cheng
|
10043e215b
|
ARM backend contribution from Apple.
llvm-svn: 33353
|
2007-01-19 07:51:42 +00:00 |