b1e6d84544
Plug in the byte and short splats
...
llvm-svn: 27387
2006-04-04 00:05:13 +00:00
447a7968af
Revert accidentally committed hunks.
...
llvm-svn: 27386
2006-04-03 23:58:04 +00:00
533aed9a35
Make sure to mark unsupported SCALAR_TO_VECTOR operations as expand.
...
llvm-svn: 27385
2006-04-03 23:55:43 +00:00
5400727595
Force use of a frame-pointer if there is anything on the stack that is aligned
...
more than the OS keeps the stack aligned.
llvm-svn: 27381
2006-04-03 22:03:29 +00:00
9ccd61c893
Add the full set of min/max instructions
...
llvm-svn: 27372
2006-04-03 15:58:28 +00:00
acf1fc8a28
add a note
...
llvm-svn: 27360
2006-04-02 07:20:00 +00:00
c5287c0ece
Inform the dag combiner that the predicate compares only return a low bit.
...
llvm-svn: 27359
2006-04-02 06:26:07 +00:00
80fdc1eb6b
Remove done item
...
llvm-svn: 27351
2006-04-02 05:28:54 +00:00
b80f114707
add a note
...
llvm-svn: 27348
2006-04-02 03:59:11 +00:00
9b2d6e7886
Custom lower all BUILD_VECTOR's so that we can compile vec_splat_u8(8) into
...
"vspltisb v0, 8" instead of a constant pool load.
llvm-svn: 27335
2006-04-02 00:43:36 +00:00
dc72c17798
Implement vnot using VNOR instead of using 'vspltisb v0, -1' and vxor
...
llvm-svn: 27331
2006-04-01 22:41:47 +00:00
ff77dc0a08
Shrinkify some more intrinsic definitions.
...
llvm-svn: 27322
2006-03-31 22:41:56 +00:00
20d3f3726f
Pull operand asm string into base class, shrinkifying intrinsic definitions.
...
No functionality change.
llvm-svn: 27320
2006-03-31 22:34:05 +00:00
110fc74b97
Fix 80 column violations :)
...
llvm-svn: 27315
2006-03-31 21:57:36 +00:00
a4150f751d
fix a pasto
...
llvm-svn: 27308
2006-03-31 21:19:06 +00:00
e7fd4b0274
Add vperm support for all datatypes
...
llvm-svn: 27307
2006-03-31 20:00:35 +00:00
baa73e0d91
Rearrange code a bit
...
llvm-svn: 27306
2006-03-31 19:52:36 +00:00
754b41c84b
Add, sub and shuffle are legal for all vector types
...
llvm-svn: 27305
2006-03-31 19:48:58 +00:00
40ff17dc22
add a note
...
llvm-svn: 27302
2006-03-31 19:00:22 +00:00
829a061abf
note to self: *save* file, then check it in
...
llvm-svn: 27291
2006-03-31 06:04:53 +00:00
d4058a59d4
Implement an item from the readme, folding vcmp/vcmp. instructions with
...
identical instructions into a single instruction. For example, for:
void test(vector float *x, vector float *y, int *P) {
int v = vec_any_out(*x, *y);
*x = (vector float)vec_cmpb(*x, *y);
*P = v;
}
we now generate:
_test:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r4
lvx v1, 0, r3
vcmpbfp. v0, v1, v0
mfcr r4, 2
stvx v0, 0, r3
rlwinm r3, r4, 27, 31, 31
xori r3, r3, 1
stw r3, 0(r5)
mtspr 256, r2
blr
instead of:
_test:
mfspr r2, 256
oris r6, r2, 57344
mtspr 256, r6
lvx v0, 0, r4
lvx v1, 0, r3
vcmpbfp. v2, v1, v0
mfcr r4, 2
*** vcmpbfp v0, v1, v0
rlwinm r4, r4, 27, 31, 31
stvx v0, 0, r3
xori r3, r4, 1
stw r3, 0(r5)
mtspr 256, r2
blr
Testcase here: CodeGen/PowerPC/vcmp-fold.ll
llvm-svn: 27290
2006-03-31 06:02:07 +00:00
070181c927
compactify some more instruction definitions
...
llvm-svn: 27288
2006-03-31 05:38:32 +00:00
45c709388a
Compactify comparisons.
...
llvm-svn: 27287
2006-03-31 05:32:57 +00:00
d7495ae7e9
Lower vector compares to VCMP nodes, just like we lower vector comparison
...
predicates to VCMPo nodes.
llvm-svn: 27285
2006-03-31 05:13:27 +00:00
e5a6c4f8b7
These are done
...
llvm-svn: 27284
2006-03-31 04:53:21 +00:00
bca5fbe914
Mark INSERT_VECTOR_ELT as expand
...
llvm-svn: 27276
2006-03-31 01:48:55 +00:00
c4e3eadf21
Add the rest of the vmul instructions and the vmulsum* instructions.
...
llvm-svn: 27268
2006-03-30 23:39:06 +00:00
a23158f1ca
Use a new tblgen feature to significantly shrinkify instruction definitions that
...
directly correspond to intrinsics.
llvm-svn: 27266
2006-03-30 23:21:27 +00:00
551d3a11d3
Add a bunch of new instructions for intrinsics.
...
llvm-svn: 27265
2006-03-30 23:07:36 +00:00
7d6f4f14b4
add a note
...
llvm-svn: 27243
2006-03-29 00:24:13 +00:00
66e1410858
add a note
...
llvm-svn: 27227
2006-03-28 18:56:23 +00:00
d1aa1638c6
Expose base register for DwarfWriter. Refactor code accordingly.
...
llvm-svn: 27225
2006-03-28 13:48:33 +00:00
af8c373e77
Fix a couple typos
...
llvm-svn: 27216
2006-03-28 04:18:18 +00:00
1b3928765d
Add a few more altivec intrinsics
...
llvm-svn: 27215
2006-03-28 04:15:58 +00:00
3710fca2b8
implement a bunch more intrinsics.
...
llvm-svn: 27209
2006-03-28 02:29:37 +00:00
cb5ec07cc3
Use normal lvx for scalar_to_vector instead of lve*x. They do the exact
...
same thing and we have a dag node for the former.
llvm-svn: 27205
2006-03-28 01:43:22 +00:00
e55d171ccd
Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value. Split them into separate enums.
...
llvm-svn: 27201
2006-03-28 00:40:33 +00:00
fa53b276d0
Translate llvm target registers to dwarf register numbers properly.
...
llvm-svn: 27180
2006-03-27 20:18:45 +00:00
939c9ab88f
Add a bunch of notes from my journey thus far.
...
llvm-svn: 27170
2006-03-27 07:41:00 +00:00
22ec3e7b7e
Split out altivec notes into their own README
...
llvm-svn: 27168
2006-03-27 07:04:16 +00:00
1738c293b5
Fix the JIT encoding of VSEL
...
llvm-svn: 27160
2006-03-27 03:34:17 +00:00
df59d5314c
Fix the JIT encoding of VSPLTI*
...
llvm-svn: 27159
2006-03-27 03:28:57 +00:00
ed728c1291
SelectionDAGISel can now natively handle Switch instructions, in the same
...
manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks. The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.
This functionality is currently only enabled on x86, but should be safe for
every target. In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.
llvm-svn: 27156
2006-03-27 01:32:24 +00:00
65473e20d8
add vsel
...
llvm-svn: 27153
2006-03-26 22:38:43 +00:00
6961fc76bb
Codegen vector predicate compares.
...
llvm-svn: 27151
2006-03-26 10:06:40 +00:00
b1ddc988af
Remove PPC:isZeroVector, use ISD::isBuildVectorAllZeros instead
...
llvm-svn: 27149
2006-03-26 09:52:32 +00:00
793cbcb4fd
Add all of the altivec comparison instructions. Add patterns for the
...
non-predicate altivec compare intrinsics.
llvm-svn: 27143
2006-03-26 04:57:17 +00:00
c6c88b2ea1
Add and 8/16-bit adds, add all integer subtracts, add saturating subtract
...
intrinsics.
llvm-svn: 27142
2006-03-26 02:39:02 +00:00
53e07decd7
implement the vsldoi intrinsic.
...
llvm-svn: 27139
2006-03-26 00:41:48 +00:00
5c0c762443
fix the pattern for vandc, it's NOT vnand
...
llvm-svn: 27136
2006-03-25 23:10:40 +00:00
e8c1d04051
add patterns for VANDC/VNOR, implementing
...
CodeGen/PowerPC/eqv-andc-orc-nor.ll:VNOR/VANDC
llvm-svn: 27135
2006-03-25 23:05:29 +00:00
b3617beb52
Add some logical operations
...
llvm-svn: 27127
2006-03-25 22:16:05 +00:00
1b4bb22f8a
implement a bunch of intrinsics
...
llvm-svn: 27118
2006-03-25 08:01:02 +00:00
2a85fa1f79
Move all Altivec stuff out into a new PPCInstrAltivec.td file.
...
Add a bunch of patterns for different datatypes, e.g. bit_convert, undef and
zero vector support.
llvm-svn: 27117
2006-03-25 07:51:43 +00:00
1cb91b3cd9
Add some basic patterns for other datatypes
...
llvm-svn: 27116
2006-03-25 07:39:07 +00:00
3a66a75108
add all supported formats to the vector register file
...
llvm-svn: 27115
2006-03-25 07:36:56 +00:00
f653cdd3f9
Add support for __builtin_altivec_vnmsubfp /vmaddfp
...
llvm-svn: 27112
2006-03-25 07:05:55 +00:00
5d70a7c4a5
#include Intrinsics.h into all dag isels
...
llvm-svn: 27109
2006-03-25 06:47:10 +00:00
2771e2c960
Codegen things like:
...
<int -1, int -1, int -1, int -1>
and
<int 65537, int 65537, int 65537, int 65537>
Using things like:
vspltisb v0, -1
and:
vspltish v0, 1
instead of using constant pool loads.
This implements CodeGen/PowerPC/vec_splat.ll:splat_imm_i{32|16}.
llvm-svn: 27106
2006-03-25 06:12:06 +00:00
f0729b4067
Add dwarf register numbering to register data.
...
llvm-svn: 27081
2006-03-24 21:15:58 +00:00
9f9b6116e1
add another note
...
llvm-svn: 27077
2006-03-24 20:04:27 +00:00
d589dd1352
Fix a bad JIT encoding of VPERM. Why is VPERM D,A,B,C but vfmadd is D,A,C,B ??
...
llvm-svn: 27069
2006-03-24 18:24:43 +00:00
f2286d5917
Like the comment says, prefer to use the implicit add done by [r+r] addressing
...
modes than emitting an explicit add and using a base of r0. This implements
Regression/CodeGen/PowerPC/mem-rr-addr-mode.ll
llvm-svn: 27068
2006-03-24 17:58:06 +00:00
a90b7141ed
Disable the i32->float G5 optimization. It is unsafe, as documented in the
...
comment.
This fixes 177.mesa, and McCat/09-vor with the td scheduler.
llvm-svn: 27060
2006-03-24 07:53:47 +00:00
ab882abce8
add support for using vxor to build zero vectors. This implements
...
Regression/CodeGen/PowerPC/vec_zero.ll
llvm-svn: 27059
2006-03-24 07:48:08 +00:00
f5efddf80b
Gabor points out that we can't spell. :)
...
llvm-svn: 27049
2006-03-24 07:12:19 +00:00
cbcfe46556
add a note
...
llvm-svn: 27000
2006-03-23 21:28:44 +00:00
81137629e0
Add PPC vector bit-convert support
...
llvm-svn: 26995
2006-03-23 19:54:27 +00:00
3c43609f1f
Add support to locate local variables in frames (early version.)
...
llvm-svn: 26994
2006-03-23 18:12:57 +00:00
cf0166fbeb
Change interface to DwarfWriter.
...
llvm-svn: 26991
2006-03-23 18:09:44 +00:00
6f95ab7abb
Eliminate IntrinsicLowering from TargetMachine.
...
Make the CBE and V9 backends create their own, since they're the only ones that use it.
llvm-svn: 26974
2006-03-23 05:43:16 +00:00
eccf46950c
This has been implemented. Tweak it into another note
...
llvm-svn: 26944
2006-03-22 05:33:23 +00:00
4a66d69433
When possible, custom lower 32-bit SINT_TO_FP to this:
...
_foo2:
extsw r2, r3
std r2, -8(r1)
lfd f0, -8(r1)
fcfid f0, f0
frsp f1, f0
blr
instead of this:
_foo2:
lis r2, ha16(LCPI2_0)
lis r4, 17200
xoris r3, r3, 32768
stw r3, -4(r1)
stw r4, -8(r1)
lfs f0, lo16(LCPI2_0)(r2)
lfd f1, -8(r1)
fsub f0, f1, f0
frsp f1, f0
blr
This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).
llvm-svn: 26943
2006-03-22 05:30:33 +00:00
77373d1bea
Add support for "ri" addressing modes where the immediate is a 14-bit field
...
which is shifted left two bits before use. Instructions like STD use this
addressing mode.
llvm-svn: 26942
2006-03-22 05:26:03 +00:00
4e7371758f
Fix the JIT encoding of the VAForm_1 instructions, including vmaddfp
...
llvm-svn: 26935
2006-03-22 01:44:36 +00:00
00f4683bf6
These targets don't support EXTRACT_VECTOR_ELT, though, in time, X86 will.
...
llvm-svn: 26930
2006-03-21 20:51:05 +00:00
3a2ae6ad3c
Don't emit pseudo instructions!
...
llvm-svn: 26926
2006-03-21 20:19:37 +00:00
013127981a
Update readme
...
llvm-svn: 26924
2006-03-21 18:58:20 +00:00
139eac5b71
Print absolute memory references like this:
...
lwz r2, 8(0)
instead of this:
lwz r2, 8(r0)
This fixes the llc/llc-beta failures on PPC last night.
llvm-svn: 26922
2006-03-21 17:21:13 +00:00
bda7310ef7
With Evan's latest tblgen patch, this code is obsolete, thanks Evan!
...
llvm-svn: 26917
2006-03-21 06:37:40 +00:00
d2132f87d7
When codegen'ing vector MUL using VFMADD, *add* the 0, don't *mul* the 0.
...
llvm-svn: 26913
2006-03-21 00:51:38 +00:00
f194834161
minor note
...
llvm-svn: 26912
2006-03-21 00:47:09 +00:00
c8b16d00b9
Handle constant addresses more efficiently, folding the low bits into the
...
disp field of the load/store if possible. This compiles
CodeGen/PowerPC/load-constant-addr.ll to:
_test:
lis r2, 2838
lfs f1, 26848(r2)
blr
instead of:
_test:
lis r2, 2838
ori r2, r2, 26848
lfs f1, 0(r2)
blr
llvm-svn: 26908
2006-03-20 22:38:22 +00:00
6d74b09da7
remove dead variable
...
llvm-svn: 26907
2006-03-20 22:37:23 +00:00
a1bc294f0c
Fix a couple of bugs in permute/splat generate, thanks to Nate for actually
...
figuring these out! :)
llvm-svn: 26904
2006-03-20 18:26:51 +00:00
eda030da04
reenable this hack, the tblgen version isn't quite ready
...
llvm-svn: 26902
2006-03-20 17:54:43 +00:00
f96d523b8f
Fix the pattern for VADDUWM, add i32 splat
...
llvm-svn: 26901
2006-03-20 17:51:58 +00:00
89f3cff0f5
Use tblgen'd VECTOR_SHUFFLE selection code.
...
llvm-svn: 26900
2006-03-20 08:14:16 +00:00
a9a1313386
Add support for generating vspltw, instead of a vperm instruction with a
...
constant pool load. This generates significantly nicer code for splats.
When tblgen gets bugfixed, we can remove the custom selection code.
llvm-svn: 26898
2006-03-20 06:51:10 +00:00
a8fbb6dd3d
Implement PPC::isSplatShuffleMask and PPC::getVSPLTImmediate.
...
llvm-svn: 26897
2006-03-20 06:37:44 +00:00
ffc475689b
fix duplicate definition errors
...
llvm-svn: 26896
2006-03-20 06:33:01 +00:00
382f356bd9
Check in some intermediate code that adds a skeleton for matching vsplt*
...
instructions
llvm-svn: 26894
2006-03-20 06:15:45 +00:00
93d99f9928
fix typo
...
llvm-svn: 26889
2006-03-20 05:05:55 +00:00
366b2514fa
add vsplat instructions, fix sched description for vperm
...
llvm-svn: 26888
2006-03-20 04:47:33 +00:00
a8713b1ee6
Custom lower arbitrary VECTOR_SHUFFLE's to VPERM.
...
TODO: leave specific ones as VECTOR_SHUFFLE's and turn them into specialized
operations like vsplt*
llvm-svn: 26887
2006-03-20 01:53:53 +00:00
0a8b4eaee9
Claim to have v16i8 for perm masks
...
llvm-svn: 26886
2006-03-20 01:53:02 +00:00
e7a058de7d
add the vperm instruction
...
llvm-svn: 26883
2006-03-20 01:00:56 +00:00
169e6238ad
Add a note about the MUL -> FMADD vector bug.
...
llvm-svn: 26874
2006-03-19 22:08:08 +00:00
7e9440a4fc
Custom lower SCALAR_TO_VECTOR into lve*x.
...
llvm-svn: 26868
2006-03-19 06:55:52 +00:00
b1ee9c7e24
PPC doesn't have SCALAR_TO_VECTOR
...
llvm-svn: 26865
2006-03-19 06:17:19 +00:00
5b595af956
add support for vector undef
...
llvm-svn: 26863
2006-03-19 06:10:09 +00:00
0c9eb670bb
minor fixes
...
llvm-svn: 26857
2006-03-19 05:43:01 +00:00
ea6468758d
notes
...
llvm-svn: 26856
2006-03-19 05:33:30 +00:00
431c90c9fa
we don't use lmw/stmw. When we want them they are easy enough to add
...
llvm-svn: 26853
2006-03-19 04:33:37 +00:00
f7b6e7212f
rename these nodes
...
llvm-svn: 26848
2006-03-19 01:13:28 +00:00
21f87d0e4c
Fix subfic to match subc by default instead of sub so that it is correctly
...
cost-modeled as producing a flag. This fixes the test I just added for neg
llvm-svn: 26835
2006-03-17 22:41:37 +00:00
bb01d4f272
Remove BRTWOWAY*
...
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
llvm-svn: 26814
2006-03-17 01:40:33 +00:00
8bf1c59e7f
remove dead variable
...
llvm-svn: 26813
2006-03-16 23:52:08 +00:00
fb0e36fa56
Notes on how to kill the eeevil brtwoway, and make ppc branch selector
...
more target independant, generate better code, and be less conservative.
llvm-svn: 26809
2006-03-16 22:37:48 +00:00
1e6dfa4c1f
Strangely, calls clobber call-clobbered vector regs. Whodathoughtit?
...
llvm-svn: 26808
2006-03-16 22:35:59 +00:00
325bb46315
add a note
...
llvm-svn: 26807
2006-03-16 22:25:55 +00:00
91400bd413
teach the ppc backend how to spill/reload vector regs
...
llvm-svn: 26806
2006-03-16 22:24:02 +00:00
6e90062416
add callee saved vector regs
...
llvm-svn: 26805
2006-03-16 22:07:06 +00:00
20931a798e
Added a way for TargetLowering to specify what values can be used as the
...
scale component of the target addressing mode.
llvm-svn: 26802
2006-03-16 21:47:42 +00:00
0b27047a6c
in functions that use a lot of callee saved regs, this can be more than
...
5 instructions away.
llvm-svn: 26801
2006-03-16 21:31:45 +00:00
fd9f3e8ed3
Add support for copying registers. still needed: spilling and reloading them
...
llvm-svn: 26800
2006-03-16 20:03:58 +00:00
32e73f9881
Another case we could do better on.
...
llvm-svn: 26795
2006-03-16 18:50:44 +00:00
1678a6c477
Save/restore VRSAVE once per function, not once per block.
...
llvm-svn: 26793
2006-03-16 18:25:23 +00:00
2e1fde7c5c
Update scheduling info for vrsave instruction
...
llvm-svn: 26776
2006-03-15 05:25:05 +00:00
ab1ed2aa96
Fix an off by one error that caused PPC LLC failures last night.
...
llvm-svn: 26758
2006-03-14 17:56:49 +00:00
0f9d6534f5
PPC LSR pass should use target lowering hooks.
...
llvm-svn: 26743
2006-03-13 23:56:51 +00:00
2dd2c652b2
Added getTargetLowering() to TargetMachine. Refactored targets to support this.
...
llvm-svn: 26742
2006-03-13 23:20:37 +00:00
02e2c18c9c
For functions that use vector registers, save VRSAVE, mark used
...
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
llvm-svn: 26733
2006-03-13 21:52:10 +00:00
ec9d0bc3ec
Fix a couple of bugs that broke the alpha tester build
...
llvm-svn: 26722
2006-03-13 05:23:59 +00:00
4fbb612685
Handle cracked instructions in dispatch group formation.
...
llvm-svn: 26721
2006-03-13 05:20:04 +00:00
7579cfb1a0
Mark instructions that are cracked by the PPC970 decoder as such.
...
llvm-svn: 26720
2006-03-13 05:15:10 +00:00
51348c5f27
Several big changes:
...
1. Use flags on the instructions in the .td file to indicate the PPC970 unit
type instead of a table in the .cpp file. Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
accurately.
llvm-svn: 26719
2006-03-12 09:13:49 +00:00
d03132a409
blr is a branch too
...
llvm-svn: 26710
2006-03-11 21:49:49 +00:00
c2447e8b59
teach the JIT to encode vector registers
...
llvm-svn: 26697
2006-03-10 20:19:50 +00:00
543832d39d
Change the interface for getting a target HazardRecognizer to be more clean.
...
llvm-svn: 26608
2006-03-08 04:25:59 +00:00
a8dd636192
add a note
...
llvm-svn: 26605
2006-03-08 00:25:47 +00:00
313570fb17
Use "llvm.metadata" section for debug globals. Filter out these globals in the
...
asm printer.
llvm-svn: 26599
2006-03-07 22:00:35 +00:00
907e13c742
add another missing store.
...
llvm-svn: 26595
2006-03-07 16:26:48 +00:00
8c73d80b08
add a couple more load/store instrs, add a newline to the end of file.
...
llvm-svn: 26594
2006-03-07 16:19:46 +00:00
3e3219cc0a
This kinda sorta implements "things that have to lead a dispatch group".
...
llvm-svn: 26591
2006-03-07 08:30:27 +00:00
675567f77c
add some new instructions to the classifier. With this, we correctly insert
...
a nop into Freebench/neural, which speeds it up from 136->129s (~5.4%).
llvm-svn: 26590
2006-03-07 07:14:55 +00:00
05ad128dca
add some comments that describe what we model
...
llvm-svn: 26588
2006-03-07 06:44:19 +00:00
2cab13573c
Implement a very very simple hazard recognizer for LSU rejects and ctr set/read
...
flushes
llvm-svn: 26587
2006-03-07 06:32:48 +00:00
883cefc656
add a note
...
llvm-svn: 26585
2006-03-07 04:42:59 +00:00
ea79d9fd73
implement TII::insertNoop
...
llvm-svn: 26562
2006-03-05 23:49:55 +00:00
9c7f50376a
Copysign needs to be expanded everywhere. Note that Alpha and IA64 should
...
implement copysign as a native op if they have it.
llvm-svn: 26541
2006-03-05 05:08:37 +00:00
60a60f4b1e
Implement CodeGen/PowerPC/or-addressing-mode.ll, which is also PR668.
...
llvm-svn: 26450
2006-03-01 07:14:48 +00:00
3cb349a068
add a note
...
llvm-svn: 26448
2006-03-01 06:36:20 +00:00
27f5345b1f
Compile this:
...
void foo(float a, int *b) { *b = a; }
to this:
_foo:
fctiwz f0, f1
stfiwx f0, 0, r4
blr
instead of this:
_foo:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
stw r2, 0(r4)
blr
This implements CodeGen/PowerPC/stfiwx.ll, and also incidentally does the
right thing for GCC bugzilla 26505.
llvm-svn: 26447
2006-03-01 05:50:56 +00:00
f418435819
Use a target-specific dag-combine to implement CodeGen/PowerPC/fp-int-fp.ll.
...
llvm-svn: 26445
2006-03-01 04:57:39 +00:00
1926427351
Vector op lowering.
...
llvm-svn: 26438
2006-03-01 01:11:20 +00:00
b9f35f06bc
Add a subtarget feature for the stfiwx instruction. I know the G5 has it,
...
but I don't know what other PPC impls do. If someone could update the proc
table, I would appreciate it :)
llvm-svn: 26421
2006-02-28 07:08:22 +00:00
872810da6c
remove implemented item
...
llvm-svn: 26418
2006-02-28 06:36:04 +00:00
f918ed2e33
readme updates
...
llvm-svn: 26405
2006-02-27 22:08:36 +00:00
7674d90fa1
Add memory printing support for PPC. Input memory operands now work with
...
inline asms! :)
llvm-svn: 26365
2006-02-24 20:27:40 +00:00
a1ec1ddd59
Implement selection of inline asm memory operands
...
llvm-svn: 26348
2006-02-24 02:13:12 +00:00
0ed48fe601
PPC JIT relocation model should be DynamicNoPIC.
...
llvm-svn: 26338
2006-02-23 22:18:07 +00:00
1bad2546d0
Implement the PPC inline asm "L" modifier. This allows us to compile:
...
long long test(long long X) {
__asm__("foo %0 %L0 %1 %L1" : "=r"(X): "r"(X));
return X;
}
to:
foo r2 r3 r2 r3
llvm-svn: 26333
2006-02-23 19:31:10 +00:00
73136dfecc
- Added option -relocation-model to set relocation model. Valid values include static, pic,
...
dynamic-no-pic, and default.
PPC and x86 default is dynamic-no-pic for Darwin, pic for others.
- Removed options -enable-pic and -ppc-static.
llvm-svn: 26315
2006-02-22 20:19:42 +00:00
2fa33a989d
Coordinate activities with llvm-gcc4 and dwarf.
...
llvm-svn: 26314
2006-02-22 19:02:11 +00:00
7ad77dfc2a
split register class handling from explicit physreg handling.
...
llvm-svn: 26308
2006-02-22 00:56:39 +00:00
7bb4696dc3
Updates to match change of getRegForInlineAsmConstraint prototype
...
llvm-svn: 26305
2006-02-21 23:11:00 +00:00
5f99760ae7
Moved PICEnabled to include/llvm/Target/TargetOptions.h
...
llvm-svn: 26272
2006-02-18 00:08:58 +00:00
5965bd19f8
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
...
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
llvm-svn: 26255
2006-02-17 05:43:56 +00:00
42c01c8d39
If the false case is the current basic block, then this is a self loop.
...
We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra
instruction in the loop. Instead, invert the condition and emit
"Loop: ... br!cond Loop; br Out.
Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering.
llvm-svn: 26231
2006-02-16 08:27:56 +00:00
b134520b86
If we have zero initialized data with external linkage, use .zerofill to
...
emit it (instead of .space), saving a bit of space in the .o file.
For example:
int foo[100];
int bar[100] = {};
when compiled with C++ or -fno-common results in shrinkage from 1160 to 360
bytes of space. The X86 backend can also do this on darwin.
llvm-svn: 26185
2006-02-14 22:18:23 +00:00
84fb09eba4
Make sure that weak functions are aligned properly
...
llvm-svn: 26181
2006-02-14 20:42:33 +00:00
3a0ad47b39
Switch to using getCALLSEQ_START instead of using our own creation calls
...
llvm-svn: 26142
2006-02-13 08:55:29 +00:00
bc3ec1d37b
Add missing patterns for andi. and andis., fixing test/Regression/CodeGen/
...
PowerPC/and-imm.ll
llvm-svn: 26136
2006-02-12 09:09:52 +00:00
d1b82d8db0
Match getTargetNode() changes (now return SDNode* instead of SDOperand).
...
llvm-svn: 26085
2006-02-09 07:17:49 +00:00
6dc90ca172
Change Select() from
...
SDOperand Select(SDOperand N);
to
void Select(SDOperand &Result, SDOperand N);
llvm-svn: 26067
2006-02-09 00:37:58 +00:00
2e07d6370a
Darwin doesn't support #APP/#NO_APP
...
llvm-svn: 26066
2006-02-08 23:42:22 +00:00
26e385a623
Rename BSel -> PPCBSel for the benefit of doxygen users.
...
Move the methods out of line.
Remove unused Debug.h stuff.
Teach getNumBytesForInstruction to know the size of an inline asm.
llvm-svn: 26064
2006-02-08 19:33:26 +00:00
f7b962d7d7
Emit the 'mr' pseudoop for easier reading.
...
llvm-svn: 26053
2006-02-08 06:56:40 +00:00
b97142eec0
Move emails from nate into public places
...
llvm-svn: 26051
2006-02-08 06:43:51 +00:00
203b2f1288
Implement getConstraintType for PPC.
...
llvm-svn: 26042
2006-02-07 20:16:30 +00:00
15a6c4c444
Add the simple PPC integer constraints
...
llvm-svn: 26027
2006-02-07 00:47:13 +00:00
2bf2c8d7e7
Change prototype
...
llvm-svn: 26022
2006-02-06 22:18:19 +00:00
58d48c8118
We seem to have settled to __DWARF for section name.
...
llvm-svn: 26015
2006-02-06 14:16:15 +00:00
bfa4b7cc75
Complex pattern isel code shouldn't select nodes.
...
llvm-svn: 26010
2006-02-05 08:45:01 +00:00
54cb1833a4
Use SelectRoot() as entry of any tblgen based isel.
...
llvm-svn: 25997
2006-02-05 06:46:41 +00:00
c0e48c6c58
add a note
...
llvm-svn: 25984
2006-02-05 05:27:35 +00:00
1b1a8731c0
Use the asmprinter to find out what the preferred alignment of a global is.
...
This patch speeds up 172.mgrid from 31.81s to 11.39s on darwin/ppc.
Many many thanks to Nate for tracking down the root cause of the issue.
llvm-svn: 25979
2006-02-05 01:30:45 +00:00
a1e895cf97
Remove some stuff that now works
...
llvm-svn: 25963
2006-02-04 07:29:35 +00:00
81e66abd1e
add a note
...
llvm-svn: 25944
2006-02-03 22:06:45 +00:00
a23b04acdb
remove some target-indep and implemented notes
...
llvm-svn: 25930
2006-02-03 06:22:11 +00:00
fc567d85d5
Flesh out a couple of the items in the README
...
llvm-svn: 25928
2006-02-03 05:17:06 +00:00
f0a2d66d1c
Add a note
...
llvm-svn: 25921
2006-02-03 01:49:49 +00:00
9b178ce225
update a note
...
llvm-svn: 25918
2006-02-02 23:50:22 +00:00
4efb328926
add 64b gpr store to the possible list of isStoreToStackSlot opcodes.
...
llvm-svn: 25916
2006-02-02 21:07:50 +00:00
c327d71e06
implement isStoreToStackSlot for PPC
...
llvm-svn: 25914
2006-02-02 20:16:12 +00:00
bb53acd03c
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :)
...
llvm-svn: 25913
2006-02-02 20:12:32 +00:00
9dd7df7ee7
new example
...
llvm-svn: 25903
2006-02-02 07:37:11 +00:00
cd018525f8
Update the README
...
llvm-svn: 25902
2006-02-02 07:27:56 +00:00
f7f056751c
add a method
...
llvm-svn: 25884
2006-02-01 22:38:46 +00:00
a983beab37
add a note
...
llvm-svn: 25876
2006-02-01 17:54:23 +00:00
7e7f439f85
Fix some of the stuff in the PPC README file, and clean up legalization
...
of the SELECT_CC, BR_CC, and BRTWOWAY_CC nodes.
llvm-svn: 25875
2006-02-01 07:19:44 +00:00
a0527473ac
another testcase.
...
llvm-svn: 25862
2006-02-01 00:28:12 +00:00
32be2dc0af
Allow the specification of explicit alignments for constant pool entries.
...
llvm-svn: 25855
2006-01-31 22:23:14 +00:00
0151361d21
add info about the inline asm register constraints for PPC
...
llvm-svn: 25853
2006-01-31 19:20:21 +00:00
a162f208ee
Codegen
...
bool %test(int %X) {
%Y = seteq int %X, 13
ret bool %Y
}
as
_test:
addi r2, r3, -13
cntlzw r2, r2
srwi r3, r2, 5
blr
rather than
_test:
cmpwi cr7, r3, 13
mfcr r2
rlwinm r3, r2, 31, 31, 31
blr
This has very little effect on most code, but speeds up analyzer 23% and
mason 11%
llvm-svn: 25848
2006-01-31 08:17:29 +00:00
b0fe138b65
example nate pointed out
...
llvm-svn: 25841
2006-01-31 07:16:34 +00:00
a9bfca8d1e
add the 'lucas' optimization
...
llvm-svn: 25830
2006-01-31 02:55:28 +00:00
32058cfb7b
Functions that are lazily streamed in from the .bc file are *not* external.
...
This fixes llvm-test/SingleSource/UnitTests/2006-01-29-SimpleIndirectCall.c
and PR704
llvm-svn: 25793
2006-01-29 20:49:17 +00:00
3072af4d4f
Now that OpActions is big enough, we can specify actions for vector types
...
llvm-svn: 25784
2006-01-29 08:41:37 +00:00
d7738e6b32
disable this for now
...
llvm-svn: 25778
2006-01-29 07:31:33 +00:00
d33c60b52b
Request expansion of ConstantVec nodes.
...
llvm-svn: 25773
2006-01-29 06:32:58 +00:00
61c9a8e942
Targets all now request ConstantFP to be legalized into TargetConstantFP.
...
'fpimm' in .td files is now TargetConstantFP.
llvm-svn: 25771
2006-01-29 06:26:08 +00:00
30432e07f0
Fix a bug in my elimination of ISD::CALL this morning. PPC now has to
...
provide the expansion for i64 calls itself
llvm-svn: 25735
2006-01-28 07:33:03 +00:00
0c7b4666a3
add a note about how we should implement this FIXME from the legalizer:
...
// FIXME: revisit this when we have some kind of mechanism by which targets
// can decided legality of vector constants, of which there may be very
// many.
llvm-svn: 25733
2006-01-28 05:40:47 +00:00
6c82262289
Add a couple more things to the readme.
...
llvm-svn: 25724
2006-01-28 01:22:10 +00:00
f424a66524
Use PPCISD::CALL instead of ISD::CALL
...
llvm-svn: 25717
2006-01-27 23:34:02 +00:00
4d967a4cbb
Make llvm.frame/returnaddr not crash on ppc
...
llvm-svn: 25710
2006-01-27 22:25:06 +00:00
8c47c3a3b1
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
...
the same functionality. This addresses another piece of bug 680. Next,
on to fixing Alpha VAARG, which I broke last time.
llvm-svn: 25696
2006-01-27 21:09:22 +00:00
d98701c639
Subtarget feature can now set any variable to any value
...
llvm-svn: 25678
2006-01-27 08:09:42 +00:00
1240574609
PHI and INLINEASM are now built-in instructions provided by Target.td
...
llvm-svn: 25674
2006-01-27 01:46:15 +00:00
0bbdc55333
Set up MachineDebugInfo to scan for debug information form "llvm.db"g globals.
...
Global Variable information is now pulled from "llvm.dbg.globals"
llvm-svn: 25655
2006-01-26 20:21:46 +00:00
030e002fb9
Set SchedulingForLatency to be the default scheduling preference for all.
...
llvm-svn: 25607
2006-01-25 18:52:42 +00:00
e74795cd70
First part of bug 680:
...
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
llvm-svn: 25606
2006-01-25 18:21:52 +00:00
1092a02619
Default scheduling preference is SchedulingForLatency.
...
llvm-svn: 25603
2006-01-25 09:15:54 +00:00
3e65f28ffe
Crude Dwarf global variable debugging.
...
llvm-svn: 25569
2006-01-24 00:49:18 +00:00
de02d7727f
Add explicit #includes of <iostream>
...
llvm-svn: 25515
2006-01-22 23:41:00 +00:00
469640e506
Add explicit #includes of <iostream>
...
llvm-svn: 25509
2006-01-22 22:53:01 +00:00
9436aa74a9
trivial formatting improvement: don't insert extra blank lines between .comm
...
vars.
llvm-svn: 25492
2006-01-21 01:35:26 +00:00
c3c27032d0
add a note
...
llvm-svn: 25439
2006-01-19 02:09:38 +00:00
ce5066c863
Don't assert on 'select_cc SETUO'
...
llvm-svn: 25423
2006-01-18 19:42:35 +00:00
36eba3a49b
fix out of date comment
...
llvm-svn: 25422
2006-01-18 19:37:44 +00:00
15e7642ab1
Fix Regression/CodeGen/PowerPC/2006-01-18-InvalidBranchOpcodeAssert.ll
...
llvm-svn: 25421
2006-01-18 19:35:21 +00:00
194a5268cb
Added minimum Dwarf aranges. Cleaned up some section headers. Line number
...
support now works in gdb.
llvm-svn: 25417
2006-01-18 16:54:26 +00:00
cc9dfecf81
Add frame work for additional dwarf sections. Comments will improve as code
...
is added.
llvm-svn: 25410
2006-01-17 20:41:40 +00:00
b9966029fe
Adding basic support for Dwarf line number debug information.
...
I promise to keep future commits smaller.
llvm-svn: 25396
2006-01-17 17:31:53 +00:00
7c76290038
add notes from my *other* email acct.
...
llvm-svn: 25362
2006-01-16 17:58:54 +00:00
b2eacf48aa
transfer some notes from my email to somewhere useful.
...
llvm-svn: 25361
2006-01-16 17:53:00 +00:00
5bd514d7b0
Use the default impl of DYNAMIC_STACKALLOC, allowing us to delete some code.
...
llvm-svn: 25334
2006-01-15 09:02:48 +00:00
2fba8a3aaa
bswap implementation
...
llvm-svn: 25312
2006-01-14 03:14:10 +00:00
f2b38dbdc7
Remove some redundant stuff out of the readme.
...
llvm-svn: 25308
2006-01-14 01:24:22 +00:00
776c326c96
implement stacksave/stackrestore on PPC
...
llvm-svn: 25277
2006-01-13 17:52:03 +00:00
8e2f52e645
expand unsupported stacksave/stackrestore nodes
...
llvm-svn: 25272
2006-01-13 02:42:53 +00:00
268d3584fc
ahem :)
...
llvm-svn: 25239
2006-01-12 02:05:36 +00:00
1014b38404
these cases are autogenerated
...
llvm-svn: 25238
2006-01-12 02:01:45 +00:00
44416f92f1
remove dead code
...
llvm-svn: 25237
2006-01-12 01:54:15 +00:00
33792a483a
Goodbye PPC pattern isel. You have served us well, but it is now time for
...
you to ride off into the sunset.
llvm-svn: 25236
2006-01-12 01:46:07 +00:00
2812e79c23
Fix an off-by-one error that Nate's eagle eyes caught
...
llvm-svn: 25231
2006-01-11 23:16:29 +00:00
dc43a3f237
Use the auto-insert BuildMI constructor to avoid an explicit insert. No
...
functionality change, just code cleanup.
llvm-svn: 25230
2006-01-11 23:07:57 +00:00
3280da3cda
If a function has a non-zero sized frame, use an add to adjust the stack
...
pointer in the epilog, not a load.
llvm-svn: 25229
2006-01-11 23:03:54 +00:00
1b8121b227
Add bswap, rotl, and rotr nodes
...
Add dag combiner code to recognize rotl, rotr
Add ppc code to match rotl
Targets should add rotl/rotr patterns if they have them
llvm-svn: 25222
2006-01-11 21:21:00 +00:00
602dfea79c
Fix calls that need to store values in stack slots, to not copy the stack
...
pointer. This allows us to emit stuff like this:
li r10, 0
stw r10, 56(r1)
or r3, r10, r10
or r4, r10, r10
or r5, r10, r10
or r6, r10, r10
or r7, r10, r10
or r8, r10, r10
or r9, r10, r10
bl L_bar$stub
instead of this:
or r2, r1, r1 ;; Extraneous copy.
li r10, 0
stw r10, 56(r2)
or r3, r10, r10
or r4, r10, r10
or r5, r10, r10
or r6, r10, r10
or r7, r10, r10
or r8, r10, r10
or r9, r10, r10
bl L_bar$stub
wowness.
llvm-svn: 25221
2006-01-11 19:55:07 +00:00
66f63f72f3
Dead FP arguments still use an incoming FP reg. This fixes
...
Regression/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll, which was
distilled from a miscompilation in 252.eon.
llvm-svn: 25217
2006-01-11 18:21:25 +00:00
477933cfbd
Remove a comment that no longer applies.
...
llvm-svn: 25167
2006-01-10 00:15:59 +00:00
347ed8a581
Give PPCISD:: nodes legible names in dumps.
...
llvm-svn: 25166
2006-01-09 23:52:17 +00:00
bfb2de9030
add ret void support back
...
llvm-svn: 25164
2006-01-09 23:20:37 +00:00
7785e5b3a4
New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace
...
hasInFlag, hasOutFlag.
llvm-svn: 25155
2006-01-09 18:28:21 +00:00
1185e73cc9
Fix the PPC JIT failures last night, which were due to mishandling of linkonce globals
...
llvm-svn: 25141
2006-01-07 06:22:16 +00:00
b87030358d
linkonce symbols have an extra indirection, just like weak ones do. This fixes
...
Prolangs-C++/family and Prolangs-C++/primes.
llvm-svn: 25119
2006-01-06 01:04:03 +00:00
20c88dfd1b
Fix a compile crash building MultiSource/Applications/d with the new front-end.
...
The PPC backend was generating random shift counts in this case, due to an
uninitialized variable.
llvm-svn: 25114
2006-01-05 18:32:49 +00:00
deeafa0f00
Had expand logic backward.
...
llvm-svn: 25105
2006-01-05 01:47:43 +00:00
762e9ec06c
Added initial support for DEBUG_LABEL allowing debug specific labels to be
...
inserted in the code.
llvm-svn: 25104
2006-01-05 01:25:28 +00:00
219d559824
Applied some recommend changes from sabre. The dominate one beginning "let the
...
pass manager do it's thing." Fixes crash when compiling -g files and suppresses
dwarf statements if no debug info is present.
llvm-svn: 25100
2006-01-04 22:28:25 +00:00
0da76a676a
Add unique id to debug location for debug label use (work in progress.)
...
llvm-svn: 25096
2006-01-04 15:04:11 +00:00
b0609d91c3
Tie dwarf generation to darwin assembler.
...
llvm-svn: 25093
2006-01-04 13:52:30 +00:00
336dba6fb1
Add support for generating v4i32 altivec code
...
llvm-svn: 25046
2005-12-30 00:12:56 +00:00
c2c8a6202f
Remove a fixme
...
llvm-svn: 25045
2005-12-30 00:11:07 +00:00
14c53b45f5
Added field noResults to Instruction.
...
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.
llvm-svn: 25017
2005-12-26 09:11:45 +00:00
9aea6e4691
Fix one of the things in the todo file, and get a bit closer to folding
...
constant offsets from statics into the address arithmetic.
llvm-svn: 24999
2005-12-24 01:00:15 +00:00
9ae486047e
* Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.
...
* Added a pseudo instruction (for each target) that represent "return void".
This is a workaround for lack of optional flag operand (return void is not
lowered so it does not have a flag operand.)
llvm-svn: 24997
2005-12-23 22:14:32 +00:00
c46fc2482c
make sure bit_converts are expanded
...
llvm-svn: 24978
2005-12-23 05:13:35 +00:00
f474034432
Simplify some code by using BIT_CONVERT
...
llvm-svn: 24974
2005-12-23 00:59:59 +00:00
177d7af5d5
remove dead code
...
llvm-svn: 24965
2005-12-22 21:16:08 +00:00
6b0325aa26
fix handling of weak linkage
...
llvm-svn: 24964
2005-12-22 21:15:17 +00:00
ffe3542726
move some random notes out of my email into someplace useful
...
llvm-svn: 24956
2005-12-22 17:19:28 +00:00
dfad8ed54e
Bye bye HACKTROCITY.
...
llvm-svn: 24935
2005-12-22 02:26:21 +00:00
82285c55aa
Flip the meaning of FPContractions to reflect Requires<[]> change.
...
llvm-svn: 24884
2005-12-20 20:08:53 +00:00
b11b8e44fa
Pattern-match return. Includes gross hack!
...
llvm-svn: 24874
2005-12-20 00:26:01 +00:00
c126397a69
Fix a couple of the FIXMEs, thanks to suggestion from Chris. This allows
...
us to load and store vectors directly at a pointer (offset of zero) by
using r0 as the base register. This also requires some asm printer work
to satisfy the darwin assembler.
For
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = add <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
We now produce:
_foo:
lvx v0, 0, r3
vaddfp v0, v0, v0
stvx v0, 0, r3
blr
Instead of:
_foo:
li r2, 0
lvx v0, r2, r3
vaddfp v0, v0, v0
stvx v0, r2, r3
blr
llvm-svn: 24872
2005-12-19 23:40:42 +00:00
8e6a8af205
Convert load/store over to being pattern matched
...
llvm-svn: 24871
2005-12-19 23:25:09 +00:00
2f5fb6a720
This is handled by the autogen'd code
...
llvm-svn: 24834
2005-12-18 21:06:11 +00:00
7c462768ed
Added source file/line correspondence for dwarf (PowerPC only at this point.)
...
llvm-svn: 24748
2005-12-16 22:45:29 +00:00
887af88ce3
Weak and linkonce global vars should still have a .globl emitted for them
...
llvm-svn: 24747
2005-12-16 21:46:14 +00:00
672578bd94
Add a second vector type to the VRRC register class, and fix some patterns
...
so that tablegen can infer all types.
llvm-svn: 24746
2005-12-16 09:19:13 +00:00
575751151c
Update the darwin handling of linkonce & weak functions and GV stubs. This
...
should work in all permutations.
llvm-svn: 24728
2005-12-16 00:22:14 +00:00
808f7a8abb
Remove a now unused statistic.
...
llvm-svn: 24720
2005-12-14 22:56:16 +00:00
e37cb604c1
Use the new predicate support that Evan Cheng added to remove some code
...
from the DAGToDAG cpp file. This adds pattern support for vector and
scalar fma, which passes test/Regression/CodeGen/PowerPC/fma.ll, and
does the right thing in the presence of -disable-excess-fp-precision.
Allows us to match:
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
%tmp3 = add <4 x float> %tmp2, %tmp1
store <4 x float> %tmp3, <4 x float> *%a
ret void
}
As:
_foo:
li r2, 0
lvx v0, r2, r3
vmaddfp v0, v0, v0, v0
stvx v0, r2, r3
blr
Or, with llc -disable-excess-fp-precision,
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v1, v0, v0, v1
vaddfp v0, v1, v0
stvx v0, r2, r3
blr
llvm-svn: 24719
2005-12-14 22:54:33 +00:00
3db275d996
Added predicate !NoExcessFPPrecision to FMADD, FMADDS, FMSUB, and FMSUBS.
...
llvm-svn: 24716
2005-12-14 22:07:12 +00:00
40f081d8e0
Add support for fmul node of type v4f32.
...
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
Is selected to:
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v0, v0, v0, v1
stvx v0, r2, r3
blr
llvm-svn: 24701
2005-12-14 00:34:09 +00:00
69caef2b78
Prepare support for AltiVec multiply, divide, and sqrt.
...
llvm-svn: 24700
2005-12-13 22:55:22 +00:00
87079884d1
Use the shared asmprinter code for printing special llvm globals
...
llvm-svn: 24695
2005-12-13 06:32:50 +00:00
54a11df95d
reindent a loop, unswitch a loop. No functionality changes
...
llvm-svn: 24692
2005-12-13 04:33:58 +00:00
090eed0483
Remove type casts that are no longer needed
...
llvm-svn: 24661
2005-12-11 07:45:47 +00:00
3d9559fedc
Fix the JIT failures from last night.
...
llvm-svn: 24659
2005-12-11 07:37:41 +00:00
4e56db674c
Add support for TargetConstantPool nodes to the dag isel emitter, and use
...
them in the PPC backend, to simplify some logic out of Select and
SelectAddr.
llvm-svn: 24657
2005-12-10 02:36:00 +00:00
ade6f9a255
Add support patterns to many load and store instructions which will
...
hopefully use patterns in the near future.
llvm-svn: 24651
2005-12-09 23:54:18 +00:00
e0f5f8e43c
Teach the PPC backend about the ctor and dtor list when not using __main and
...
linking the entire program into one bc file.
llvm-svn: 24645
2005-12-09 18:24:29 +00:00
29e6c3dbf9
Add another important case we miss
...
llvm-svn: 24639
2005-12-08 07:13:28 +00:00
de085f0165
Silence another annoying GCC warning
...
llvm-svn: 24627
2005-12-06 20:56:18 +00:00
fea33f7e64
Use new PPC-specific nodes to represent shifts which require the 6-bit
...
amount handling that PPC provides. These are generated by the lowering code
and prevents the dag combiner from assuming (rightfully) that the shifts
don't only look at 5 bits. This fixes a miscompilation of crafty with
the new front-end.
llvm-svn: 24615
2005-12-06 02:10:38 +00:00
f3322af5c6
Add some explicit type casts so that tblgen knows the type of the shift
...
amount, which is not necessarily the same as the type being shifted.
llvm-svn: 24594
2005-12-05 02:34:05 +00:00
efc86f5f7a
The basic fneg cases are already autogen'd
...
llvm-svn: 24592
2005-12-04 19:04:38 +00:00
f979794717
Autogen matching code for ADJCALLSTACK[UP|DOWN], thanks to Evan's tblgen
...
improvements.
llvm-svn: 24591
2005-12-04 19:01:59 +00:00
fd857daa0d
Finish moving uncond br over to .td file, remove from .cpp file.
...
llvm-svn: 24590
2005-12-04 18:48:01 +00:00
d9d18aff6a
Define BR in the .td file now that Evan made tblgen smarter.
...
llvm-svn: 24589
2005-12-04 18:42:54 +00:00
df9287836e
Make sure these get added into the codegenmap when appropriate
...
llvm-svn: 24566
2005-12-01 18:09:22 +00:00
006bb04f3a
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
...
work. This change has no effect on generated code.
llvm-svn: 24563
2005-12-01 04:51:06 +00:00
aa5f8f2a26
Cosmetic change, better reflects actual values
...
llvm-svn: 24562
2005-12-01 04:48:26 +00:00
bd099102f0
Fix a regression caused by a patch earlier today
...
llvm-svn: 24561
2005-12-01 03:50:19 +00:00
d94aa71e1a
Use a getCopyToReg() variant to generate a flaggy CopyToReg node.
...
llvm-svn: 24558
2005-12-01 00:41:50 +00:00
e318977940
SelectNodeTo now returns N. Use it instead of return N directly.
...
llvm-svn: 24549
2005-11-30 22:53:06 +00:00
3713e6b49c
Fix Regression/CodeGen/PowerPC/2005-11-30-vastart-crash.ll
...
llvm-svn: 24547
2005-11-30 20:40:54 +00:00
6f8c1ace6e
No longer track value types for asm printer operands, and remove them as
...
an argument to every operand printing function. Requires some slight
tweaks to x86, the only user.
llvm-svn: 24541
2005-11-30 18:54:35 +00:00
1064d6ec43
First chunk of actually generating vector code for packed types. These
...
changes allow us to generate the following code:
_foo:
li r2, 0
lvx v0, r2, r3
vaddfp v0, v0, v0
stvx v0, r2, r3
blr
for this llvm:
void %foo(<4 x float>* %a) {
entry:
%tmp1 = load <4 x float>* %a
%tmp2 = add <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float>* %a
ret void
}
llvm-svn: 24534
2005-11-30 08:22:07 +00:00
048b26387b
Represent the encoding of the SPR instructions as they actually are, so
...
that we can use the correct SPR numbers in the InstrInfo.td file. This is
necessary to support VRsave.
llvm-svn: 24521
2005-11-29 22:42:50 +00:00
3e7db9c6d5
Hook up one type, v4f32, to the VR RegisterClass for now.
...
llvm-svn: 24517
2005-11-29 08:17:20 +00:00
c138118cdb
Add the remainder of the AltiVec 4 x float instructions. Further
...
enhancements will be necessary to teach the code generator that since
there is no fmul, it will have to do vmaddfp, adding +0.0.
llvm-svn: 24516
2005-11-29 08:04:45 +00:00
9c415364cf
No targets support line number info yet.
...
llvm-svn: 24513
2005-11-29 06:16:21 +00:00
89b049af90
Add the majority of the vector machien value types we expect to support,
...
and make a few changes to the legalization machinery to support more than
16 types.
llvm-svn: 24511
2005-11-29 05:45:29 +00:00
1d4af53444
Fixed a comment bug:
...
createPPCPatternInstructionSelector -> createPPCISelPattern
llvm-svn: 24510
2005-11-29 04:59:46 +00:00
7a18a25d33
don't say this is i128, because it isn't yet. Hopefully nate will change
...
this to be something sane, but in the mean time it is unused, so safe to
make something bogus.
llvm-svn: 24504
2005-11-29 00:41:40 +00:00
11fd6b22b1
Small tweaks noticed while on the plane.
...
llvm-svn: 24492
2005-11-26 22:39:34 +00:00
8492fd30ab
Some first bits of AltiVec stuff: Instruction Formats, Encodings, and
...
Registers. Apologies to Jim if the scheduling info so far isn't accurate.
There's a few more things like VRsave support that need to be finished up
in my local tree before I can commit code that Does The Right Thing for
turning 4 x float into the various altivec packed float instructions.
llvm-svn: 24489
2005-11-23 05:29:52 +00:00
ef83ebd45d
Use generic constant pool emission code in the AsmPrinter class.
...
llvm-svn: 24465
2005-11-21 08:26:15 +00:00
ffbfa71866
Use the FunctionNumber provided by the AsmPrinter class
...
llvm-svn: 24462
2005-11-21 08:14:07 +00:00
dd3bf8e4a2
Use CommentString where possible, fix a bug where aix mode wouldn't assemble
...
due to basic blocks being misnamed.
llvm-svn: 24459
2005-11-21 08:02:41 +00:00
a0222a1698
unify the darwin and aix constant pool printers
...
llvm-svn: 24458
2005-11-21 07:57:37 +00:00
99946fb63f
Adjust to capitalized AsmPrinter method names
...
llvm-svn: 24456
2005-11-21 07:51:23 +00:00
c2bc19af57
use PrivateGlobalPrefix for basic blocks
...
llvm-svn: 24453
2005-11-21 07:41:05 +00:00
b650241f8b
This is now implemented in common codegen code
...
llvm-svn: 24446
2005-11-21 07:06:58 +00:00
41cb115afb
set PrivateGlobalPrefix on darwin, use it when printing out CP references
...
llvm-svn: 24441
2005-11-21 06:47:58 +00:00
cdde9990b7
only use dyld stubs if not in ppc-static mode. This completes support for
...
non-static codegen.
llvm-svn: 24403
2005-11-17 19:40:30 +00:00
6ab87fa360
refactor call operand handling to eliminate special cases from printOp.
...
llvm-svn: 24401
2005-11-17 19:25:59 +00:00
bd9efdb64c
disentangle call operands from branch operands a bit
...
llvm-svn: 24400
2005-11-17 19:16:08 +00:00
3570cf456b
add an option to generate completely non-pic code, corresponding to what
...
gcc -static produces on PPC. This is used for building kexts and other things.
With this, materializing the address of a global looks like:
lis r2, ha16(L_H$non_lazy_ptr)
la r3, lo16(L_H$non_lazy_ptr)(r2)
we're still emitting stubs for functions, which is wrong. That is next.
llvm-svn: 24399
2005-11-17 18:55:48 +00:00
8f8ed28a64
Fix a bug that resistor on IRC hit where we tried to create token factor
...
nodes of load results, not of their chain results.
llvm-svn: 24398
2005-11-17 18:30:17 +00:00
5aba6ae3b3
Enable global address legalization, fixing a todo and allowing the removal
...
of some code. This exposes the implicit load from the stubs to the DAG, allowing
them to be optimized by the dag combiner. It also moves darwin specific stuff
out of the isel into the legalizer, and allows more to be moved to the .td file.
llvm-svn: 24397
2005-11-17 18:26:56 +00:00
0fe88e3f32
Teach the selector to fold lo(g) into load instruction immediate fields
...
llvm-svn: 24396
2005-11-17 18:02:16 +00:00
4b11fa284d
Generate LA and ADDIS when possible.
...
llvm-svn: 24395
2005-11-17 17:52:01 +00:00
3648c20472
Use the right accessor to create this node
...
llvm-svn: 24394
2005-11-17 17:51:38 +00:00
595088aa0f
Add an initial hack at legalizing GlobalAddress into the appropriate nodes
...
on Darwin to remove smarts from the isel. This is currently disabled by
default (uncomment setOperationAction(ISD::GlobalAddress to enable it).
tblgen needs to become smarter about tglobaladdr nodes and bigger patterns
needed to be added to the .td file. However, we can currently emit stuff like
this: :)
li r2, lo16(L_x$non_lazy_ptr)
lis r3, ha16(L_x$non_lazy_ptr)
lwzx r2, r3, r2
The obvious improvements will follow.
llvm-svn: 24390
2005-11-17 07:30:41 +00:00
63ed749ce0
LI could theoretically be used for the lo-part of a global address, just like
...
lis can be used for the high part.
llvm-svn: 24388
2005-11-17 07:04:43 +00:00
b7025749e1
When lowering direct calls, lower them to use a targetglobaladress directly
...
instead of a globaladdress. This has no effect on the generated code at all.
llvm-svn: 24386
2005-11-17 05:56:14 +00:00
a171f6b20c
Patch to clean up function call pseudos and support the BLA instruction,
...
which branches to an absolute address. This is required to support objc
direct dispatch.
llvm-svn: 24370
2005-11-16 00:48:01 +00:00
63985e2892
Make sure to use SwitchSection to switch sections so that we don't accidentally emit
...
functions into the .const section. Whoops.
llvm-svn: 24363
2005-11-15 01:45:01 +00:00
1a4adc7aee
Handle globals with explicit alignment requests
...
llvm-svn: 24355
2005-11-14 19:00:30 +00:00
0aacd2ab9b
Teach the PPC asmwriter to honor globals with explicit section requests.
...
llvm-svn: 24353
2005-11-14 18:52:46 +00:00
fafff9ba1d
Make BB and CPI labels use the function number, not the function name as a
...
uniquing id. This makes things happy when the function name is quoted,
preventing labels like LBB"foo"_2.
llvm-svn: 24295
2005-11-10 21:59:25 +00:00
9eb7dfa15a
Darwin supports quoted labels. This implements:
...
test/Regression/CodeGen/PowerPC/darwin-labels.ll
llvm-svn: 24287
2005-11-10 19:33:43 +00:00
59e44ff3d3
Make the aix asm printer interface properly with the parent class
...
llvm-svn: 24274
2005-11-10 18:20:29 +00:00
88e234dd49
Add a new option to indicate we want the code generator to emit code quickly,
...
not spending tons of time microoptimizing it. This is useful for an -O0
style of build.
llvm-svn: 24235
2005-11-08 02:12:47 +00:00
3ee3e69556
Add the necessary support to the ISel to allow targets to codegen the new
...
alignment information appropriately. Includes code for PowerPC to support
fixed-size allocas with alignment larger than the stack. Support for
arbitrarily aligned dynamic allocas coming soon.
llvm-svn: 24224
2005-11-06 09:00:38 +00:00
75fe59c4ea
add a case Nate sent me
...
llvm-svn: 24195
2005-11-05 08:57:56 +00:00
802748cd61
Allow itineraries to be passed through the Target Machine.
...
llvm-svn: 24139
2005-11-01 20:06:59 +00:00
7432ceef5c
Add a flag to enable a darwin linker optimization
...
llvm-svn: 24130
2005-11-01 00:12:36 +00:00
6b63e0c6fd
Make constant pool entries use private labels. This is important when you're
...
not compiling a whole program at a time :)
llvm-svn: 24129
2005-10-31 22:12:06 +00:00
e507a15184
This is implemented
...
llvm-svn: 24107
2005-10-30 06:42:12 +00:00
00cea9b2e0
New case to handle someday
...
llvm-svn: 24075
2005-10-28 23:26:57 +00:00
7ca53a5783
Don't emit "32" for unordered comparison
...
llvm-svn: 24073
2005-10-28 22:58:07 +00:00
f8899a6877
add a hack to get code with ordered comparisons working. This hack is
...
tracked as PR642
llvm-svn: 24068
2005-10-28 20:49:47 +00:00
5d6cb604de
add support for branch on ordered/unordered.
...
llvm-svn: 24067
2005-10-28 20:32:44 +00:00
97d72c80e4
Do not globalize internal symbols
...
llvm-svn: 24064
2005-10-28 18:44:07 +00:00
a0dfc67ae6
a bad case for bitfield insert
...
llvm-svn: 24051
2005-10-28 00:20:45 +00:00
75eab3ca63
Typo made worse x 2 - take 2.
...
llvm-svn: 24018
2005-10-26 18:07:50 +00:00
f718a9e17b
Fix an assert compiling MallocBench/gs
...
llvm-svn: 24017
2005-10-26 18:01:11 +00:00
b1f2cedbaa
Typo x 2
...
llvm-svn: 24016
2005-10-26 17:50:22 +00:00
a2b5235fac
Give full control of subtarget features over to table generated code.
...
llvm-svn: 24013
2005-10-26 17:30:34 +00:00
53ad110490
Add attribute name and type to SubtargetFeatures.
...
llvm-svn: 24012
2005-10-26 17:28:23 +00:00
ff1796534f
Add a note about some bitfield stuff we could be doing better.
...
llvm-svn: 23994
2005-10-25 23:50:02 +00:00
762bf809b5
Correctly Expand or Promote FP_TO_UINT based on the capabilities of the
...
machine. This allows us to generate great code for i32 FP_TO_UINT now on
targets with 64 bit extensions.
llvm-svn: 23993
2005-10-25 23:48:36 +00:00
81ff73ec46
autogen undef
...
llvm-svn: 23991
2005-10-25 21:03:41 +00:00
b439dad538
Allow pseudos to have patterns, no functionality change
...
llvm-svn: 23988
2005-10-25 20:58:43 +00:00
261009a4df
Autogen fsel
...
llvm-svn: 23987
2005-10-25 20:55:47 +00:00
65845a2f7c
Expose the fextend on the DAG instead of doing it in the matcher
...
llvm-svn: 23986
2005-10-25 20:54:57 +00:00
cd7f101c9a
Autogen a few new ppc-specific nodes
...
llvm-svn: 23985
2005-10-25 20:41:46 +00:00
26ee5953f7
The dag isel generator generates this now
...
llvm-svn: 23984
2005-10-25 20:36:10 +00:00
c0a201c318
Be a bit more paranoid about calling SelectNodeTo
...
llvm-svn: 23982
2005-10-25 20:26:41 +00:00
e1fd05ebde
Fix a couple of minor bugs. The first fixes povray, the second fixes things
...
if the dag combiner isn't run
llvm-svn: 23981
2005-10-25 19:32:37 +00:00
db4621a5f5
Preparation of supporting scheduling info. Need to find info based on selected
...
CPU.
llvm-svn: 23974
2005-10-25 15:15:28 +00:00
d36c34822e
Simplify this, matching changes in the tblgen emitter
...
llvm-svn: 23909
2005-10-23 22:34:25 +00:00
abcce5c4b3
mark this as beta
...
llvm-svn: 23906
2005-10-23 22:23:45 +00:00
a389f0d8fa
rearrange things a bit so that instructions can use subtarget features in the
...
future.
llvm-svn: 23902
2005-10-23 22:08:13 +00:00
0d4923b975
improve -help output
...
llvm-svn: 23892
2005-10-23 05:28:51 +00:00
13a19453d2
Add g3 back to the mix and reorder to irritate them anal folk. Actually, it's
...
to group appropriately and provide cues to maintainers that the lists don't
need to be ordered.
llvm-svn: 23880
2005-10-22 08:04:24 +00:00
c5d511c4d9
64-bit reg support should not be enabled by default, as support isn't complete.
...
llvm-svn: 23878
2005-10-21 22:15:43 +00:00
e296949fbe
Instead of aborting if not a case we can handle specially, break out and
...
let the generic code handle it. This fixes CodeGen/Generic/2005-10-21-longlonggtu.ll on ppc.
also, reindent this code
llvm-svn: 23874
2005-10-21 21:17:10 +00:00
9ed9032e22
Plugin new subtarget backend into the build.
...
llvm-svn: 23870
2005-10-21 19:05:19 +00:00
fd0d55ec69
Match rotate. This does actually match the rotates in an rc5 cipher, but I
...
haven't seen it fire on our testsuite.
llvm-svn: 23863
2005-10-21 06:36:18 +00:00
4dd383120f
Invert the TargetLowering flag that controls divide by consant expansion.
...
Add a new flag to TargetLowering indicating if the target has really cheap
signed division by powers of two, make ppc use it. This will probably go
away in the future.
Implement some more ISD::SDIV folds in the dag combiner
Remove now dead code in the x86 backend.
llvm-svn: 23853
2005-10-21 00:02:42 +00:00
60bbe2d1e5
Add some more patterns for i64 on ppc
...
llvm-svn: 23842
2005-10-20 07:51:08 +00:00
c6f067a8c4
Move the target constant divide optimization up into the dag combiner, so
...
that the nodes can be folded with other nodes, and we can not duplicate
code in every backend. Alpha will probably want this too.
llvm-svn: 23835
2005-10-20 02:15:44 +00:00
74ab9960f2
Added InstrSchedClass to each of the PowerPC Instructions.
...
Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.
llvm-svn: 23830
2005-10-19 19:51:16 +00:00
9f3c26c4ea
Write patterns for the various shl and srl patterns that don't involve
...
doing something clever.
llvm-svn: 23824
2005-10-19 18:42:01 +00:00
9761100055
Push processor descriptions to the top of target and add command line info.
...
llvm-svn: 23820
2005-10-19 13:34:52 +00:00
c16b0c387f
now that tblgen is smarter, use integers directly. This should help Andrew too
...
llvm-svn: 23818
2005-10-19 04:32:04 +00:00
5f37623218
teach ppc backend these are copies
...
llvm-svn: 23813
2005-10-19 01:50:36 +00:00
5b6f4dc623
Convert these cases to patterns
...
llvm-svn: 23811
2005-10-19 01:38:02 +00:00
9eaa6bac06
Woo, it kinda works. We now generate this atrociously bad, but correct,
...
code for long long foo(long long a, long long b) { return a + b; }
_foo:
or r2, r3, r3
or r3, r4, r4
or r4, r5, r5
or r5, r6, r6
rldicr r2, r2, 32, 31
rldicl r3, r3, 0, 32
rldicr r4, r4, 32, 31
rldicl r5, r5, 0, 32
or r2, r3, r2
or r3, r5, r4
add r4, r3, r2
rldicl r2, r4, 32, 32
or r4, r4, r4
or r3, r2, r2
blr
llvm-svn: 23809
2005-10-19 01:12:32 +00:00
ecdf842311
apply some tblgen majik to simplify the X register definitions
...
llvm-svn: 23805
2005-10-19 00:17:55 +00:00
92e77502f3
Make a new reg class for 64 bit regs that aliases the 32 bit regs. This
...
will have to tide us over until we get real subreg support, but it prevents
the PrologEpilogInserter from spilling 8 byte GPRs on a G4 processor.
Add some initial support for TRUNCATE and ANY_EXTEND, but they don't
currently work due to issues with ScheduleDAG. Something wll have to be
figured out.
llvm-svn: 23803
2005-10-19 00:05:37 +00:00
78afac2ddd
Add the ability to lower return instructions to TargetLowering. This
...
allows us to lower legal return types to something else, to meet ABI
requirements (such as that i64 be returned in two i32 regs on Darwin/ppc).
llvm-svn: 23802
2005-10-18 23:23:37 +00:00
d812a2e449
Simple edits; remove unimplimented cases and clarify long haul SLU cases.
...
llvm-svn: 23788
2005-10-18 16:59:23 +00:00
5a2fb9787b
Fix the JIT encoding of LWA, LD, STD, and STDU.
...
llvm-svn: 23787
2005-10-18 16:51:22 +00:00
c6533006c8
Checking in first round of scheduling tablegen files. Not tied in as yet.
...
llvm-svn: 23786
2005-10-18 16:23:40 +00:00
53b9c3ad4c
add a case
...
llvm-svn: 23785
2005-10-18 06:30:51 +00:00
e74dfbb9ce
Do the right thing and enable 64 bit regs under the control of a subtarget
...
option. Currently the only way to enable this is to specify the
64bitregs mattr flag. It is never enabled by default on any config yet.
llvm-svn: 23779
2005-10-18 00:56:42 +00:00
0b71e007ef
First bits of 64 bit PowerPC stuff, currently disabled. A lot of this is
...
purely mechanical.
llvm-svn: 23778
2005-10-18 00:28:58 +00:00
6cca84e43c
More PPC32 -> PPC changes, as well as merging some classes that were
...
redundant after the change.
llvm-svn: 23759
2005-10-16 05:39:50 +00:00
d869bec4fe
Remove some dead code: the ORI/ORIS cases are autogen'd. This makes
...
SelectIntImmediateExpr dead.
llvm-svn: 23753
2005-10-15 22:06:18 +00:00
03354280eb
prune #includes
...
llvm-svn: 23752
2005-10-15 21:58:54 +00:00
a52969c8d6
These instructions are now autogenerated
...
llvm-svn: 23751
2005-10-15 21:44:56 +00:00
286c1d7cfa
Add a pattern for FSQRTS
...
llvm-svn: 23750
2005-10-15 21:44:15 +00:00
efa382616b
remove dead code
...
llvm-svn: 23749
2005-10-15 21:40:12 +00:00
e33870d154
remove broken SRA/rlwimi case
...
llvm-svn: 23746
2005-10-15 19:04:48 +00:00
6f3b954662
Rename PPC32*.h to PPC*.h
...
This completes the grand PPC file renaming
llvm-svn: 23745
2005-10-14 23:59:06 +00:00
0aa794ba5b
Merge PPCJITInfo.h and PPC32JITInfo.h. Note that the PowerPCJITInfo
...
and PPC32JITInfo classes should be merged.
llvm-svn: 23744
2005-10-14 23:53:41 +00:00
bfca1ab79d
Rename PowerPC*.h to PPC*.h
...
llvm-svn: 23743
2005-10-14 23:51:18 +00:00
e80bf1b33a
Rename PowerPCInstrBuilder.h -> PPC*
...
llvm-svn: 23742
2005-10-14 23:45:43 +00:00
2ed745a905
Nuke the PowerPCTargetMachine.h header. Note that the PowerPCTargetMachine
...
still should be merged into the PPC32TargetMachine class
llvm-svn: 23741
2005-10-14 23:44:05 +00:00
7503d46feb
Rename PowerPC*.td -> PPC*.td
...
llvm-svn: 23740
2005-10-14 23:40:39 +00:00
f3b97f53b9
These are dead
...
llvm-svn: 23739
2005-10-14 23:38:51 +00:00
0921e3bfc1
Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td
...
llvm-svn: 23738
2005-10-14 23:37:35 +00:00
09cd9e7661
Like the comment says...
...
llvm-svn: 23737
2005-10-14 22:48:24 +00:00
2121f3ca50
Nuke PowerPCInstrFormats.h, its contents are dead. Remove the definitions
...
from the .td file that correspond to it
llvm-svn: 23736
2005-10-14 22:44:13 +00:00
c41e1be2e8
Remove an unnecsesary file. PPC32 and PPC64 share architected registers.
...
We will decide with subtarget support whether we ever use an i64 register
class.
llvm-svn: 23734
2005-10-14 18:58:46 +00:00
7d9f719d42
These are now autogenerated
...
llvm-svn: 23731
2005-10-14 06:26:29 +00:00
9c0d3c5932
Add patterns for FP round/extend
...
llvm-svn: 23727
2005-10-14 04:55:50 +00:00
d59a57a8d5
These definitions have been moved to common code.
...
llvm-svn: 23681
2005-10-10 06:01:00 +00:00
89c7fa22b1
Disable formation of rlwinm instructions from SRA bases. This fixes
...
the 177.mesa failure from last night, and fixes the
CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll regression test I added.
If this code cannot be fixed, it should be removed for good, but I'll leave
it to Nate to decide its fate.
llvm-svn: 23670
2005-10-09 05:36:17 +00:00
967ce74980
Remove another unused file. Preparing for the great "enable i64 on ppc32"
...
merge, and using subtarget info for ptr size.
llvm-svn: 23668
2005-10-08 01:32:34 +00:00
af72457fc4
Remove a file that is no longer used
...
llvm-svn: 23666
2005-10-08 01:21:27 +00:00
dae96f8881
When preselecting, favor things that have low depth to select first. This
...
is faster and uses less stack space. This reduces our stack requirement
enough to compile sixtrack, and though it's a hack, should be enough until
we switch to iterative isel
llvm-svn: 23664
2005-10-07 22:10:27 +00:00
e373592258
Fix a CQ regression from my patch to split F32/F64 into seperate register
...
classes on PPC. We were emitting fmr instructions to do fp extensions, which
weren't getting coallesced. This fixes Regression/CodeGen/PowerPC/fpcopy.ll
llvm-svn: 23654
2005-10-07 05:00:52 +00:00
318622fb9f
Pull out Call, reducing stack frame size from 6032 bytes to 5184 bytes.
...
llvm-svn: 23650
2005-10-06 19:07:45 +00:00
491b8294f4
Pull out setcc, this reduces stack frame size from 7520 to 6032 bytes
...
llvm-svn: 23649
2005-10-06 19:03:35 +00:00
502a36935e
Pull two more methods out, reducing stack frame size from 8224 -> 7520 bytes
...
llvm-svn: 23648
2005-10-06 18:56:10 +00:00
259e6c76f2
Add a recursive-iterative hybrid stage to attempt to reduce stack space, this
...
helps but not enough.
Start pulling cases out of PPC32DAGToDAGISel::Select. With GCC 4, this function
required 8512 bytes of stack space for each invocation (GCC 3 required less
than 700 bytes). Pulling this first function out gets us down to 8224. More
to come :(
llvm-svn: 23647
2005-10-06 18:45:51 +00:00
afef68baff
Speed up the asm printer a lot by not printing formatted LLVM asm output
...
for globals
llvm-svn: 23608
2005-10-03 07:08:36 +00:00
68303a78ff
add patterns for float binops and fma ops
...
llvm-svn: 23592
2005-10-02 07:46:28 +00:00
3734d204b8
another solution to the fsel issue. Instead of having 4 variants, just force
...
the comparison to be 64-bits. This is fine because extensions from float
to double are free.
llvm-svn: 23589
2005-10-02 07:07:49 +00:00
9e98672962
fsel can take a different FP type for the comparison and for the result. As such
...
split the FSEL family into 4 things instead of just two.
llvm-svn: 23588
2005-10-02 06:58:23 +00:00
a17e6c486c
fix an f32/f64 type mismatch
...
llvm-svn: 23587
2005-10-02 06:37:13 +00:00
5ab9d42bb4
Minor tweak to the branch selector. When emitting a two-way branch, and if
...
we're in a single-mbb loop, make sure to emit the backwards branch as the
conditional branch instead of the uncond branch. For example, emit this:
LBBl29_z__44:
stw r9, 0(r15)
stw r9, 4(r15)
stw r9, 8(r15)
stw r9, 12(r15)
addi r15, r15, 16
addi r8, r8, 1
cmpw cr0, r8, r28
ble cr0, LBBl29_z__44
b LBBl29_z__48 *** NOT PART OF LOOP
Instead of:
LBBl29_z__44:
stw r9, 0(r15)
stw r9, 4(r15)
stw r9, 8(r15)
stw r9, 12(r15)
addi r15, r15, 16
addi r8, r8, 1
cmpw cr0, r8, r28
bgt cr0, LBBl29_z__48 *** PART OF LOOP!
b LBBl29_z__44
The former sequence has one fewer dispatch group for the loop body.
llvm-svn: 23582
2005-10-01 23:06:26 +00:00
6f4dc51d6f
like the comment says, enable this
...
llvm-svn: 23581
2005-10-01 23:02:40 +00:00
8713ebf37c
fix typo
...
llvm-svn: 23578
2005-10-01 02:51:36 +00:00
d3eee1a09b
Modify the ppc backend to use two register classes for FP: F8RC and F4RC.
...
These are used to represent float and double values, and the two regclasses
contain the same physical registers.
llvm-svn: 23577
2005-10-01 01:35:02 +00:00
f61232354f
Should be using flag and not chain.
...
llvm-svn: 23572
2005-09-30 23:43:37 +00:00
fbfad0b565
Remove some now-dead code.
...
llvm-svn: 23571
2005-09-30 21:28:27 +00:00
88025e17c5
constant fold these calls
...
llvm-svn: 23558
2005-09-30 17:16:59 +00:00
f6d4173f75
pass extra args
...
llvm-svn: 23539
2005-09-30 01:31:52 +00:00
64ca7cda3f
these methods get extra args
...
llvm-svn: 23538
2005-09-30 01:30:55 +00:00
08f157c5b2
Use the 32-bit version for now
...
llvm-svn: 23534
2005-09-30 00:05:05 +00:00
027a2671ef
Add a bunch of patterns for F64 FP ops, add some more integer ops
...
llvm-svn: 23533
2005-09-29 23:34:24 +00:00
1de5706e68
Remove code for patterns that are autogenerated
...
llvm-svn: 23532
2005-09-29 23:33:31 +00:00
0a1cd715d4
tblgen autogens this pattern now
...
llvm-svn: 23530
2005-09-29 22:37:24 +00:00
bae1f9d790
copy and paste error
...
llvm-svn: 23528
2005-09-29 21:11:57 +00:00
a748e3ae5b
now that tblgen is smarter, this pattern is not needed. Also, tblgen
...
now inverts commuted versions of ANDC/ORC with the current .td file.
llvm-svn: 23527
2005-09-29 19:29:15 +00:00
02d3ba3db8
consistency with other cases, no functionality change
...
llvm-svn: 23524
2005-09-29 17:38:52 +00:00
eca4f56646
Make the JIT default to the DAG isel instead of the pattern isel, like LLC.
...
The Pattern isel has some strange memory corruption issues going on. :(
This should have been converted over anyway, but it got forgotten somehow
when switching to the dag isel.
llvm-svn: 23523
2005-09-29 17:31:03 +00:00
08c319fbdd
Never rely on ReplaceAllUsesWith when selecting, use CodeGenMap instead.
...
ReplaceAllUsesWith does not replace scalars SDOperand floating around on
the stack, permitting things to be selected multiple times.
llvm-svn: 23515
2005-09-29 00:59:32 +00:00
d4e9e8b7ec
Codegen ADD X, IMM -> addis/addi if needed.
...
This implements PowerPC/fold-li.ll
llvm-svn: 23514
2005-09-28 23:07:13 +00:00
b9b2e77295
Autogen MUL, move FP cases together
...
llvm-svn: 23512
2005-09-28 22:53:16 +00:00
5769311c92
disentangle FP from INT versions of div/mul
...
llvm-svn: 23511
2005-09-28 22:50:24 +00:00
585131baaf
Use the autogenerated matcher for ADD/SUB
...
llvm-svn: 23510
2005-09-28 22:47:28 +00:00
f023b2cda2
add a patter for SUBFIC
...
llvm-svn: 23509
2005-09-28 22:47:06 +00:00
21551ea5ab
Mark int binops as int-only, add FP binops. Mark FADD/FMUL as commutative but
...
not associative. Add [SU]REM.
llvm-svn: 23508
2005-09-28 22:38:27 +00:00
d3ea19b51a
Add FP versions of the binary operators, keeping the int and fp worlds seperate.
...
llvm-svn: 23506
2005-09-28 22:29:58 +00:00
7fe6734dff
Mark associative nodes as associative
...
llvm-svn: 23503
2005-09-28 20:58:39 +00:00
b97b054ba7
Nate pointed out that mulh[us] are commutative as well. Thanks!
...
llvm-svn: 23500
2005-09-28 19:01:44 +00:00
89d168ceb3
expose commutativity information
...
llvm-svn: 23498
2005-09-28 18:27:58 +00:00
fab48b3285
All (xor *) cases are autogenerated now
...
llvm-svn: 23497
2005-09-28 18:12:37 +00:00
037d69a404
add support for missed eqv tests
...
llvm-svn: 23496
2005-09-28 18:10:51 +00:00
33f8e08c8f
Implement PowerPC/eqv-andc-orc-nor.ll:EQV3
...
llvm-svn: 23494
2005-09-28 18:04:52 +00:00
8cd7b88a88
learn to codegen not as NOR instead of xoris/xori
...
llvm-svn: 23490
2005-09-28 17:13:15 +00:00
bb5939a436
These nodes are all autogenerated
...
llvm-svn: 23489
2005-09-28 17:07:09 +00:00
a028e7a39c
Darwin, like many BSD systems, has a setjmp/longjmp which saves the signal mask
...
on setjmp calls and restores it on longjmp calls (both of which require syscalls).
This makes the calls REALLY slow. Use _setjmp/_longjmp instead. This speeds up
hexxagon from 120.31s to 15.68s: from 5.53x slower than GCC to 28% faster than GCC.
llvm-svn: 23482
2005-09-27 22:18:25 +00:00
c628f00845
Make sure to clear the CodeGenMap after each basic block is selected to avoid
...
cross MBB pollution.
llvm-svn: 23470
2005-09-27 17:45:33 +00:00
54ec5f2089
Move the post-lsr simplify cfg pass after lowereh, so it can clean up after
...
eh lowering as well.
llvm-svn: 23459
2005-09-27 00:14:41 +00:00
4435b149a0
minor pattern shuffling
...
llvm-svn: 23458
2005-09-26 22:20:16 +00:00
6736a6cdd2
Teach the dag isel generator how to construct arbitrary immediates. The
...
generated isel now tries li then lis, then lis+ori.
llvm-svn: 23418
2005-09-24 00:41:58 +00:00
4d9cf68023
Implement hook for ppc
...
llvm-svn: 23374
2005-09-17 01:03:26 +00:00
0ebec06671
disable this for now
...
llvm-svn: 23366
2005-09-15 21:44:00 +00:00
2e84be22a8
give all operands names
...
llvm-svn: 23356
2005-09-14 21:10:24 +00:00
f006d15e7f
Fix some issues exposed by more testing. XORIS had the wrong operands
...
specified. The various *imm operands defined by PPC are really all i32,
even though the actual immediate is restricted to a smaller value in it.
llvm-svn: 23352
2005-09-14 20:53:05 +00:00
6b013fc923
Fix some bugs noticed by new checking code
...
llvm-svn: 23350
2005-09-14 18:18:39 +00:00
b011cb2746
we don't need this proto any longer
...
llvm-svn: 23342
2005-09-13 22:05:21 +00:00
03e08eefc7
move the #include for the generated code into the isel class body so we
...
can use/define class methods
llvm-svn: 23339
2005-09-13 22:03:06 +00:00
0f965a615e
Change the arg lowering code to use copyfromreg from vregs associated
...
with incoming arguments instead of the pregs themselves. This fixes
the scheduler from causing problems by moving a copyfromreg for an argument
to after a select_cc node (now it can, and bad things won't happen).
llvm-svn: 23334
2005-09-13 19:33:40 +00:00
aa6cbd90c5
Remove some dead vectors
...
llvm-svn: 23329
2005-09-13 18:47:49 +00:00
4309c3a785
PowerPC cannot truncstore i1 natively
...
llvm-svn: 23304
2005-09-10 00:21:06 +00:00
0f2146bb5d
I forgot that we always spill fp values as 64-bits. Implement spill folding
...
for FP as well. This triggers a couple dozen times on 177.mesa (for example).
llvm-svn: 23299
2005-09-09 21:59:44 +00:00
712e78ee28
Fix a problem that Nate noticed, where spill code was not getting coallesced
...
with copies, leading to code like this:
lwz r4, 380(r1)
or r10, r4, r4 ;; Last use of r4
By teaching the PPC backend how to fold spills into copies, we now get this
code:
lwz r10, 380(r1)
wow. :)
This reduces a testcase nate sent me from 1505 instructions to 1484.
Note that this could handle FP values but doesn't currently, for reasons
mentioned in the patch
llvm-svn: 23298
2005-09-09 21:46:49 +00:00
f540c1a2e8
code cleanup
...
llvm-svn: 23297
2005-09-09 20:51:08 +00:00
c37a2f13c4
Teach the code generator that rlwimi is commutable if the rotate amount
...
is zero. This lets the register allocator elide some copies in some cases.
This implements CodeGen/PowerPC/rlwimi-commute.ll
llvm-svn: 23292
2005-09-09 18:17:41 +00:00
39b4d83f6a
Introduce two new concepts:
...
1. Add support for defining Pattern's, which can match expressions when there
is no instruction that directly implements something. Instructions usually
implicitly define patterns.
2. Add support for defining SDNodeXForm's, which are node transformations.
This seperates the concept of a node xform out from the existing predicate
support.
Using this new stuff, we add a few instruction patterns, one for testing, and
two for OR/XOR by an arbitrary immediate.
llvm-svn: 23286
2005-09-09 00:39:56 +00:00
4b09f3c6f5
whitespace/comment changes, no functionality diffs
...
llvm-svn: 23283
2005-09-08 23:17:26 +00:00
0ec8fa0880
Add a bunch of stuff needed for node type inference. Move 'BLR' down with
...
the rest of the instructions, add comment markers to seperate portions of
the file into logical parts
llvm-svn: 23277
2005-09-08 19:50:41 +00:00
76cb006e2c
add patterns for x?oris?
...
llvm-svn: 23268
2005-09-08 17:40:49 +00:00
2d8032b54c
add patterns to the addi/addis/mulli etc instructions. Define predicates
...
for matching signed 16-bit and shifted 16-bit ppc immediates
llvm-svn: 23267
2005-09-08 17:33:10 +00:00
cf9b0e6673
Add patterns for some new instructions, allowing the use of the ineg fragment.
...
llvm-svn: 23266
2005-09-08 17:01:54 +00:00
498915dafa
Remove some cases handled by the generated portion of the isel
...
llvm-svn: 23262
2005-09-07 23:45:15 +00:00
5ea0ee7b19
On non-apple systems, when using -march=ppc32, do not print:
...
'' is not a recognized processor for this target (ignoring processor)
Default to "generic" instead of "" for the default CPU.
llvm-svn: 23257
2005-09-07 05:45:33 +00:00
6095214bf0
Implement i64<->fp using the fctidz/fcfid instructions on PowerPC when we
...
are allowed to generate 64-bit-only PowerPC instructions for 32 bit hosts,
such as the PowerPC 970.
This speeds up 189.lucas from 81.99 to 32.64 seconds.
llvm-svn: 23250
2005-09-06 22:03:27 +00:00
e9e2c6d314
Add note about future optimization noted in the ppc compiler writer's guide
...
llvm-svn: 23245
2005-09-06 15:30:48 +00:00
2dded8302a
Add accessor for 64bit flag, so that we can tell when it is safe to
...
generate the fun in-register fp<->long instructions.
llvm-svn: 23244
2005-09-06 15:30:12 +00:00
aa833d4571
explicitly specify an operands list for patterns with inputs (e.g. neg)
...
llvm-svn: 23240
2005-09-03 01:28:40 +00:00
8ae9525bd0
include the dag isel fragment
...
llvm-svn: 23239
2005-09-03 01:17:22 +00:00
0442dcfabc
ask for a dag isel
...
llvm-svn: 23238
2005-09-03 01:15:41 +00:00
5f12cf14be
Change the isel to not break out of the big giant switch. Instead, the
...
switch should never be exited, so its bottom is now unreachable.
llvm-svn: 23234
2005-09-03 00:53:47 +00:00
9220f92c41
rearrange logical ops to group them together more consistently.
...
Define the PatFrag class which can be used to define subpatterns to match
things with. Define 'not', and use it to define the patterns for andc,
nand, etc.
llvm-svn: 23233
2005-09-03 00:21:51 +00:00
dcbb561b76
Add AND/OR/XOR
...
llvm-svn: 23232
2005-09-02 22:35:53 +00:00
3a1002d529
Add some initial patterns to simple binary instructions, though they
...
currently don't do anything. This elides patterns for binary operators
that ping on the carry flag, since we don't model it yet.
This patch also removes PPC::SUB, because it is dead.
llvm-svn: 23230
2005-09-02 21:18:00 +00:00
06e237f253
turn on dag isel by default
...
llvm-svn: 23226
2005-09-02 19:53:54 +00:00
27d628dfc9
Add help support for -mcpu and -mattr.
...
llvm-svn: 23222
2005-09-02 19:27:43 +00:00
aa3b1fcc58
Decouple fsqrt from gpul optimizations, implementing fsqrt.ll.
...
Remove the -enable-gpopt option which is subsumed by feature flags.
llvm-svn: 23218
2005-09-02 18:33:05 +00:00
763a3a0fa7
Restore this patch now that the latent bug has been fixed
...
llvm-svn: 23209
2005-09-02 01:24:55 +00:00
06d440f2ee
Revert the previous patch which causes a mysterious regression in toast.
...
llvm-svn: 23207
2005-09-02 00:47:05 +00:00
9ee867b93b
Implement small-arguments.ll:test3 by teaching the DAG optimizer that
...
the results of calls to functions returning small values are properly
sign/zero extended.
llvm-svn: 23198
2005-09-01 23:44:32 +00:00
68d15fdfea
Align functions to 16-byte boundaries, to eliminate noise in performance measurements. This improves the performance of 'treeadd' by about 20% with the dag
...
isel, restoring it to the pattern-isel level (which happens to get the alignment right).
llvm-svn: 23194
2005-09-01 23:08:50 +00:00
e40a3ccd60
Local labels on darwin apparently start with just 'L', not .L like other
...
platforms. This reduces executable size and makes shark realize the actual
bounds of functions instead of showing each MBB as a function :)
llvm-svn: 23193
2005-09-01 21:48:35 +00:00
19058c3989
1. Use SubtargetFeatures in llc/lli.
...
2. Propagate feature "string" to all targets.
3. Implement use of SubtargetFeatures in PowerPCTargetSubtarget.
llvm-svn: 23192
2005-09-01 21:38:21 +00:00
a305d28cf6
Implement dynamic allocas correctly. In particular, because we were copying
...
directly out of R1 (without using a CopyFromReg, which uses a chain), multiple
allocas were getting CSE'd together, producing bogus code. For this:
int %foo(bool %X, int %A, int %B) {
br bool %X, label %T, label %F
F:
%G = alloca int
%H = alloca int
store int %A, int* %G
store int %B, int* %H
%R = load int* %G
ret int %R
T:
ret int 0
}
We were generating:
_foo:
stwu r1, -16(r1)
stw r31, 4(r1)
or r31, r1, r1
stw r1, 12(r31)
cmpwi cr0, r3, 0
bne cr0, .LBB_foo_2 ; T
.LBB_foo_1: ; F
li r2, 16
subf r2, r2, r1 ;; One alloca
or r1, r2, r2
or r3, r1, r1
or r1, r2, r2
or r2, r1, r1
stw r4, 0(r3)
stw r5, 0(r2)
lwz r3, 0(r3)
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
.LBB_foo_2: ; T
li r3, 0
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
Now we generate:
_foo:
stwu r1, -16(r1)
stw r31, 4(r1)
or r31, r1, r1
stw r1, 12(r31)
cmpwi cr0, r3, 0
bne cr0, .LBB_foo_2 ; T
.LBB_foo_1: ; F
or r2, r1, r1
li r3, 16
subf r2, r3, r2 ;; Alloca 1
or r1, r2, r2
or r2, r1, r1
or r6, r1, r1
subf r3, r3, r6 ;; Alloca 2
or r1, r3, r3
or r3, r1, r1
stw r4, 0(r2)
stw r5, 0(r3)
lwz r3, 0(r2)
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
.LBB_foo_2: ; T
li r3, 0
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
This fixes Povray and SPASS with the dag isel, the last two failing cases.
Tommorow we will hopefully turn it on by default! :)
llvm-svn: 23190
2005-09-01 21:31:30 +00:00
293b3a68e0
Fix a bug where we were useing HA to get the high part, which seems like it
...
could cause a miscompile. Fixing this didn't fix the two programs that fail
though. :(
This also changes the implementation to follow the pattern selector more
closely, causing us to select 0 to li instead of lis.
llvm-svn: 23189
2005-09-01 19:38:28 +00:00
34182aff7f
Do not select the operands being passed into SelectCC. IT does this itself
...
and selecting early prevents folding immediates into the cmpw* instructions
llvm-svn: 23188
2005-09-01 19:20:44 +00:00
da2e04c69d
Move FCTIWZ handling out of the instruction selectors and into legalization,
...
getting them out of the business of making stack slots.
llvm-svn: 23180
2005-08-31 21:09:52 +00:00
6bad1fb19e
Remove dead code
...
llvm-svn: 23179
2005-08-31 20:25:15 +00:00
e675a08e10
Move SHL,SHR i64 -> legalizer
...
llvm-svn: 23178
2005-08-31 20:23:54 +00:00
3a04a4b767
Remove code that is now dead from the pattern isel.
...
llvm-svn: 23177
2005-08-31 19:11:36 +00:00
2f03896a0f
lower sra_parts on the dag, implementing it for the dag isel, and exposing
...
the ops to dag optimization.
llvm-svn: 23176
2005-08-31 19:09:57 +00:00
2bd2af8ecd
add assert zext/sext to the dag isel
...
llvm-svn: 23171
2005-08-31 18:08:46 +00:00
46ff6aa993
Handle AssertSext/AssertZext nodes, fixing the regressions last night.
...
llvm-svn: 23170
2005-08-31 17:48:04 +00:00
e3287b85b7
Enable generation of AssertSext and AssertZext in the PPC backend.
...
llvm-svn: 23168
2005-08-31 01:58:39 +00:00
f4d594370b
Fix 'ret long' to return the high and lo parts in the right registers. This
...
fixes crafty and probably others.
llvm-svn: 23167
2005-08-31 01:34:29 +00:00
69e9a9a94c
now that physregs can exist in the same dag with multiple types, remove some
...
ugly hacks
llvm-svn: 23162
2005-08-30 22:59:48 +00:00
8f8d539746
Fix type mismatches when passing f32 values to calls
...
llvm-svn: 23159
2005-08-30 21:28:19 +00:00
9f23ae226f
Fix some indentation (first hunks).
...
Remove code (last hunk) that miscompiled immediate and's, such as
and uint %tmp.30, 4294958079
into
andi. r8, r8, 56319
andis. r8, r8, 65535
instead of:
li r9, -9217
and r8, r8, r9
The first always generates zero.
This fixes espresso.
llvm-svn: 23155
2005-08-30 18:37:48 +00:00
6a41fd75cd
Fix a problem Nate found where we swapped the operands of SHL/SHR_PARTS. This
...
fixes fourinarow
llvm-svn: 23153
2005-08-30 17:42:59 +00:00
bdf3d3defb
codegen ADD_PARTS correctly: put the results in the right registers! This
...
fixes fhourstones
llvm-svn: 23152
2005-08-30 17:40:13 +00:00
45706e9fb8
add operands in the right order, fixing McCat/18-imp with the dag isel
...
llvm-svn: 23150
2005-08-30 17:13:58 +00:00
7a59b1cf90
Make sure the selector emits register register copies with flag operands
...
linking them to calls when appropriate, this prevents the scheduler from
pulling these copies away from the call.
This fixes Ptrdist/yacr2
llvm-svn: 23143
2005-08-30 01:57:02 +00:00
e413b60632
The first operand to AND does not always have more than two operands. This
...
fixes MediaBench/toast with the dag selector
llvm-svn: 23141
2005-08-30 00:59:16 +00:00
e75b5e63a7
Fix a bug in my patch for legalizing to fsel. It cannot handle seteq/setne,
...
which I failed to include when I moved the code over. This fixes
MallocBench/gs.
llvm-svn: 23140
2005-08-30 00:45:18 +00:00
61f7c3e843
emit FMR instructions to convert f64<->f32 instructions, so things like
...
STOREs, know the right type to store.
llvm-svn: 23139
2005-08-30 00:30:43 +00:00
62b9a5d1f8
Fix some really strange indentation that xcode likes to use.
...
no xcode, this is not right:
if (!foo) break;
X;
llvm-svn: 23138
2005-08-30 00:19:00 +00:00
12357281b8
fix a crash in cfrac
...
llvm-svn: 23137
2005-08-29 23:49:25 +00:00
1cbbe1015a
Implement DYNAMIC_STACKALLOC, wrap some long lines
...
llvm-svn: 23136
2005-08-29 23:30:11 +00:00
b2b418509b
Fix a dumb bug of mine where we were mishandling the PPC ABI (undef handling).
...
This fixes voronoi and bh in Olden, allowing all of olden to pass!
llvm-svn: 23133
2005-08-29 22:22:57 +00:00
c429ab2fb1
Fix a bug the last patch exposed in treeadd among others
...
llvm-svn: 23127
2005-08-29 01:07:02 +00:00
d4d683a47b
A hack to fix a problem folding immedaites. This fixes Olden/power.
...
llvm-svn: 23126
2005-08-29 01:01:01 +00:00
3ccad3fb8c
Fix order of operands for copytoreg node when emitting calls. This fixes
...
Olden/msFix order of operands for copytoreg node when emitting calls. This fixes
Olden/mstt.
llvm-svn: 23125
2005-08-29 00:26:57 +00:00
66ddc8d3bf
add operands in the correct order
...
llvm-svn: 23123
2005-08-29 00:02:01 +00:00
dfcde88d07
Fix a bug in FP_EXTEND, implement FP_TO_SINT
...
llvm-svn: 23121
2005-08-28 23:59:09 +00:00
38660c6666
fix an assertion failure in treeadd
...
llvm-svn: 23120
2005-08-28 23:39:22 +00:00
787e962795
The condition register being branched on may not be cr0, as such, print it.
...
This fixes: UnitTests/2005-07-17-INT-To-FP.c
llvm-svn: 23112
2005-08-26 23:42:05 +00:00
29bfaa7ef0
Propagate cr# from COND_BRANCH to the actual branch instruction as appropriate
...
llvm-svn: 23111
2005-08-26 23:41:27 +00:00
422e23dd02
allow code using mtcrf to assemble
...
llvm-svn: 23107
2005-08-26 22:05:54 +00:00
72f23815bc
Remove operand type 'crbit', since it is no longer used
...
llvm-svn: 23106
2005-08-26 22:04:17 +00:00
c3d1bdd0a9
teach getClass what a condition reg is
...
llvm-svn: 23105
2005-08-26 21:51:29 +00:00
97345405a6
Minor cleanups:
...
* avoid calling getClass() multiple times (it is relatively expensive)
* Allow -disable-fp-elim to turn of frame pointer elimination.
llvm-svn: 23104
2005-08-26 21:49:18 +00:00
9b577f108a
implement SELECT_CC fully for the DAG->DAG isel!
...
llvm-svn: 23101
2005-08-26 21:23:58 +00:00
b2854fadda
Make fsel emission work with both the pattern and dag-dag selectors, by
...
giving it a non-instruction opcode. The dag->dag selector used to not
select the operands of the fsel, because it thought that whole tree was
already selected.
llvm-svn: 23091
2005-08-26 20:25:03 +00:00
bec817ce6f
implement the fold for:
...
bool %test(int %X, int %Y) {
%C = setne int %X, 0
ret bool %C
}
to:
_test:
addic r2, r3, -1
subfe r3, r2, r3
blr
llvm-svn: 23089
2005-08-26 18:46:49 +00:00
a9e6a82d66
Changes to adjust to new ReplaceAllUsesWith syntax. Change FP_EXTEND to
...
just return its input, instead of emitting an explicit copy.
llvm-svn: 23088
2005-08-26 18:37:23 +00:00
76eea9a480
Remove some code made dead by the fsel patch
...
llvm-svn: 23085
2005-08-26 17:45:06 +00:00
c75e047245
now that fsel is formed during legalization, this code is dead
...
llvm-svn: 23084
2005-08-26 17:40:39 +00:00
7f1fa8eaef
implement the other half of the select_cc -> fsel lowering, which handles
...
when the RHS of the comparison is 0.0. Turn this on by default.
llvm-svn: 23083
2005-08-26 17:36:52 +00:00
c30405e0ee
Change ConstantPoolSDNode to actually hold the Constant itself instead of
...
putting it into the constant pool. This allows the isel machinery to
create constants that it will end up deciding are not needed, without them
ending up in the resultant function constant pool.
llvm-svn: 23081
2005-08-26 17:15:30 +00:00
7bbdae53d6
Fix some warnings in an optimized build
...
llvm-svn: 23080
2005-08-26 16:38:51 +00:00
2091a36631
Fix a huge annoyance: SelectNodeTo took types before the opcode unlike
...
every other SD API. Fix it to take the opcode before the types.
llvm-svn: 23079
2005-08-26 16:36:26 +00:00
7b809f593b
Fix JIT encoding of conditional branches
...
llvm-svn: 23076
2005-08-26 04:11:42 +00:00
f3d06c6417
add initial support for converting select_cc -> fsel in the legalizer
...
instead of in the backend. This currently handles fsel cases with registers,
but doesn't have the 0.0 and -0.0 optimization enabled yet.
Once this is finished, special hack for fp immediates can go away.
llvm-svn: 23075
2005-08-26 00:52:45 +00:00
89093ca62a
SUBFIC produces two results, not one.
...
llvm-svn: 23073
2005-08-26 00:34:06 +00:00
bed4f2b982
Implement SHL_PARTS and SRL_PARTS
...
llvm-svn: 23072
2005-08-26 00:28:00 +00:00
b81431b012
Emit the lo/hi parts in the right order :)
...
llvm-svn: 23068
2005-08-25 23:36:49 +00:00
02884fe41c
implement support for 64-bit add/sub, fix a broken assertion for 64-bit
...
return. Allow the udiv breaker-upper to work with any non-zero constant
operand.
llvm-svn: 23066
2005-08-25 23:21:06 +00:00
abbd8ea048
simplify the add/sub_parts code
...
llvm-svn: 23065
2005-08-25 23:19:58 +00:00
6e184f2b3d
Finish implementing SDIV/UDIV by copying over the majik constant code from
...
ISelPattern
llvm-svn: 23062
2005-08-25 22:04:30 +00:00
717f97a5c8
Simplify some code. It's not clear why the UDIV expanded sequence
...
doesn't work for large uint constants, but we'll keep the current behavior
llvm-svn: 23061
2005-08-25 22:03:50 +00:00
b746dd1cf6
Implement setcc correctly for G5 and non-G5 systems
...
llvm-svn: 23060
2005-08-25 21:39:42 +00:00
3dcd75bc54
implement setcc on the G5. We're still missing the non-g5 specific bits, but
...
they will come later.
llvm-svn: 23059
2005-08-25 20:08:18 +00:00
65ffd8fbf4
Remove option to make SetCC illegal on PowerPC after long discussion with
...
Chris. This will be accomplished through correctly modeling CR's and
subregs.
llvm-svn: 23056
2005-08-25 20:01:10 +00:00
dc66457022
Add support for sdiv by 2^k and -2^k. Producing code like:
...
_test:
srawi r2, r3, 2
addze r3, r2
blr
llvm-svn: 23052
2005-08-25 17:50:06 +00:00
4bd2aab6c1
fit in 80 cols
...
llvm-svn: 23051
2005-08-25 17:49:31 +00:00
25db699671
Implement support for taking the address of constant pool indices, which
...
is used by the int -> FP code among other things. This gets
2005-05-12-Int64ToFP past that failure, to dying on lack of support for add_parts
llvm-svn: 23042
2005-08-25 05:04:11 +00:00
666512c832
Add support for FP constants, fixing UnitTests/2004-02-02-NegativeZero
...
llvm-svn: 23038
2005-08-25 04:47:18 +00:00
e4c338d0d8
Fully implement frame index, so that we can pass the address of alloca's
...
around to functions and stuff
llvm-svn: 23036
2005-08-25 00:45:43 +00:00
66a6a13225
implement unconditional branches, fixing UnitTests/2003-05-02-DependentPHI.c
...
llvm-svn: 23034
2005-08-25 00:29:58 +00:00
4ae278a760
LFS/STFS load and store FP values, not integer ones. This change allows us
...
to codegen this: float foo() { return 1.245; }
into this:
_foo:
lis r2, ha16(.CPI_foo_0)
lfs f1, lo16(.CPI_foo_0)(r2)
blr
instead of this:
_foo:
lis r2, ha16(.CPI_foo_0)
lfs r2, lo16(.CPI_foo_0)(r2) <-- ouch
or f1, r2, r2 <-- ouch
blr
with the dag isel.
llvm-svn: 23033
2005-08-25 00:26:22 +00:00
794eb6684d
Fix a broken assertion
...
llvm-svn: 23032
2005-08-25 00:19:12 +00:00
a3fbdae515
Split IMPLICIT_DEF into IMPLICIT_DEF_GPR and IMPLICIT_DEF_FP, so that the
...
instructions take a consistent reg class. Implement ISD::UNDEF in the dag->dag
selector to generate this, fixing UnitTests/2003-07-06-IntOverflow.
llvm-svn: 23028
2005-08-24 23:08:16 +00:00
d83cd354bd
implement support for calls
...
llvm-svn: 23026
2005-08-24 22:45:17 +00:00
1fc2a7f006
Remove some dead cases.
...
Emit the indcall sequence as:
mtctr inreg
mr R12, inreg
btctr
If inreg and R12 aren't coallesced, this reduces the odds of having the mtctr
and btctr in the same dispatch group. :)
llvm-svn: 23023
2005-08-24 22:21:47 +00:00
1e98a330f2
add an idea
...
llvm-svn: 23020
2005-08-24 18:15:24 +00:00
7c1ba938be
Whoops, fix a thinko. All cases except SETNE are now handled by the
...
target independent code in SelectionDAG.cpp
llvm-svn: 23002
2005-08-24 05:06:48 +00:00
a1e0a2f72b
Remove unused statistic
...
Prefer 'neg X' to 'subfic 0, X' since neg does not set XER[CA]
llvm-svn: 23001
2005-08-24 05:03:20 +00:00
6948b79b26
Add the "ppc specific" setcc-equivalent select_cc cases
...
Prefer 'neg X' to 'subfic 0, X' since it does not set XER[CA]
llvm-svn: 23000
2005-08-24 04:59:21 +00:00
b6d034a841
Add callseq_begin/end support
...
Call stil not supported yet
llvm-svn: 22998
2005-08-24 00:47:15 +00:00
5e3953d761
add a note
...
llvm-svn: 22982
2005-08-23 06:27:59 +00:00
f3ce09b36e
Ack, typo
...
llvm-svn: 22981
2005-08-23 05:45:10 +00:00
7216ad415b
Add an option to make SetCC illegal as a beta option
...
llvm-svn: 22979
2005-08-23 05:42:36 +00:00
06436b2b7d
Remove some instructions we no longer generate
...
llvm-svn: 22976
2005-08-23 01:16:46 +00:00
46323cf0e2
Remove some regs that are not used.
...
llvm-svn: 22975
2005-08-22 22:32:13 +00:00
956820d989
Nate noticed that 30% of the malloc/frees in llc come from calls to LowercaseString
...
in the asmprinter. This changes the .td files to use lower case register names,
avoiding the need to do this call. This speeds up the asmprinter from 1.52s
to 1.06s on kc++ in a release build.
llvm-svn: 22974
2005-08-22 22:00:02 +00:00
ca0c0d7550
Implement stores.
...
llvm-svn: 22963
2005-08-22 01:27:59 +00:00
1d634b2f44
Fix compilation of:
...
float %test2(float* %P) {
%Q = load float* %P
%R = add float %Q, %Q
ret float %R
}
By returning the right result.
llvm-svn: 22961
2005-08-22 00:59:14 +00:00
b676e5a666
Make sure expressions only have one use before emitting them into a place that is conditionally executed
...
llvm-svn: 22960
2005-08-22 00:47:28 +00:00
c5292ec9de
Implement most of load support. There is still a bug though.
...
llvm-svn: 22959
2005-08-21 22:31:09 +00:00
968aeb18b0
Don't print out the MBB label for the entry mbb
...
llvm-svn: 22953
2005-08-21 19:09:33 +00:00
519acbfb76
Simplify the logic for BRTWOWAY_CC handling. The isel code already
...
simplifies BRTWOWAY into BR if one of the results is a fall-through.
Unless I'm missing something, there is no reason to duplicate this
in the target-specific code.
llvm-svn: 22952
2005-08-21 19:03:28 +00:00
2a1823d178
Implement selection for branches.
...
llvm-svn: 22951
2005-08-21 18:50:37 +00:00
Chris Lattner