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151 Commits

Author SHA1 Message Date
Dale Johannesen a2b3c175db Fix for PR 1505 (and 1489). Rewrite X87 register 
model to include f32 variants.  Some factoring
improvments forthcoming.

llvm-svn: 37847
 2007-07-03 00:53:03 +00:00
Dan Gohman 309d3d51b3 Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from 
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.

llvm-svn: 37704
 2007-06-22 14:59:07 +00:00
Chris Lattner a5fcd24746 Fix CodeGen/X86/2007-03-24-InlineAsmPModifier.ll 
llvm-svn: 35926
 2007-04-11 22:29:46 +00:00
Anton Korobeynikov 0ad22563b8 Oops :) 
llvm-svn: 35438
 2007-03-28 18:38:33 +00:00
Anton Korobeynikov 7522c9d8e1 Don't allow MatchAddress recurse too much. This trims exponential 
behaviour in some cases.

llvm-svn: 35437
 2007-03-28 18:36:33 +00:00
Chris Lattner 3e1d917e80 Two changes: 
1) codegen a shift of a register as a shift, not an LEA.
2) teach the RA to convert a shift to an LEA instruction if it wants something
   in three-address form.

This gives us asm diffs like:

-       leal (,%eax,4), %eax
+       shll $2, %eax

which is faster on some processors and smaller on all of them.

and, more interestingly:

-       movl 24(%esi), %eax
-       leal (,%eax,4), %edi
+       movl 24(%esi), %edi
+       shll $2, %edi

Without #2, #1 was a significant pessimization in some cases.

This implements CodeGen/X86/shift-codegen.ll

llvm-svn: 35204
 2007-03-20 06:08:29 +00:00
Chris Lattner fe8c530d79 Fix a miscompilation in the addr mode code trying to implement X | C and 
X + C to promote LEA formation.  We would incorrectly apply it in some cases
(test) and miss it in others.

This fixes CodeGen/X86/2007-02-04-OrAddrMode.ll

llvm-svn: 33884
 2007-02-04 20:18:17 +00:00
Evan Cheng 1281dc32ef Linux GOT indirect reference is only necessary in PIC mode. 
llvm-svn: 33441
 2007-01-22 21:34:25 +00:00
Reid Spencer 015b432b54 Adjust #includes to compensate for lost of DerivedTypes.h in 
TargetLowering.h

llvm-svn: 33154
 2007-01-12 23:22:14 +00:00
Anton Korobeynikov a0554d90e8 * PIC codegen for X86/Linux has been implemented 
* PIC-aware internal structures in X86 Codegen have been refactored
* Visibility (default/weak) has been added
* Docs fixes (external weak linkage, visibility, formatting)

llvm-svn: 33136
 2007-01-12 19:20:47 +00:00
Anton Korobeynikov 4efbbc963f Really big cleanup. 
- New target type "mingw" was introduced
- Same things for both mingw & cygwin are marked as "cygming" (as in
gcc)
- .lcomm is supported here, so allow LLVM to use it
- Correctly use underscored versions of setjmp & _longjmp for both mingw
& cygwin

llvm-svn: 32833
 2007-01-03 11:43:14 +00:00
Chris Lattner 1ef9cd400d eliminate static ctors for Statistic objects. 
llvm-svn: 32703
 2006-12-19 22:59:26 +00:00
Evan Cheng 582ac4bed7 Fix for PR1062 by Dan Gohman. 
llvm-svn: 32688
 2006-12-19 21:31:42 +00:00
Bill Wendling 9bfb1e1f29 What should be the last unnecessary <iostream>s in the library. 
llvm-svn: 32333
 2006-12-07 22:21:48 +00:00
Chris Lattner 700b873130 Detemplatize the Statistic class. The only type it is instantiated with 
is 'unsigned'.

llvm-svn: 32279
 2006-12-06 17:46:33 +00:00
Evan Cheng 47e181cc4d Revert an unintended change. 
llvm-svn: 32239
 2006-12-05 22:03:40 +00:00
Evan Cheng dd60ca029c - Switch X86-64 JIT to large code size model. 
- Re-enable some codegen niceties for X86-64 static relocation model codegen.
- Clean ups, etc.

llvm-svn: 32238
 2006-12-05 19:50:18 +00:00
Evan Cheng 62cdc3f011 - Fix X86-64 JIT by temporarily disabling code that treats GV address as 32-bit 
immediate in small code model. The JIT cannot ensure GV's are placed in the
lower 4G.
- Some preliminary support for large code model.

llvm-svn: 32215
 2006-12-05 04:01:03 +00:00
Evan Cheng ae1cd75af7 - Use a different wrapper node for RIP-relative GV, etc. 
- Proper support for both small static and PIC modes under X86-64
- Some (non-optimal) support for medium modes.

llvm-svn: 32046
 2006-11-30 21:55:46 +00:00
Evan Cheng 8c84c7cd0d Clean up. 
llvm-svn: 32027
 2006-11-29 23:46:27 +00:00
Evan Cheng 0b1692216d Fix for PR1018 - Better support for X86-64 Linux in small code model. 
llvm-svn: 32026
 2006-11-29 23:19:46 +00:00
Evan Cheng 20350c4025 Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead 
of opcode and number of operands.

llvm-svn: 31947
 2006-11-27 23:37:22 +00:00
Evan Cheng 9e8093ae20 For unsigned 8-bit division. Use movzbw to set the lower 8 bits of AX while 
clearing the upper 8-bits instead of issuing two instructions. This also
eliminates the need to target the AH register which can be problematic on
x86-64.

llvm-svn: 31832
 2006-11-17 22:10:14 +00:00
Bill Wendling c8e81b8d48 Removed even more std::cerr and #include <iostream> things. 
llvm-svn: 31813
 2006-11-17 07:52:03 +00:00
Evan Cheng dbd3d294e6 Matches MachineInstr changes. 
llvm-svn: 31712
 2006-11-13 23:36:35 +00:00
Evan Cheng db04c958a5 Add implicit use / def operands to created MI's. 
llvm-svn: 31676
 2006-11-11 10:21:44 +00:00
Evan Cheng a36cdcfaf8 Add all implicit defs to FP_REG_KILL mi. 
llvm-svn: 31674
 2006-11-11 07:19:36 +00:00
Evan Cheng fb44822a98 Fix a bug in SelectScalarSSELoad. Since the load is wrapped in a 
SCALAR_TO_VECTOR, even if the hasOneUse() check pass we may end up folding
the load into two instructions. Make sure we check the SCALAR_TO_VECTOR
has only one use as well.

llvm-svn: 31641
 2006-11-10 21:23:04 +00:00
Evan Cheng 6cd0909da7 Match tblegen changes. 
llvm-svn: 31571
 2006-11-08 20:34:28 +00:00
Jeff Cohen 7d6f3db3e2 Unbreak VC++ build. 
llvm-svn: 31464
 2006-11-05 19:31:28 +00:00
Chris Lattner de2f0906e4 silence warning 
llvm-svn: 31393
 2006-11-03 01:13:15 +00:00
Evan Cheng ff1a712794 SelectScalarSSELoad should call CanBeFoldedBy as well. 
llvm-svn: 30973
 2006-10-16 06:34:55 +00:00
Evan Cheng b86375cfd0 Corrected load folding check. We need to start from the root of the sub-dag 
being matched and ensure there isn't a non-direct path to the load (i.e. a
path that goes out of the sub-dag.)

llvm-svn: 30958
 2006-10-14 08:33:25 +00:00
Evan Cheng ab51cf2e78 Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode. 
llvm-svn: 30945
 2006-10-13 21:14:26 +00:00
Evan Cheng a7956d2894 Doh. This wasn't causing problems by luck. 
llvm-svn: 30914
 2006-10-12 19:13:59 +00:00
Chris Lattner 40ec2bebf9 fix compilation failure of smg2000 
llvm-svn: 30900
 2006-10-12 03:55:48 +00:00
Chris Lattner d5fcfaa6da Fold "zero extending vector loads" now that evan added the chain manip stuff. 
This compiles both tests in X86/vec_ss_load_fold.ll into:

_test1:
        movss 4(%esp), %xmm0
        subss LCPI1_0, %xmm0
        mulss LCPI1_1, %xmm0
        minss LCPI1_2, %xmm0
        xorps %xmm1, %xmm1
        maxss %xmm1, %xmm0
        cvttss2si %xmm0, %eax
        andl $65535, %eax
        ret

instead of:

_test1:
        movss LCPI1_0, %xmm0
        movss 4(%esp), %xmm1
        subss %xmm0, %xmm1
        movss LCPI1_1, %xmm0
        mulss %xmm0, %xmm1
        movss LCPI1_2, %xmm0
        minss %xmm0, %xmm1
        xorps %xmm0, %xmm0
        maxss %xmm0, %xmm1
        cvttss2si %xmm1, %eax
        andl $65535, %eax
        ret

llvm-svn: 30894
 2006-10-11 22:09:58 +00:00
Evan Cheng 4090dc4703 ComplexPatterns sse_load_f32 and sse_load_f64 returns in / out chain operands. 
llvm-svn: 30892
 2006-10-11 21:06:01 +00:00
Evan Cheng 61b8b43bbe More isel time load folding checking for nodes that produce flag values. 
See comment in CanBeFoldedBy() for detailed explanation.

llvm-svn: 30851
 2006-10-10 01:46:56 +00:00
Evan Cheng e71fe34d75 Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes. 
llvm-svn: 30844
 2006-10-09 20:57:25 +00:00
Chris Lattner 398195ebbe completely disable folding of loads into scalar sse instructions and provide 
a framework for doing it right.  This fixes
CodeGen/X86/2006-10-07-ScalarSSEMiscompile.ll.

Once X86DAGToDAGISel::SelectScalarSSELoad is implemented right, this task
will be done.

llvm-svn: 30817
 2006-10-07 21:55:32 +00:00
Evan Cheng 1212b4d249 Not needed. 
llvm-svn: 30674
 2006-09-29 22:05:10 +00:00
Anton Korobeynikov 6f7072c66a Added some eye-candy for Subtarget type checking 
Added X86 StdCall & FastCall calling conventions. Codegen will follow.

llvm-svn: 30446
 2006-09-17 20:25:45 +00:00
Evan Cheng f8464da015 Remove a unnecessary check. 
llvm-svn: 30382
 2006-09-14 23:55:02 +00:00
Chris Lattner 706dd3e0d4 Fix a regression in the 32-bit port from the 64-bit port landing. 
We now compile CodeGen/X86/lea-2.ll into:

_test:
        movl 4(%esp), %eax
        movl 8(%esp), %ecx
        leal -5(%ecx,%eax,4), %eax
        ret

instead of:

_test:
        movl 4(%esp), %eax
        leal (,%eax,4), %eax
        addl 8(%esp), %eax
        addl $4294967291, %eax
        ret

llvm-svn: 30288
 2006-09-13 04:45:25 +00:00
Evan Cheng 9a083a4121 Reflects MachineConstantPoolEntry changes. 
llvm-svn: 30279
 2006-09-12 21:04:05 +00:00
Evan Cheng 11b0a5dbd4 Committing X86-64 support. 
llvm-svn: 30177
 2006-09-08 06:48:29 +00:00
Evan Cheng 2c4e0f120f Oops. Bad typo. Without the check of N1.hasOneUse() bad things can happen. 
Suppose the TokenFactor can reach the Op:

       [Load chain]
           ^
           |
         [Load]
         ^    ^
         |    |
        /      \-
       /         |
      /          [Op]
     /          ^ ^
     |        ..  |
     |       /    |
   [TokenFactor]  |
       ^          |
       |          |
        \        /
         \      /
         [Store]

If we move the Load below the TokenFactor, we would have created a cycle in
the DAG.

llvm-svn: 30040
 2006-09-01 22:52:28 +00:00
Evan Cheng b28800f4d5 Remove dead code. 
llvm-svn: 29962
 2006-08-29 21:42:58 +00:00
Evan Cheng dfb85155dc Don't performance load/op/store transformation if op produces a floating point 
or vector result. X86 does not have load/mod/store variants of those
instructions.

llvm-svn: 29957
 2006-08-29 18:37:37 +00:00