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421 Commits

Author SHA1 Message Date
Dan Gohman 57111e7a60 Define non-intrinsic instructions for vector min, max, sqrt, rsqrt, and rcp, 
in addition to the intrinsic forms. Add spill-folding entries for these new
instructions, and for the scalar min and max instrinsic instructions which
were missing. And add some preliminary ISelLowering code for using the new
non-intrinsic vector sqrt instruction, and fneg and fabs.

llvm-svn: 38478
 2007-07-10 00:05:58 +00:00
Anton Korobeynikov de9c825859 Proper flag __alloca call 
llvm-svn: 37923
 2007-07-05 20:36:08 +00:00
Dale Johannesen 3d7008cd49 Refactor X87 instructions. As a side effect, all 
their names are changed.

llvm-svn: 37876
 2007-07-04 21:07:47 +00:00
Dale Johannesen a2b3c175db Fix for PR 1505 (and 1489). Rewrite X87 register 
model to include f32 variants.  Some factoring
improvments forthcoming.

llvm-svn: 37847
 2007-07-03 00:53:03 +00:00
Evan Cheng 444d3ca53d No vector fneg. 
llvm-svn: 37786
 2007-06-29 00:18:15 +00:00
Evan Cheng 3bd318e298 Type of vector extract / insert index operand should be iPTR. 
llvm-svn: 37784
 2007-06-29 00:01:20 +00:00
Dan Gohman a866514528 Generalize MVT::ValueType and associated functions to be able to represent 
extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.

This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.

llvm-svn: 37719
 2007-06-25 16:23:39 +00:00
Dan Gohman 309d3d51b3 Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from 
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.

llvm-svn: 37704
 2007-06-22 14:59:07 +00:00
Chris Lattner 944200be45 If a function is vararg, never pass inreg arguments in registers. Thanks to 
Anton for half of this patch.

llvm-svn: 37641
 2007-06-19 00:13:10 +00:00
Evan Cheng cea02ffd05 Look for VECTOR_SHUFFLE that's identity operation on either LHS or RHS. This can happen before DAGCombiner catches it. 
llvm-svn: 37636
 2007-06-19 00:02:56 +00:00
Bill Wendling 094a4e813a Revert patch. It regresses: 
define double @test2(i64 %A) {
   %B = bitcast i64 %A to double
   ret double %B
}

$ llvm-as < t.ll | llc -march=x86-64

before:

         .align  4
         .globl  _test2
_test2:
         movd %rdi, %xmm0
         ret

after:

_test2:
         subq $8, %rsp
         movq %rdi, (%rsp)
         movsd (%rsp), %xmm0
         addq $8, %rsp
         ret

llvm-svn: 37617
 2007-06-16 23:57:15 +00:00
Bill Wendling cd9673e565 Fix a failure to bit_convert from integer GPR to MMX register. 
llvm-svn: 37611
 2007-06-16 06:17:31 +00:00
Dan Gohman 5c4413120f Rename MVT::getVectorBaseType to MVT::getVectorElementType. 
llvm-svn: 37579
 2007-06-14 22:58:02 +00:00
Chris Lattner 75372ad603 fix x86-64 mmx calling convention for real, which passes in integer gprs. 
llvm-svn: 37534
 2007-06-09 05:08:10 +00:00
Chris Lattner a4a49e37ab fix mmx handling bug 
llvm-svn: 37533
 2007-06-09 05:01:50 +00:00
Dan Gohman 703e0f8608 Add explicit qualification for namespace MVT members. 
llvm-svn: 37320
 2007-05-24 14:33:05 +00:00
Dan Gohman eefa83e67b Use MVT::FIRST_VECTOR_VALUETYPE and MVT::LAST_VECTOR_VALUETYPE. 
llvm-svn: 37234
 2007-05-18 18:44:07 +00:00
Evan Cheng afa1cb6da3 Fix a bogus check that prevented folding VECTOR_SHUFFLE to UNDEF; add an optimization to fold VECTOR_SHUFFLE to a zero vector. 
llvm-svn: 37173
 2007-05-17 18:45:50 +00:00
Chris Lattner dade607f19 This is the correct fix for PR1427. This fixes mmx-shuffle.ll and doesn't 
cause other regressions.

llvm-svn: 37160
 2007-05-17 17:13:13 +00:00
Anton Korobeynikov 1ad4618715 Revert patch for PR1427. It breaks almost all vector tests. 
llvm-svn: 37159
 2007-05-17 07:50:14 +00:00
Chris Lattner 6a5a46322f Fix PR1427 and test/CodeGen/X86/mmx-shuffle.ll 
llvm-svn: 37141
 2007-05-17 03:29:42 +00:00
Chris Lattner c8798d085c fix subtle bugs in inline asm operand selection 
llvm-svn: 37065
 2007-05-15 01:28:08 +00:00
Chris Lattner 83df45a959 Fix two classes of bugs: 
1. x86 backend rejected (&gv+c) for the 'i' constraint when in static mode.
  2. the matcher didn't correctly reject and accept some global addresses.
     the right predicate is GVRequiresExtraLoad, not "relomodel = pic".

llvm-svn: 36670
 2007-05-03 16:52:29 +00:00
Anton Korobeynikov f1dcf69fc3 Emit correct register move information in eh frames for X86. This allows Shootout-C++/except to pass on x86/linux 
with non-llvm-compiled (e.g. "native") unwind runtime.

llvm-svn: 36647
 2007-05-02 19:53:33 +00:00
Bill Wendling 591eab8844 Support for the special case of a vector with the canonical form: 
vector_shuffle v1, v2, <2, 6, 3, 7>

I.e.

         vector_shuffle v, undef, <2, 2, 3, 3>

MMX only has a shuffle for v4i16 vectors. It needs to use the unpackh for
this type of operation.

llvm-svn: 36403
 2007-04-24 21:16:55 +00:00
Lauro Ramos Venancio efb8077ddd X86 TLS: fix and optimize the implementation of "initial exec" model. 
llvm-svn: 36355
 2007-04-22 22:50:52 +00:00
Lauro Ramos Venancio 4e91908f17 X86 TLS: Implement review feedback. 
llvm-svn: 36318
 2007-04-21 20:56:26 +00:00
Lauro Ramos Venancio 2518889872 Implement "general dynamic", "initial exec" and "local exec" TLS models for 
X86 32 bits.

llvm-svn: 36283
 2007-04-20 21:38:10 +00:00
Anton Korobeynikov 9b91d98a30 Add comment 
llvm-svn: 36213
 2007-04-17 19:34:00 +00:00
Chris Lattner ff0598de75 rename X86FunctionInfo to X86MachineFunctionInfo to match the header file 
it is defined in.

llvm-svn: 36196
 2007-04-17 17:21:52 +00:00
Anton Korobeynikov 8b7aab009e Implemented correct stack probing on mingw/cygwin for dynamic alloca's. 
Also, fixed static case in presence of eax livin. This fixes PR331

PS: Why don't we still have push/pop instructions? :)
llvm-svn: 36195
 2007-04-17 09:20:00 +00:00
Anton Korobeynikov fb80151c42 Removed tabs everywhere except autogenerated & external files. Add make 
target for tabs checking.

llvm-svn: 36146
 2007-04-16 18:10:23 +00:00
Chris Lattner 2805bce656 Fix mmx paddq, add support for the 'y' register class, though it isn't tested. 
llvm-svn: 35940
 2007-04-12 04:14:49 +00:00
Chris Lattner 808ac93f68 remove some dead hooks 
llvm-svn: 35845
 2007-04-09 23:31:19 +00:00
Chris Lattner 39f65335d5 remove some dead target hooks, subsumed by isLegalAddressingMode 
llvm-svn: 35840
 2007-04-09 22:27:04 +00:00
Chris Lattner 7451e4d6a1 move a bunch of register constraints from being handled by 
getRegClassForInlineAsmConstraint to being handled by
getRegForInlineAsmConstraint.  This allows us to let the llvm register allocator
allocate, which gives us better code.  For example, X86/2007-01-29-InlineAsm-ir.ll
used to compile to:

_run_init_process:
        subl $4, %esp
        movl %ebx, (%esp)
        xorl %ebx, %ebx
        movl $11, %eax
        movl %ebx, %ecx
        movl %ebx, %edx
        # InlineAsm Start
        push %ebx ; movl %ebx,%ebx ; int $0x80 ; pop %ebx
        # InlineAsm End

Now we get:
_run_init_process:
        xorl %ecx, %ecx
        movl $11, %eax
        movl %ecx, %edx
        # InlineAsm Start
        push %ebx ; movl %ecx,%ebx ; int $0x80 ; pop %ebx
        # InlineAsm End

llvm-svn: 35804
 2007-04-09 05:49:22 +00:00
Chris Lattner 2b6b4eb471 implement support for CodeGen/X86/inline-asm-x-scalar.ll:test3 - i32/i64 values 
used with x constraints.

llvm-svn: 35803
 2007-04-09 05:31:48 +00:00
Chris Lattner 590ed5e5b7 implement CodeGen/X86/inline-asm-x-scalar.ll 
llvm-svn: 35799
 2007-04-09 05:11:28 +00:00
Chris Lattner 1eb94d973a implement the new addressing mode description hook. 
llvm-svn: 35521
 2007-03-30 23:15:24 +00:00
Bill Wendling 2338e21b2b Remove cruft I put in there... 
llvm-svn: 35394
 2007-03-28 01:02:54 +00:00
Bill Wendling ad2db4a4cf Unbreak mmx arithmetic. It was barfing trying to do v8i8 arithmetic. 
llvm-svn: 35392
 2007-03-28 00:57:11 +00:00
Bill Wendling 6dff51ae65 Fix so that pandn is emitted instead of an xor/and combo. Add integer 
comparison operators.

llvm-svn: 35385
 2007-03-27 20:22:40 +00:00
Bill Wendling 158f6092a2 Promote to v1i64 type... 
llvm-svn: 35353
 2007-03-26 08:03:33 +00:00
Bill Wendling 98d2104c6f Add support for the v1i64 type. This makes better code for this: 
#include <mmintrin.h>

extern __m64 C;

void baz(__v2si *A, __v2si *B)
{
  *A = C;
  _mm_empty();
}

We get this:

_baz:
        call "L1$pb"
"L1$pb":
        popl %eax
        movl L_C$non_lazy_ptr-"L1$pb"(%eax), %eax
        movq (%eax), %mm0
        movl 4(%esp), %eax
        movq %mm0, (%eax)
        emms
        ret

GCC gives us this:

_baz:
        pushl   %ebx
        call    L3
"L00000000001$pb":
L3:
        popl    %ebx
        subl    $8, %esp
        movl    L_C$non_lazy_ptr-"L00000000001$pb"(%ebx), %eax
        movl    (%eax), %edx
        movl    4(%eax), %ecx
        movl    16(%esp), %eax
        movl    %edx, (%eax)
        movl    %ecx, 4(%eax)
        emms
        addl    $8, %esp
        popl    %ebx
        ret

llvm-svn: 35351
 2007-03-26 07:53:08 +00:00
Chris Lattner d685514e2e switch TargetLowering::getConstraintType to take the entire constraint, 
not just the first letter.  No functionality change.

llvm-svn: 35322
 2007-03-25 02:14:49 +00:00
Chris Lattner 03a643aa69 enforce the proper range for the i386 N constraint. 
llvm-svn: 35319
 2007-03-25 01:57:35 +00:00
Bill Wendling d551a18783 Support added for shifts and unpacking MMX instructions. 
llvm-svn: 35266
 2007-03-22 18:42:45 +00:00
Dale Johannesen 0c6bb5eab7 repair x86 performance, dejagnu problems from previous change 
llvm-svn: 35245
 2007-03-21 21:51:52 +00:00
Chris Lattner f01f87bc63 fix a warning 
llvm-svn: 35152
 2007-03-19 00:39:32 +00:00
Devang Patel b38c2ec89c Support 'I' inline asm constraint. 
llvm-svn: 35129
 2007-03-17 00:13:28 +00:00