e50b17e97e
Fix a couple of typo's.
...
llvm-svn: 32585
2006-12-14 19:46:06 +00:00
ac1fa442a7
This is done.
...
llvm-svn: 32584
2006-12-14 19:45:32 +00:00
0fd32e9ade
Added MOVSS2DIrr and MOVDI2SSrr to foldMemeoryOperand().
...
llvm-svn: 32583
2006-12-14 19:44:45 +00:00
fccea9b2a9
- Rename MOVDSS2DIrr to MOVSS2DIrr for consistency sake.
...
- Add MOVDI2SSrm and MOVSS2DImr to fold load / store for i32 <-> f32 bit_convert
patterns.
llvm-svn: 32582
2006-12-14 19:43:11 +00:00
3b7544e24c
avoid using a constant table when a constant can be used inline
...
llvm-svn: 32580
2006-12-14 18:58:37 +00:00
09e2921d9a
Avoid creating invalid sub/add instructions on the prolog/epilog
...
patch by Lauro
llvm-svn: 32577
2006-12-14 13:31:27 +00:00
9ffa6a60ed
Add note.
...
llvm-svn: 32561
2006-12-13 20:59:43 +00:00
59e7a777da
Honor cpu directive, take two.
...
llvm-svn: 32492
2006-12-12 20:57:08 +00:00
8171e58bd9
Rollback changes to take a different tack.
...
llvm-svn: 32488
2006-12-12 19:26:50 +00:00
67d1c8ae0e
more general matching of the MVN instruction
...
llvm-svn: 32484
2006-12-12 17:10:13 +00:00
7c3cab9ddc
Honor the command line specification for machine type.
...
llvm-svn: 32483
2006-12-12 16:07:33 +00:00
470d61d82c
don't use "ordinary" addressing mode 1 when mvn is appropriate
...
llvm-svn: 32482
2006-12-12 14:03:29 +00:00
095e6f3044
Reduce number of instructions to load 64-bit constants.
...
llvm-svn: 32481
2006-12-12 13:23:43 +00:00
b341b0861d
Change inferred getCast into specific getCast. Passes all tests.
...
llvm-svn: 32469
2006-12-12 05:05:00 +00:00
9fa0a26808
use MVN to handle small negative constants
...
llvm-svn: 32459
2006-12-12 01:03:11 +00:00
1bbe581d0f
add mvn
...
llvm-svn: 32454
2006-12-12 00:37:38 +00:00
2075374e28
Fix the BitCastUnion type for 32-bit targets.
...
llvm-svn: 32453
2006-12-12 00:11:08 +00:00
eb3e8d75df
add note
...
llvm-svn: 32452
2006-12-11 23:56:10 +00:00
f4646a7e54
Another step forward in PPC64 JIT support: we now no-longer need stubs
...
emitted for external globals in PPC64-JIT-PIC mode (which is good because
we didn't handle them before!).
This also fixes a bug handling the picbase delta, which we would get wrong
in some cases.
llvm-svn: 32451
2006-12-11 23:22:45 +00:00
b1f3157638
getInstrItineraryData shouldn't copy the itineraries
...
llvm-svn: 32448
2006-12-11 21:42:55 +00:00
b943555716
Implement correct bitcast of int<->float and long<->double by using a
...
union to perform the bitcast.
llvm-svn: 32444
2006-12-11 20:39:15 +00:00
2b136a73bd
Missing opcode.
...
llvm-svn: 32439
2006-12-11 18:45:56 +00:00
e95909a4ef
Layout proper frame for ppc64.
...
llvm-svn: 32436
2006-12-11 18:10:54 +00:00
e8da58b3f9
Properly mangles symbol table names
...
Supports constant pools
Supports relocations to jump tables
Supports relocations within the data segment (global = address of global)
Allocates memory in a non-hacky for all non-code objects.
llvm-svn: 32430
2006-12-11 02:20:45 +00:00
a11aa92e6b
Update note, with the SROA change, we now produce:
...
_pairtest:
movl 8(%esp), %eax
movl 4(%esp), %ecx
movd %eax, %xmm0
movd %ecx, %xmm1
addss %xmm0, %xmm1
movl 12(%esp), %eax
movss %xmm1, (%eax)
ret
instead of:
_pairtest:
subl $12, %esp
movl 20(%esp), %eax
movl %eax, 4(%esp)
movl 16(%esp), %eax
movl %eax, (%esp)
movss (%esp), %xmm0
addss 4(%esp), %xmm0
movl 24(%esp), %eax
movss %xmm0, (%eax)
addl $12, %esp
ret
llvm-svn: 32427
2006-12-11 01:20:25 +00:00
6727f2a5f9
this is done
...
llvm-svn: 32424
2006-12-11 01:01:03 +00:00
feeb9c7be5
Evan implemented the machineinstr improvements.
...
The rot example works if the type is cast to ubyte.
Move sroa examples together and upgrade them to HEAD syntax.
llvm-svn: 32423
2006-12-11 00:44:03 +00:00
3b7c257cae
Cleaned setjmp/longjmp lowering interfaces. Now we're producing right
...
code (both asm & cbe) for Mingw32 target.
Removed autoconf checks for underscored versions of setjmp/longjmp.
llvm-svn: 32415
2006-12-10 23:12:42 +00:00
6af2220815
Reverting until finding the cause of secondary bugs.
...
llvm-svn: 32413
2006-12-10 13:09:42 +00:00
04c832d4ab
__PPC64CompilationCallback code was allowing registers to be clobbered by stub.
...
llvm-svn: 32412
2006-12-10 12:13:31 +00:00
b8ada08b26
.align is in bits
...
.comm is in bytes
:-(
llvm-svn: 32408
2006-12-10 02:53:14 +00:00
b313efb0cd
fix test/Regression/CodeGen/X86/weak.ll
...
if a variable has no initialization, I->getInitializer() will fail
llvm-svn: 32407
2006-12-09 23:14:08 +00:00
e107a8b872
Added option -soft-float to generate SW fp library calls instead of fp instructions.
...
llvm-svn: 32393
2006-12-09 02:41:30 +00:00
d12d2250a7
%progbits not @progbits
...
llvm-svn: 32376
2006-12-08 22:06:02 +00:00
94f29f129d
add \"aw\",@progbits" to ctors and dtors
...
llvm-svn: 32373
2006-12-08 21:24:58 +00:00
78cb08d082
Move findTiedToSrcOperand to TargetInstrDescriptor.
...
llvm-svn: 32366
2006-12-08 18:45:48 +00:00
87f4382163
fix truncstorei1
...
llvm-svn: 32364
2006-12-08 18:41:21 +00:00
dcb3c978c4
Packed Structures
...
llvm-svn: 32361
2006-12-08 18:06:16 +00:00
b5f1c22e94
Use MI's TargetInstrDescriptor.
...
llvm-svn: 32352
2006-12-08 07:57:56 +00:00
5040f58ae4
Fix a bug introduced by the streams patch. DEBUG code was made unconditional.
...
llvm-svn: 32351
2006-12-08 05:41:26 +00:00
09fecf9a47
this is an initial patch to switch the ppc64 jit over to working in PIC mode,
...
which allows the code to be above the 2G marker. We still need to JIT emit
dyld stubs to support external, weak, common, etc globals, but that will
happen tomorrow.
llvm-svn: 32348
2006-12-08 04:54:03 +00:00
4d475f6e6e
add a note
...
llvm-svn: 32347
2006-12-08 02:01:32 +00:00
085cfdbfdc
Simplify a bit
...
llvm-svn: 32343
2006-12-07 23:55:55 +00:00
13535c2d93
fix incorrect encoding of rldicr, used by ppc64 function stubs, etc.
...
llvm-svn: 32341
2006-12-07 23:44:07 +00:00
30c0f3367c
Don't use <sstream> in Streams.h but <iosfwd> instead.
...
llvm-svn: 32340
2006-12-07 23:41:45 +00:00
265fa68bd8
fix alignment
...
llvm-svn: 32337
2006-12-07 22:38:06 +00:00
9bfb1e1f29
What should be the last unnecessary <iostream>s in the library.
...
llvm-svn: 32333
2006-12-07 22:21:48 +00:00
a9a817dc7d
fix CodeGen/PowerPC/2006-12-07-LargeAlloca.ll on ppc64
...
llvm-svn: 32331
2006-12-07 22:15:58 +00:00
219a796475
make sure that we don't use a common symbol if a section was specified
...
llvm-svn: 32310
2006-12-07 18:33:58 +00:00
76a61eb054
Be sure to grab weak functions too, and make implicit defs comments
...
llvm-svn: 32308
2006-12-07 17:39:14 +00:00
d8e7451dc3
Fix i64 uint_to_fp on ppc64
...
llvm-svn: 32297
2006-12-07 01:24:16 +00:00
e312c152d2
MI keeps a ptr of TargetInstrDescriptor, use it.
...
llvm-svn: 32296
2006-12-07 01:21:59 +00:00
43c0eb839c
implement sextinreg i8->i64 and i16->i64
...
llvm-svn: 32293
2006-12-06 21:46:13 +00:00
9472eb83c3
fix another sradi encoding bug. This fixes Olden/health with the ppc64 jit.
...
llvm-svn: 32291
2006-12-06 21:35:10 +00:00
b8cf1ff83c
Always pass "true" to isMaxValue(bool) because we know the type is LongTy.
...
llvm-svn: 32290
2006-12-06 21:27:07 +00:00
de09dea742
Adjust to new ConstantIntegral interface for Max/Min tests.
...
llvm-svn: 32289
2006-12-06 20:45:15 +00:00
aeadac88ea
fix the jit encoding of sradi, simplify the MDForm1 description.
...
llvm-svn: 32285
2006-12-06 20:02:54 +00:00
1fa392dbfa
add relocation support for ppc64 branches.
...
llvm-svn: 32284
2006-12-06 19:40:04 +00:00
7c779fcad4
add #include
...
llvm-svn: 32281
2006-12-06 18:19:53 +00:00
f06bb658a8
add missing #include
...
llvm-svn: 32280
2006-12-06 18:14:47 +00:00
700b873130
Detemplatize the Statistic class. The only type it is instantiated with
...
is 'unsigned'.
llvm-svn: 32279
2006-12-06 17:46:33 +00:00
527c12f8e6
Make it easier for gdb to find the return address.
...
llvm-svn: 32277
2006-12-06 17:42:06 +00:00
776abee608
print weak references
...
llvm-svn: 32276
2006-12-06 13:35:10 +00:00
81cf22d873
These asm printers shouldn't use assembly/writer.h
...
llvm-svn: 32262
2006-12-06 06:13:25 +00:00
47e181cc4d
Revert an unintended change.
...
llvm-svn: 32239
2006-12-05 22:03:40 +00:00
dd60ca029c
- Switch X86-64 JIT to large code size model.
...
- Re-enable some codegen niceties for X86-64 static relocation model codegen.
- Clean ups, etc.
llvm-svn: 32238
2006-12-05 19:50:18 +00:00
c20b7e878a
If we have ScalarSSE, we can select bitconvert into single instructions.
...
This compiles bitcast.ll:test3/test4 into:
_test3:
movd %xmm0, %eax
ret
_test4:
movd %edi, %xmm0
ret
llvm-svn: 32230
2006-12-05 18:45:06 +00:00
57a41985e3
Add a perf optzn corresponding to PR1033.
...
llvm-svn: 32229
2006-12-05 18:25:10 +00:00
55c17f9177
Fix PR1033 and CodeGen/X86/bitcast.ll, by expanding bitcast to a load/store pair.
...
This could be better, readme entry pending.
llvm-svn: 32228
2006-12-05 18:22:22 +00:00
b5dee63958
expand memmove and memcpy
...
llvm-svn: 32226
2006-12-05 17:57:23 +00:00
96fd6447c7
add support for the "r" asm constraint
...
patch by Lauro Ramos Venancio
llvm-svn: 32224
2006-12-05 17:37:31 +00:00
a16201c672
Fix typo noticed by Lauro Ramos Venancio, thanks!
...
llvm-svn: 32223
2006-12-05 17:29:40 +00:00
2369a024d7
add support for weak linkage
...
llvm-svn: 32222
2006-12-05 17:00:17 +00:00
3b235aa5dc
JIT large code model support.
...
llvm-svn: 32220
2006-12-05 07:29:55 +00:00
8e0e9fbe7b
Asm printing bug.
...
llvm-svn: 32218
2006-12-05 06:43:58 +00:00
62cdc3f011
- Fix X86-64 JIT by temporarily disabling code that treats GV address as 32-bit
...
immediate in small code model. The JIT cannot ensure GV's are placed in the
lower 4G.
- Some preliminary support for large code model.
llvm-svn: 32215
2006-12-05 04:01:03 +00:00
830f224bf5
Update
...
llvm-svn: 32214
2006-12-05 03:58:23 +00:00
d139ddd2e6
Add support for 64-bit 'r' constraint. Patch by by Rafael ~Avila de EspÃndol!
...
This fixes PR1029 and Regression/CodeGen/X86/x86-64-asm.ll
llvm-svn: 32206
2006-12-04 22:38:21 +00:00
e4f4d048dd
Restoration of the stack pointer after a deallocation of a alloca was not
...
updating the SP link.
llvm-svn: 32202
2006-12-04 22:04:42 +00:00
0c2a74a487
Non-darwin gcc should default to static relocation to match gcc.
...
llvm-svn: 32184
2006-12-04 18:07:10 +00:00
67fc141db5
Match TargetInstrInfo changes.
...
llvm-svn: 32098
2006-12-01 21:52:58 +00:00
07fc107e90
convertToThreeAddress() is now responsible for updating live info as well as inserting the new MI's.
...
llvm-svn: 32097
2006-12-01 21:52:41 +00:00
022030a425
Add weak reference directive.
...
llvm-svn: 32091
2006-12-01 20:47:11 +00:00
b689d32b20
Copy and paste error. An initialized global cannot be a weak reference.
...
llvm-svn: 32075
2006-12-01 17:39:22 +00:00
1b0bc794e6
1. In ppc64 mode we need only use one GPR.
...
2. Float values need to be promoted to double when they are vararg.
llvm-svn: 32074
2006-12-01 16:30:47 +00:00
311622f912
ExternalWeak case in wrong location.
...
llvm-svn: 32073
2006-12-01 14:37:39 +00:00
845bd6e096
Fix 2005-05-08-FPStackifierPHI.ll failure.
...
llvm-svn: 32071
2006-12-01 10:11:51 +00:00
5fb2c76d59
A initialized global variable cannot be extern weak. However, if a global value's initializer is itself a external weak symbol, emit the weak reference.
...
llvm-svn: 32069
2006-12-01 09:13:26 +00:00
fa54c0b6fb
Darwin PPC external weak linkage support.
...
llvm-svn: 32068
2006-12-01 07:56:37 +00:00
5b020349f2
Minor code clean up.
...
llvm-svn: 32067
2006-12-01 07:38:23 +00:00
db66456285
Fix indentation.
...
llvm-svn: 32066
2006-12-01 07:17:00 +00:00
6476a3b4ba
Darwin X86 external weak linkage support.
...
llvm-svn: 32065
2006-12-01 07:15:24 +00:00
09ed0ff2ac
Fix the CodeGen/PowerPC/vec_constants.ll regression.
...
llvm-svn: 32057
2006-12-01 01:45:39 +00:00
12c94949e0
Introducing external weak linkage. Darwin codegen should be added later.
...
llvm-svn: 32052
2006-12-01 00:25:12 +00:00
6dbdfe2baa
Factor out GVRequiresExtraLoad() from .h to .cpp
...
llvm-svn: 32048
2006-11-30 22:42:55 +00:00
ae1cd75af7
- Use a different wrapper node for RIP-relative GV, etc.
...
- Proper support for both small static and PIC modes under X86-64
- Some (non-optimal) support for medium modes.
llvm-svn: 32046
2006-11-30 21:55:46 +00:00
aafeaef8c8
MachineInstr::setOpcode -> MachineInstr::setInstrDescriptor
...
llvm-svn: 32034
2006-11-30 07:12:03 +00:00
fef6400f01
Remove the ugly SPARCV9 TargetInstrDescriptors hack.
...
llvm-svn: 32033
2006-11-30 07:10:43 +00:00
7a9238c84d
In PIC mode, GV not requiring an extra load can be used as address immediate.
...
llvm-svn: 32028
2006-11-29 23:48:14 +00:00
8c84c7cd0d
Clean up.
...
llvm-svn: 32027
2006-11-29 23:46:27 +00:00
0b1692216d
Fix for PR1018 - Better support for X86-64 Linux in small code model.
...
llvm-svn: 32026
2006-11-29 23:19:46 +00:00
2f648fc55d
Fix bug codegen'ing FP constant vectors with integer splats. Make sure the
...
created intrinsics have the right integer types. This fixes
PowerPC/2006-11-29-AltivecFPSplat.ll
llvm-svn: 32024
2006-11-29 19:58:49 +00:00
152671f0bf
Offset for load of 32-bit arg in 64-bit world was incorrect.
...
llvm-svn: 32019
2006-11-29 13:37:09 +00:00
28a9e9b230
Custom lower READCYCLECOUNTER for x86-64.
...
llvm-svn: 32017
2006-11-29 08:28:13 +00:00
0d67dde00a
done
...
llvm-svn: 32013
2006-11-29 07:21:46 +00:00
8facb43593
16-byte stack alignment for X86-64 ELF. Patch by Dan Gohman.
...
llvm-svn: 32004
2006-11-29 02:00:40 +00:00
38084725a2
Upgrade the ugly darwin 64-bit bswap idiom (bswap %eax / bswap %edx /
...
xchgl %eax, %edx) to llvm.bswap.i64. This compiles:
long long test2(long long A) {
return _OSSwapInt64(A);
}
to:
_test2:
movl 8(%esp), %eax
movl 4(%esp), %edx
bswapl %eax
bswapl %edx
ret
instead of:
_test2:
movl 8(%esp), %edx
movl 4(%esp), %eax
bswap %eax
bswap %edx
xchgl %eax, %edx
ret
GCC manages (with -fomit-frame-pointer) the uglier:
_test2:
subl $4, %esp
movl 8(%esp), %eax
movl 12(%esp), %edx
bswap %eax
bswap %edx
xchgl %eax, %edx
addl $4, %esp
ret
llvm-svn: 32001
2006-11-29 01:48:01 +00:00
0fc6ae0c3d
Trivially lower 'bswap $0' into llvm.bswap. This fixes hexxagon with the
...
JIT on darwin/x86, which has htonl implemented as inline asm.
llvm-svn: 31999
2006-11-29 01:14:06 +00:00
904ca9c688
gcc doesn't like an empty colbber list
...
llvm-svn: 31987
2006-11-28 23:07:32 +00:00
f52ae7ec72
Identities are default now
...
llvm-svn: 31980
2006-11-28 22:28:08 +00:00
8b59fd03c2
Make identity default, and fix PR1020
...
llvm-svn: 31979
2006-11-28 22:25:32 +00:00
69b1825488
New entries.
...
llvm-svn: 31976
2006-11-28 19:59:25 +00:00
7f739d5bdd
update comments
...
llvm-svn: 31975
2006-11-28 19:56:02 +00:00
212f15fa8a
Get the asminfo for the target most closely matching the module and use that for inline asm
...
llvm-svn: 31974
2006-11-28 19:53:36 +00:00
2675e23a7e
X86 asm -> gcc asm translation table (incomplete)
...
llvm-svn: 31973
2006-11-28 19:52:49 +00:00
ff35b449a0
Add per-target support for asm translation in the cbe
...
llvm-svn: 31972
2006-11-28 19:52:20 +00:00
40182179b6
Remove debug code.
...
llvm-svn: 31970
2006-11-28 18:27:02 +00:00
ec05b046c7
Prime text sections to improve branch locality in large object files.
...
llvm-svn: 31969
2006-11-28 18:21:52 +00:00
f4e2e009d9
32-bit int space was not accounted for properly in lowerCall.
...
llvm-svn: 31966
2006-11-28 14:53:52 +00:00
8ddbdc70b7
Fix JIT encoding bugs for shift / rotate by one ops.
...
llvm-svn: 31952
2006-11-28 01:28:00 +00:00
e8c64aba11
Preliminary support for inline asm in the cbe. The target specific ugliness
...
is still in Writer, but issolated to a single function. This might be split
into something in each target directory. This is sufficient to get through
archie and an strcpy impl on linux-x86.
Module level asm is not handled.
llvm-svn: 31948
2006-11-27 23:50:49 +00:00
20350c4025
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
...
of opcode and number of operands.
llvm-svn: 31947
2006-11-27 23:37:22 +00:00
16eaffe595
When truncating to bool, it is necessary to & with 1 for all casts that
...
can result in a bool. Previously PtrToInt, FPToUI and FPToSI were missing
this operation.
llvm-svn: 31938
2006-11-27 18:51:06 +00:00
6c38f0bb07
For PR950:
...
The long awaited CAST patch. This introduces 12 new instructions into LLVM
to replace the cast instruction. Corresponding changes throughout LLVM are
provided. This passes llvm-test, llvm/test, and SPEC CPUINT2000 with the
exception of 175.vpr which fails only on a slight floating point output
difference.
llvm-svn: 31931
2006-11-27 01:05:10 +00:00
24cdf575e7
fix storing bools to mem and unordered FP ops
...
llvm-svn: 31920
2006-11-26 04:34:26 +00:00
6968c497de
Add newline at end of file.
...
llvm-svn: 31902
2006-11-25 05:41:02 +00:00
5b96cdebb0
Refactored *GVRequiresExtraLoad() to Subtarget method.
...
llvm-svn: 31887
2006-11-21 00:01:06 +00:00
ec5dbccdcf
in ppc64-mode, don't allocate the 32-bit version of r13 either.
...
llvm-svn: 31884
2006-11-20 20:48:05 +00:00
ac36360348
r13 is the thread pointer on darwin/ppc64, don't allocate it.
...
llvm-svn: 31882
2006-11-20 19:33:51 +00:00
3e96211bc8
Fix codegen for x86-64 on systems (like ppc or i386) that don't have 64-bit
...
features autodetected. This fixes PR1010 and Regression/CodeGen/X86/xmm-r64.ll
on non-x86-64 hosts.
llvm-svn: 31879
2006-11-20 18:16:05 +00:00
37d080b11d
We should perform extra load for dllimported calls
...
llvm-svn: 31874
2006-11-20 10:46:14 +00:00
2cca385fbb
on ppc64, float arguments take 8-byte stack slots not 4-byte stack slots.
...
Also, valist should create a pointer RC reg class value, not a GPRC value.
llvm-svn: 31840
2006-11-18 01:57:19 +00:00
572e238c14
make sure to safe LR8 in the right stack slot for PPC64
...
llvm-svn: 31839
2006-11-18 01:34:43 +00:00
9ca15c8914
Pretty print 'rldicr r2, r2, 2, 61' as 'sldi r2, r2, 2'.
...
llvm-svn: 31838
2006-11-18 01:23:56 +00:00
542dfd5510
Rewrite the branch selector to be correct in the face of large functions.
...
The algorithm it used before wasn't 100% correct, we now use an iterative
expansion model. This fixes assembler errors when compiling 403.gcc with
tail merging enabled.
Change the way the branch selector works overall: Now, the isel generates
PPC::BCC instructions (as it used to) directly, and these BCC instructions
are emitted to the output or jitted directly if branches don't need
expansion. Only if branches need expansion are instructions rewritten
and created. This should make branch select faster, and eliminates the
Bxx instructions from the .td file.
llvm-svn: 31837
2006-11-18 00:32:03 +00:00
33fc1d45e5
add encoding for BCC, after finally wrestling strange ppc/tblgen endianness
...
issues to the ground.
llvm-svn: 31836
2006-11-17 23:53:28 +00:00
be9377a1e3
convert PPC::BCC to use the 'pred' operand instead of separate predicate
...
value and CR reg #. This requires swapping the order of these everywhere
that touches BCC and requires us to write custom matching logic for
PPCcondbranch :(
llvm-svn: 31835
2006-11-17 22:37:34 +00:00
e0263794f4
rename PPC::COND_BRANCH to PPC::BCC
...
llvm-svn: 31834
2006-11-17 22:14:47 +00:00
8c6a41ea12
start using PPC predicates more consistently.
...
llvm-svn: 31833
2006-11-17 22:10:59 +00:00
9e8093ae20
For unsigned 8-bit division. Use movzbw to set the lower 8 bits of AX while
...
clearing the upper 8-bits instead of issuing two instructions. This also
eliminates the need to target the AH register which can be problematic on
x86-64.
llvm-svn: 31832
2006-11-17 22:10:14 +00:00
de5fa025ab
Hopefully a good crack at making debugging work on intel -disable-fp-elim.
...
llvm-svn: 31830
2006-11-17 21:19:15 +00:00
73106b5e2a
Assert unhandled case.
...
llvm-svn: 31828
2006-11-17 18:49:39 +00:00
1823346b3e
1. Ignore the -disable-fp-elim when the routine is a leaf.
...
2. Offsets on 64-bit stores are still in bytes.
llvm-svn: 31824
2006-11-17 16:09:31 +00:00
91542a4f2d
Typo. Fix the nightly tests.
...
llvm-svn: 31823
2006-11-17 14:06:41 +00:00
c8e81b8d48
Removed even more std::cerr and #include <iostream> things.
...
llvm-svn: 31813
2006-11-17 07:52:03 +00:00
3b7261b18e
implement a todo: change a map into a vector
...
llvm-svn: 31805
2006-11-17 01:52:23 +00:00
be1a4d80b3
fix typo
...
llvm-svn: 31799
2006-11-17 00:49:36 +00:00
a715288b40
implicit_def_vrrc doesn't generate code.
...
llvm-svn: 31797
2006-11-16 23:49:52 +00:00
572dc9cb4e
Correct instructions for moving data between GR64 and SSE registers; also correct load i64 / store i64 from v2i64.
...
llvm-svn: 31795
2006-11-16 23:33:25 +00:00
7ae482c52a
Fix a potential bug: MOVPDI2DI, etc. are not copy instructions.
...
llvm-svn: 31794
2006-11-16 23:22:26 +00:00
48850c10c0
This is a general clean up of the PowerPC ABI. Address several problems and
...
bugs including making sure that the TOS links back to the previous frame,
that the maximum call frame size is not included twice when using frame
pointers, no longer growing the frame on calls, double storing of SP and
a cleaner/faster dynamic alloca.
llvm-svn: 31792
2006-11-16 22:43:37 +00:00
30055b9208
fix a regression that I introduced. stdu should scale the offset by 4
...
before printing it.
llvm-svn: 31791
2006-11-16 21:45:30 +00:00
c5e769710e
Align stubs on 4 byte boundary. This fixes 447.dealII.
...
llvm-svn: 31790
2006-11-16 20:13:34 +00:00
96d7386006
add a statistic
...
llvm-svn: 31785
2006-11-16 18:13:49 +00:00
a7ff5162b0
fix broken encoding
...
llvm-svn: 31778
2006-11-16 01:01:28 +00:00
e742d9a4b7
add ppc64 r+i stores with update.
...
llvm-svn: 31776
2006-11-16 00:57:19 +00:00
6f5840c409
add patterns for ppc32 preinc stores. ppc64 next.
...
llvm-svn: 31775
2006-11-16 00:41:37 +00:00
3a494989a6
switch these back to the 'bad old way'
...
llvm-svn: 31774
2006-11-16 00:33:34 +00:00
b4e911d15a
Fix ppc64 epilog bug.
...
llvm-svn: 31771
2006-11-15 23:35:30 +00:00
5771156be0
Stop using isTwoAddress, switching to operand constraints instead.
...
Tell the codegen emitter that specific operands are not to be encoded, fixing
JIT regressions w.r.t. pre-inc loads and stores (e.g. lwzu, which we generate
even when general preinc loads are not enabled).
llvm-svn: 31770
2006-11-15 23:24:18 +00:00
5c23899c7d
add a new field needed by the code emitter generator.
...
llvm-svn: 31768
2006-11-15 22:55:04 +00:00
dc2c8748a7
Properly transfer kill / dead info.
...
llvm-svn: 31765
2006-11-15 20:58:11 +00:00
bbbcac39e6
Kill / dead info has been moved to MI's.
...
llvm-svn: 31764
2006-11-15 20:56:39 +00:00
c57819d4a3
commuteInstruction should propagate kill / dead info.
...
llvm-svn: 31763
2006-11-15 20:56:03 +00:00
474b5b7c95
fix ldu/stu jit encoding. Swith 64-bit preinc load instrs to use memri
...
addrmodes.
llvm-svn: 31757
2006-11-15 19:55:13 +00:00
2775aba51d
Simplify IntrinsicLowering and clarify that it is only for use by the
...
CBE and interpreter.
llvm-svn: 31755
2006-11-15 18:00:10 +00:00
60c2a0154a
Remove unneeded forward decls
...
llvm-svn: 31754
2006-11-15 17:53:13 +00:00
0e117c7e9d
Fix the PPC regressions last night
...
llvm-svn: 31752
2006-11-15 17:40:51 +00:00
1396961e85
Switch loads over to use memri as the operand instead of a reg/imm operand
...
pair for cleanliness. Add instructions for PPC32 preinc-stores with commented
out patterns. More improvement is needed to enable the patterns, but we're
getting close.
llvm-svn: 31749
2006-11-15 02:43:19 +00:00
cf772f7eca
Revert. This wasn't meant to be checked in.
...
llvm-svn: 31737
2006-11-14 19:20:33 +00:00
e79a451475
group load and store instructions together. No functionality change.
...
llvm-svn: 31736
2006-11-14 19:19:53 +00:00
58e8bed48e
Fix predicates for unindexed stores so they don't accidentally match indexed
...
stores.
llvm-svn: 31735
2006-11-14 19:13:39 +00:00
44dbdbe5cf
Rework PPC64 calls. Now we have a LR8/CTR8 register which the PPC64 calls
...
clobber. This allows LR8 to be save/restored correctly as a 64-bit quantity,
instead of handling it as a 32-bit quantity. This unbreaks ppc64 codegen when
the code is actually located above the 4G boundary.
llvm-svn: 31734
2006-11-14 18:44:47 +00:00
b542925b22
remove a ton of custom selection logic no longer needed
...
llvm-svn: 31733
2006-11-14 18:43:11 +00:00
4916acbd0f
it would be nice of ctlz were lowered to bsf etc.
...
llvm-svn: 31730
2006-11-14 08:08:46 +00:00
97ff46b3cc
lower "X = seteq Y, Z" to '(shr (ctlz (xor Y, Z)), 5)' instead of
...
'(shr (ctlz (sub Y, Z)), 5)'.
The use of xor better exposes the operation to bit-twiddling logic in the
dag combiner. For example, this:
typedef struct {
unsigned prefix : 4;
unsigned code : 4;
unsigned unsigned_p : 4;
} tree_common;
int foo(tree_common *a, tree_common *b) {
return a->code == b->code;
}
Now compiles to:
_foo:
lwz r2, 0(r4)
lwz r3, 0(r3)
xor r2, r3, r2
rlwinm r2, r2, 28, 28, 31
cntlzw r2, r2
srwi r3, r2, 5
blr
instead of:
_foo:
lbz r2, 3(r4)
lbz r3, 3(r3)
srwi r2, r2, 4
srwi r3, r3, 4
subf r2, r2, r3
cntlzw r2, r2
srwi r3, r2, 5
blr
saving a cycle.
llvm-svn: 31725
2006-11-14 05:28:08 +00:00
6dc22332bf
add a note
...
llvm-svn: 31719
2006-11-14 01:57:53 +00:00
683712583a
minor tweaks, reject vector preinc.
...
llvm-svn: 31717
2006-11-14 01:38:31 +00:00
dbd3d294e6
Matches MachineInstr changes.
...
llvm-svn: 31712
2006-11-13 23:36:35 +00:00
1121e50f7e
teach the g5 hazard recognizer about update loads. This fixes
...
Ptrdist/anagram among others.
llvm-svn: 31708
2006-11-13 20:11:06 +00:00
0df2ada9d4
Cute example from Chris Lattner.
...
llvm-svn: 31696
2006-11-13 00:23:28 +00:00
1dfc6110ff
Make sure stack link is set in 64-bit.
...
llvm-svn: 31690
2006-11-11 22:22:07 +00:00
0d550cc56c
implement proper PPC64 prolog/epilog codegen.
...
llvm-svn: 31684
2006-11-11 19:05:28 +00:00
66c502b54a
Running with frame pointers prevented debugging, external probes and
...
potentially some system calls/exception handling from working. TOS must always
link to previous frame. This is a short term workaround until alloca scheme is
reworked.
llvm-svn: 31677
2006-11-11 10:21:58 +00:00
db04c958a5
Add implicit use / def operands to created MI's.
...
llvm-svn: 31676
2006-11-11 10:21:44 +00:00
a36cdcfaf8
Add all implicit defs to FP_REG_KILL mi.
...
llvm-svn: 31674
2006-11-11 07:19:36 +00:00
c5102bfc7c
allow the offset of a preinc'd load to be the low-part of a global. This
...
produces this clever code:
_millisecs:
lis r2, ha16(_Time.1182)
lwzu r3, lo16(_Time.1182)(r2)
lwz r2, 4(r2)
addic r4, r2, 1
addze r3, r3
blr
instead of this:
_millisecs:
lis r2, ha16(_Time.1182)
la r3, lo16(_Time.1182)(r2)
lwz r2, lo16(_Time.1182)(r2)
lwz r3, 4(r3)
addic r4, r3, 1
addze r3, r2
blr
for:
long %millisecs() {
%tmp = load long* %Time.1182 ; <long> [#uses=1]
%tmp1 = add long %tmp, 1 ; <long> [#uses=1]
ret long %tmp1
}
llvm-svn: 31673
2006-11-11 04:53:30 +00:00
2ff632c54b
Mark operands as symbol lo instead of imm32 so that they print lo(x) around
...
globals.
llvm-svn: 31672
2006-11-11 04:51:36 +00:00
b314b155ed
ppc64 doesn't have lwau, don't attempt to form it.
...
llvm-svn: 31656
2006-11-11 00:08:42 +00:00
c9fa36d706
implement preinc support for r+i loads on ppc64
...
llvm-svn: 31654
2006-11-10 23:58:45 +00:00
915026cdc3
Add a note.
...
llvm-svn: 31650
2006-11-10 22:09:17 +00:00
5b725a71a9
These are done.
...
llvm-svn: 31649
2006-11-10 22:03:35 +00:00
49683ba236
Don't dag combine floating point select to max and min intrinsics. Those
...
take v4f32 / v2f64 operands and may end up causing larger spills / restores.
Added X86 specific nodes X86ISD::FMAX, X86ISD::FMIN instead.
This fixes PR996.
llvm-svn: 31645
2006-11-10 21:43:37 +00:00
fb44822a98
Fix a bug in SelectScalarSSELoad. Since the load is wrapped in a
...
SCALAR_TO_VECTOR, even if the hasOneUse() check pass we may end up folding
the load into two instructions. Make sure we check the SCALAR_TO_VECTOR
has only one use as well.
llvm-svn: 31641
2006-11-10 21:23:04 +00:00
6c8656a6b1
dform 8/9 are identical to dform 1
...
llvm-svn: 31637
2006-11-10 17:51:02 +00:00
286357480c
Fix a potential bug.
...
llvm-svn: 31634
2006-11-10 09:13:37 +00:00
8c9c6d71ed
Add implicit def / use operands to MachineInstr.
...
llvm-svn: 31633
2006-11-10 08:43:01 +00:00
ce6455489a
add an initial cut at preinc loads for ppc32. This is broken for ppc64
...
(because the 64-bit reg target versions aren't implemented yet), doesn't
support r+r addr modes, and doesn't handle stores, but it works otherwise. :)
This is disabled unless -enable-ppc-preinc is passed to llc for now.
llvm-svn: 31621
2006-11-10 02:08:47 +00:00
cd436327f1
add note about ugly codegen with preinc
...
llvm-svn: 31617
2006-11-10 01:33:53 +00:00
14140059f0
Use TargetInstrInfo::getNumOperands() instead of MachineInstr::getNumOperands(). In preparation for implicit reg def/use changes.
...
llvm-svn: 31616
2006-11-10 01:28:43 +00:00
b9c91c265c
Fixing PR990: http://llvm.org/PR990 .
...
This should unbreak csretcc on Linux & mingw targets. Several tests from
llvm-test should be also restored (fftbench, bigfib).
llvm-svn: 31613
2006-11-10 00:48:11 +00:00
4e03cb1945
add a note about viterbi
...
llvm-svn: 31612
2006-11-10 00:23:26 +00:00
36a8fbf771
PPC supports i32 / i64 pre-inc load / store.
...
llvm-svn: 31599
2006-11-09 19:11:50 +00:00
c034f14fbe
Rename ISD::MemOpAddrMode to ISD::MemIndexedMode
...
llvm-svn: 31596
2006-11-09 18:44:21 +00:00
b15000736c
Rename ISD::MemOpAddrMode to ISD::MemIndexedMode
...
llvm-svn: 31595
2006-11-09 17:55:04 +00:00
5f7ab1b964
implement load effective address similar to the alpha backend
...
remove lea_addri and the now unused memri addressing mode
llvm-svn: 31592
2006-11-09 13:58:55 +00:00
1698c2999c
Remove M_2_ADDR_FLAG.
...
llvm-svn: 31583
2006-11-09 02:22:54 +00:00
c9a4cdc9c9
Added indexed store node and patfrag's.
...
llvm-svn: 31576
2006-11-08 23:02:11 +00:00
3b3b786f03
Use movl+xchgl instead of pushl+popl.
...
llvm-svn: 31572
2006-11-08 20:35:37 +00:00
6cd0909da7
Match tblegen changes.
...
llvm-svn: 31571
2006-11-08 20:34:28 +00:00
708cb60588
initial implementation of addressing mode 2
...
TODO: fix lea_addri
llvm-svn: 31552
2006-11-08 17:07:32 +00:00
fdff938a7e
For PR950:
...
This patch converts the old SHR instruction into two instructions,
AShr (Arithmetic) and LShr (Logical). The Shr instructions now are not
dependent on the sign of their operands.
llvm-svn: 31542
2006-11-08 06:47:33 +00:00
a801fcedd3
Refactor all the addressing mode selection stuff into the isel lowering
...
class, where it can be used for preinc formation.
llvm-svn: 31536
2006-11-08 02:15:41 +00:00
6a5a4f85d3
correct the (currently unused) pattern for lwzu.
...
llvm-svn: 31535
2006-11-08 02:13:12 +00:00
922e191116
Fixed a bug which causes x86 be to incorrectly match
...
shuffle v, undef, <2, ?, 3, ?>
to movhlps
It should match to unpckhps instead.
Added proper matching code for
shuffle v, undef, <2, 3, 2, 3>
llvm-svn: 31519
2006-11-07 22:14:24 +00:00
be7033b346
add a note from viterbi
...
llvm-svn: 31506
2006-11-07 18:30:21 +00:00
d94477f6c9
fix encoding of BLR
...
llvm-svn: 31485
2006-11-07 01:51:50 +00:00
7e885005ba
add a note
...
llvm-svn: 31477
2006-11-06 21:26:49 +00:00
7d6f3db3e2
Unbreak VC++ build.
...
llvm-svn: 31464
2006-11-05 19:31:28 +00:00
35b927e0d3
Fix a bug in the last patch and convert to && instead of & for logical expr.
...
llvm-svn: 31463
2006-11-05 19:26:37 +00:00
6088f8af16
Implement the -enabled-cbe-printf-a feature.
...
llvm-svn: 31462
2006-11-05 17:09:41 +00:00
2959789c92
encode BLR predicate info for the JIT
...
llvm-svn: 31450
2006-11-04 05:42:48 +00:00
6be726048e
Go through all kinds of trouble to mark 'blr' as having a predicate operand
...
that takes a register and condition code. Print these pieces of BLR the
right way, even though it is currently set to 'always'.
Next up: get the JIT encoding right, then enhance branch folding to produce
predicated blr for simple examples.
llvm-svn: 31449
2006-11-04 05:27:39 +00:00
c8a68d08c3
Describe PPC predicates, which are a pair of CR# and condition.
...
llvm-svn: 31438
2006-11-03 23:53:25 +00:00
4905d2c5b4
initial steps to getting the predicate on PPC::BLR right.
...
llvm-svn: 31437
2006-11-03 23:52:18 +00:00
4fcc04a32a
remove dead var
...
llvm-svn: 31436
2006-11-03 23:50:15 +00:00
9ac6442db6
remove dead/redundant vars
...
llvm-svn: 31435
2006-11-03 23:48:56 +00:00
eb7128465d
remove redundant/dead vars
...
llvm-svn: 31434
2006-11-03 23:47:20 +00:00
895d199348
remove dead vars
...
llvm-svn: 31433
2006-11-03 23:46:45 +00:00
2048373e71
add a note
...
llvm-svn: 31429
2006-11-03 22:27:39 +00:00
4ece5c04f4
revert previous patch
...
llvm-svn: 31411
2006-11-03 03:08:28 +00:00
94b29e9e91
Dead code.
...
llvm-svn: 31405
2006-11-03 02:08:41 +00:00
38b162c1d2
add createCFGSimplificationPass to ARMTargetMachine::addInstSelector
...
llvm-svn: 31400
2006-11-03 01:39:25 +00:00
799b96be08
silence warning
...
llvm-svn: 31395
2006-11-03 01:19:31 +00:00
b974b0a3e1
silence warnings.
...
llvm-svn: 31394
2006-11-03 01:18:29 +00:00
de2f0906e4
silence warning
...
llvm-svn: 31393
2006-11-03 01:13:15 +00:00
71f55131d4
silence warnings
...
llvm-svn: 31392
2006-11-03 01:11:05 +00:00
c0b1dec892
Make CBackend -pedantic clean.
...
llvm-svn: 31388
2006-11-03 00:00:57 +00:00
2de0910a1b
fix a bug reid noticed
...
llvm-svn: 31385
2006-11-02 23:39:53 +00:00
de46e48420
For PR786:
...
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.
llvm-svn: 31380
2006-11-02 20:25:50 +00:00
ac8668d62f
move ARMCondCodeToString to ARMAsmPrinter.cpp
...
remove unused variables from lowerCall
llvm-svn: 31378
2006-11-02 15:00:02 +00:00
d8b59f67f6
fix 2006-11-01-vastart.ll
...
llvm-svn: 31371
2006-11-02 03:05:26 +00:00
7eb55b395f
For PR950:
...
Replace the REM instruction with UREM, SREM and FREM.
llvm-svn: 31369
2006-11-02 01:53:59 +00:00
584a11ae22
Implement the getRegForInlineAsmConstraint method for PPC. With recent
...
sdisel changes, this eliminates a ton of copies around common inline asms.
For example:
int test2(int Y, int X) {
asm("foo %0, %1" : "=r"(X): "r"(X));
return X;
}
now compiles to:
_test2:
foo r3, r4
blr
instead of:
_test2:
mr r2, r4
foo r2, r2
mr r3, r2
blr
GCC produces:
_test2:
foo r4, r4
mr r3,r4
blr
llvm-svn: 31367
2006-11-02 01:44:04 +00:00
93cdd149f7
Rename
...
llvm-svn: 31364
2006-11-01 23:18:32 +00:00
1b2e60e970
Added getTiedToSrcOperand() to check for two-address'ness.
...
llvm-svn: 31360
2006-11-01 23:00:31 +00:00
3576405a26
print null values in bss
...
llvm-svn: 31349
2006-11-01 14:26:44 +00:00
0cd8d14c7c
implement zextload bool and truncstore bool
...
llvm-svn: 31348
2006-11-01 14:13:27 +00:00
94e5bc9e83
Fix ldmxcsr JIT encoding.
...
llvm-svn: 31343
2006-11-01 06:53:52 +00:00
7a6a5b9af5
Add constraints to Instruction class.
...
llvm-svn: 31332
2006-11-01 00:26:27 +00:00
dfbf91e59d
more shotenning
...
llvm-svn: 31331
2006-10-31 23:46:56 +00:00
a41c2d6432
Nuke dead code.
...
llvm-svn: 31327
2006-10-31 21:53:31 +00:00
44daa50bed
allow the address of a global to be used with the "i" constraint when in
...
-static mode. This implements PR882.
llvm-svn: 31326
2006-10-31 20:13:11 +00:00
60ce558aaa
implement the 'c' inline asm modifier character
...
llvm-svn: 31325
2006-10-31 20:12:30 +00:00
8b20fa42da
Let us play simplify the td file (and fix a few missed sub and mul patterns).
...
llvm-svn: 31322
2006-10-31 19:52:12 +00:00
f6a6966cd2
handle "st" as "st(0)"
...
llvm-svn: 31320
2006-10-31 19:42:44 +00:00
8c6949e5b2
Change the prototype for TargetLowering::isOperandValidForConstraint
...
llvm-svn: 31318
2006-10-31 19:40:43 +00:00
692e4155aa
Add all that branch mangling niftiness
...
llvm-svn: 31313
2006-10-31 16:49:55 +00:00
4e825336a0
add support for calling functions when the caller has variable sized objects
...
llvm-svn: 31312
2006-10-31 13:03:26 +00:00
aa4c0f9374
1. Clean up code due to changes in SwitchTo*Section(2)
...
2. Added partial debug support for mingw\cygwin targets (the same as
Linux\ELF). Please note, that currently mingw\cygwin uses 'stabs' format
for storing debug info by default, thus many (runtime) libraries has
this information included. These formats shouldn't be mixed in one binary
('stabs' & 'DWARF'), otherwise binutils tools will be confused.
llvm-svn: 31311
2006-10-31 08:31:24 +00:00
49993529eb
Unbreaking static ctors patch.
...
Defaulting second arguments of SwitchTo*Section, this should make things
somehow clearer.
llvm-svn: 31306
2006-10-31 06:11:06 +00:00
2545fe6d93
Make this compile again.
...
llvm-svn: 31304
2006-10-31 01:45:56 +00:00
de5ecd6bc1
Apply Aton's LLVM patch for PR973: Linux ctors / dtors support.
...
llvm-svn: 31303
2006-10-31 01:26:55 +00:00
3e36e07db2
fix miscompilation of llvm.isunordered, where we branched on the opposite
...
condition. This fixes miscompilation of Olden/bh and many others.
llvm-svn: 31301
2006-10-30 23:02:25 +00:00
b51b5c0b1f
Add debug support for X86/ELF targets (Linux). This allows llvm-gcc4
...
generated object modules to be debugged with gdb. Hopefully this helps
pre-release debugging.
llvm-svn: 31299
2006-10-30 22:32:30 +00:00
7443600ef8
fix wonky indentation
...
llvm-svn: 31298
2006-10-30 22:27:23 +00:00
0d41d19427
All targets expand BR_JT for now.
...
llvm-svn: 31294
2006-10-30 08:02:39 +00:00
113f7470e6
implement the BlockHasNoFallThrough hook
...
llvm-svn: 31264
2006-10-28 17:35:02 +00:00
53ebf20c26
add another target hook for branch folding.
...
llvm-svn: 31262
2006-10-28 17:29:57 +00:00
ae8c29a7d3
Doh. Must check if GV is constant first before putting it in .cstring.
...
llvm-svn: 31253
2006-10-28 05:56:51 +00:00
0d782b4c60
Doh. Must check if GV is constant first.
...
llvm-svn: 31252
2006-10-28 05:56:06 +00:00
a6873c0f88
don't dist internal readme
...
llvm-svn: 31247
2006-10-28 00:51:15 +00:00
acc6b37d0d
don't dist internal readme's
...
llvm-svn: 31246
2006-10-28 00:49:54 +00:00
3be52bb570
don't distribute internal readme's
...
llvm-svn: 31245
2006-10-28 00:48:27 +00:00
247e09a07c
Make sure all the readme files get distributed.
...
llvm-svn: 31244
2006-10-28 00:11:39 +00:00
28174f5a3a
this doesn't occur any more in mason
...
llvm-svn: 31236
2006-10-27 22:02:19 +00:00
4c0cc53da1
the code in question is now:
...
cmpw cr0, r7, r3
ble cr0, LBB1_5 ;bb25
LBB1_8: ;bb17
cmpw cr0, r8, r5
bgt cr0, LBB1_2 ;bb
which is just as good as crnand.
llvm-svn: 31235
2006-10-27 22:00:55 +00:00
e056dd5928
Fixed a significant bug where unpcklpd is incorrectly used to extract element 1 from a v2f64 value.
...
llvm-svn: 31228
2006-10-27 21:08:32 +00:00
bf3df77758
Fix for PR968: expand vector sdiv, udiv, srem, urem.
...
llvm-svn: 31220
2006-10-27 18:49:08 +00:00
e54243f030
Initialize CStringSection member var.
...
llvm-svn: 31214
2006-10-27 16:14:06 +00:00
f53ae69365
Change load PatFrag to ignore indexed load.
...
llvm-svn: 31210
2006-10-26 21:55:50 +00:00
e1e06c2de8
Place cstrings in .cstring section.
...
llvm-svn: 31207
2006-10-26 21:48:57 +00:00
392f645783
Put cstrings in .cstring section when compiling for Mac OS X.
...
llvm-svn: 31203
2006-10-26 19:18:18 +00:00
a23166d6a4
initial support for frame pointers
...
llvm-svn: 31197
2006-10-26 13:31:26 +00:00
c6b52da458
Enclose a case in { and } so that the pickier compilers don't complain.
...
llvm-svn: 31196
2006-10-26 06:17:40 +00:00
7e80b0b31e
For PR950:
...
Make necessary changes to support DIV -> [SUF]Div. This changes llvm to
have three division instructions: signed, unsigned, floating point. The
bytecode and assembler are bacwards compatible, however.
llvm-svn: 31195
2006-10-26 06:15:43 +00:00
c415c5be49
During vector shuffle lowering, we sometimes commute a vector shuffle to try
...
to match MOVL (movss, movsd, etc.). Don't forget to commute it back and try
unpck* and shufp* if that doesn't pan out.
llvm-svn: 31186
2006-10-25 21:49:50 +00:00
7e065ff7e4
X86ISD::PEXTRW 3rd operand type is always target pointer type.
...
llvm-svn: 31185
2006-10-25 21:35:05 +00:00
798b306311
Remove -disable-x86-shuffle-opti
...
llvm-svn: 31183
2006-10-25 20:48:19 +00:00
71b99297aa
Move getPreferredAlignmentLog from AsmPrinter to TargetData
...
llvm-svn: 31171
2006-10-24 20:32:14 +00:00
bd29281e97
expand ISD::VACOPY
...
llvm-svn: 31170
2006-10-24 20:15:21 +00:00
9030fc690a
Fix CodeGen/IA64/ret-0.ll, which has apparently been broken since some of the
...
isel changes happened months ago.
llvm-svn: 31164
2006-10-24 17:09:43 +00:00
ed32883b27
fix warning about missing newline at end of file
...
llvm-svn: 31162
2006-10-24 17:07:11 +00:00
aaeede0aa2
implement uncond branch insertion, mark branches with isBranch.
...
llvm-svn: 31160
2006-10-24 16:47:57 +00:00
ccd7704354
implement uncond branch insertion for the branch folding pass
...
llvm-svn: 31159
2006-10-24 16:44:55 +00:00
042d56230e
implement uncond branch insertion so alpha works work branchfolding.
...
llvm-svn: 31158
2006-10-24 16:41:36 +00:00
b7267bd034
implement uncond branch insertion for sparc to fix regressions from last night
...
due to branchfolding
llvm-svn: 31157
2006-10-24 16:39:19 +00:00
f054003ba7
new bad case
...
llvm-svn: 31156
2006-10-24 16:12:47 +00:00
d43e8a7429
Add intrinsics for the rest of the DCB* instructions.
...
llvm-svn: 31148
2006-10-24 01:08:42 +00:00
b43efe86f5
implement STRB and STRH
...
llvm-svn: 31138
2006-10-23 20:34:27 +00:00
cd5f662c7b
expand ISD::MEMSET
...
llvm-svn: 31137
2006-10-23 20:08:22 +00:00
bb3084546a
this part implemented.
...
llvm-svn: 31122
2006-10-22 21:40:12 +00:00
41a83d7871
Do section switching right way for Mingw\Cygwin and Linux.
...
This will allow (after llvm-gcc linkage fix) more dummy tests using
libstdc++ to pass on mingw :)
llvm-svn: 31120
2006-10-22 21:37:13 +00:00
aa1c614784
Don't generate a prototype for _setjmp. At least on Linux, this function
...
has a different prototype than the one #included from <setjmp.h>. This
patch fixes siod and a number of other test cases on Linux that were
failing the CBE because of this _setjmp issue.
llvm-svn: 31112
2006-10-22 09:58:21 +00:00
23f22de26f
Implement support for branch reversal, fix a bug in branch analysis.
...
This provides stuff like:
cmpw cr0, r15, r29
mr r14, r15
- bge cr0, LBB3_111 ;bb656
- b LBB3_90 ;bb501
+ blt cr0, LBB3_90 ;bb501
LBB3_111: ;bb656
lwz r18, 68(r1)
which is particularly good for dispatch group formation.
llvm-svn: 31101
2006-10-21 06:03:11 +00:00
3a897f31fa
Implement support for branch condition reversal.
...
llvm-svn: 31099
2006-10-21 05:52:40 +00:00
d881660366
Simplify code, no functionality change
...
llvm-svn: 31097
2006-10-21 05:42:09 +00:00
94e04442eb
implement support for inserting a cond branch
...
llvm-svn: 31096
2006-10-21 05:36:13 +00:00
6fca75ec05
allow insertion of a conditional branch with fall-through
...
llvm-svn: 31095
2006-10-21 05:34:23 +00:00
20e75d4635
update assert message
...
llvm-svn: 31093
2006-10-21 04:42:29 +00:00
8366b874a9
bugfix
...
llvm-svn: 31074
2006-10-20 20:44:34 +00:00
c0fb567e23
Implement branch analysis/xform hooks required by the branch folding pass.
...
llvm-svn: 31065
2006-10-20 17:42:20 +00:00
e0fc4dfc22
For PR950:
...
This patch implements the first increment for the Signless Types feature.
All changes pertain to removing the ConstantSInt and ConstantUInt classes
in favor of just using ConstantInt.
llvm-svn: 31063
2006-10-20 07:07:24 +00:00
336d62e99a
use Pat to implement extloadi8 and extloadi16
...
llvm-svn: 31052
2006-10-19 17:05:03 +00:00
f8274c0318
implement undef
...
llvm-svn: 31049
2006-10-19 13:45:00 +00:00
ea67b973c2
print common symbols
...
llvm-svn: 31048
2006-10-19 13:30:40 +00:00
ff62819e2f
implement extloadi8 and extloadi16
...
llvm-svn: 31047
2006-10-19 12:45:04 +00:00
3c563c5072
expand SIGN_EXTEND_INREG
...
llvm-svn: 31046
2006-10-19 12:06:50 +00:00
b260306625
expand brind so that we don't have to implement jump tables right now
...
llvm-svn: 31045
2006-10-19 10:56:43 +00:00
f4aeff00c2
fit in 80 cols
...
llvm-svn: 31039
2006-10-18 18:26:48 +00:00
35a1471046
add a note
...
llvm-svn: 31038
2006-10-18 17:04:09 +00:00
bad440742e
add blx
...
llvm-svn: 31037
2006-10-18 16:21:43 +00:00
01dd97a8aa
add isTerminatortto b and bcond
...
llvm-svn: 31036
2006-10-18 16:20:57 +00:00
b21e8d2e12
implement CallingConv::Fast as CallingConv::C
...
llvm-svn: 31034
2006-10-18 12:03:07 +00:00
24b7ac303c
Fixed mingw\cygwin linkonce linkage once again.
...
Added workaround for linker bug with linkonce sections.
Changed sections prefix to allow linker merge them
(PE loader doesn't like too much long-named sections :) )
All of this unbreaks libstdc++ on mingw32 allowing (small)
programs to be compiled, linked and run.
llvm-svn: 31033
2006-10-18 09:12:29 +00:00
454436dcc5
set the ppc64 stack pointer right, dynamic alloca now works for ppc64
...
llvm-svn: 31028
2006-10-18 01:20:43 +00:00
ab4df83426
Expand alloca for ppc64
...
llvm-svn: 31027
2006-10-18 01:18:48 +00:00
0408e5b7ce
expose DWARF_LABEL opcode# so the branch folder can update debug info properly.
...
llvm-svn: 31024
2006-10-17 22:41:45 +00:00
ba8f296167
expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM
...
llvm-svn: 31014
2006-10-17 21:05:33 +00:00
3968263ca8
add the FPUnaryOp and DFPUnaryOp classes
...
llvm-svn: 31013
2006-10-17 20:45:22 +00:00
99bf133d58
add FABSS and FABSD
...
llvm-svn: 31012
2006-10-17 20:33:13 +00:00
75b01beb2f
Adding linkonce linkage codegeneration support for mingw32\cygwin
...
targets.
llvm-svn: 31011
2006-10-17 20:29:49 +00:00
2d7d14262a
remove extra [] in stores
...
llvm-svn: 31008
2006-10-17 18:29:14 +00:00
a61f0105bd
add support for inserting an uncond branch
...
llvm-svn: 31003
2006-10-17 18:06:55 +00:00
19398ec86e
initial implementation of addressing mode 5
...
llvm-svn: 31002
2006-10-17 18:04:53 +00:00
feb50708eb
add the immediate to the Offset in eliminateFrameIndex
...
llvm-svn: 30998
2006-10-17 14:34:02 +00:00
418c8e69bb
add FSTD and FSTS
...
llvm-svn: 30996
2006-10-17 13:36:07 +00:00
c31ee94920
add FCPYS and FCPYD
...
llvm-svn: 30995
2006-10-17 13:13:23 +00:00
2794184191
Use S_debug for dwarf info.
...
llvm-svn: 30994
2006-10-17 11:30:57 +00:00
a3e1ad7a61
Proper fix.
...
llvm-svn: 30993
2006-10-17 00:24:49 +00:00
ed60d16ac7
One more try.
...
llvm-svn: 30992
2006-10-16 23:44:08 +00:00
1367ff084d
Unbreak x86-64 build.
...
llvm-svn: 30990
2006-10-16 22:53:28 +00:00
afdd47ace4
add fdivs e fdivd
...
llvm-svn: 30988
2006-10-16 21:50:04 +00:00
f719c5f43d
expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS
...
llvm-svn: 30987
2006-10-16 21:10:32 +00:00
afb610468b
Added a X86CompilationCallback variant which saves XMM argument registers for targets with SSE.
...
llvm-svn: 30986
2006-10-16 21:01:55 +00:00
a8b4aeace0
Proper fix for rdar://problem/4770604 Thanks to Stuart Hastings!
...
llvm-svn: 30985
2006-10-16 21:00:37 +00:00
e341d60f53
define the DFPBinOp class
...
llvm-svn: 30981
2006-10-16 18:39:22 +00:00
f63752f94b
add the FPBinOp class
...
llvm-svn: 30980
2006-10-16 18:32:36 +00:00
b23dc14135
define the Addr1BinOp class
...
llvm-svn: 30979
2006-10-16 18:18:14 +00:00
203922d083
define the IntBinOp class and use it to implement the multiply instructions
...
llvm-svn: 30978
2006-10-16 17:57:20 +00:00
c4abf8dc5b
fix assembly syntax
...
llvm-svn: 30977
2006-10-16 17:38:12 +00:00
677ee8390d
implement LDRB, LDRSB, LDRH and LDRSH
...
llvm-svn: 30976
2006-10-16 17:17:22 +00:00
595dc4c884
implement smull and umull
...
llvm-svn: 30975
2006-10-16 16:33:29 +00:00
949bcc94ea
Avoid getting into an infinite loop when -disable-x86-shuffle-opti is specified.
...
llvm-svn: 30974
2006-10-16 06:36:00 +00:00
ff1a712794
SelectScalarSSELoad should call CanBeFoldedBy as well.
...
llvm-svn: 30973
2006-10-16 06:34:55 +00:00
34e051d537
Align stack size to DWORD boundary
...
llvm-svn: 30964
2006-10-14 20:53:35 +00:00
2b7f635951
expand ISD::BRCOND
...
llvm-svn: 30963
2006-10-14 17:59:54 +00:00
4c1baf1528
fix some fp condition codes
...
use non trapping comparison instructions
llvm-svn: 30962
2006-10-14 13:42:53 +00:00
b86375cfd0
Corrected load folding check. We need to start from the root of the sub-dag
...
being matched and ensure there isn't a non-direct path to the load (i.e. a
path that goes out of the sub-dag.)
llvm-svn: 30958
2006-10-14 08:33:25 +00:00
a47294ed7a
implement branch inspection/modification methods.
...
llvm-svn: 30946
2006-10-13 21:21:17 +00:00
ab51cf2e78
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
...
llvm-svn: 30945
2006-10-13 21:14:26 +00:00
63007919dc
remove some dead code
...
llvm-svn: 30938
2006-10-13 20:40:42 +00:00
be131662c3
add note
...
llvm-svn: 30937
2006-10-13 20:20:58 +00:00
cf56917053
set isBarrier correctly
...
llvm-svn: 30936
2006-10-13 19:10:34 +00:00
4dc4f30a48
Correctly handle instruction separators.
...
llvm-svn: 30935
2006-10-13 17:56:02 +00:00
95129a7f22
Expose method and ivars for measuring inline asm length properly.
...
llvm-svn: 30934
2006-10-13 17:50:07 +00:00
5ab3166f74
add FNEGS and FNEGD
...
llvm-svn: 30932
2006-10-13 17:37:35 +00:00
d6050c3149
add SBCS and SUBS
...
llvm-svn: 30930
2006-10-13 17:19:20 +00:00
79d9807c87
implement calls to functions that return long
...
llvm-svn: 30929
2006-10-13 16:47:22 +00:00
3874a168d0
implement unordered floating point compares
...
llvm-svn: 30928
2006-10-13 13:14:59 +00:00
03fda13dbb
add a note
...
llvm-svn: 30921
2006-10-12 22:01:26 +00:00
a7956d2894
Doh. This wasn't causing problems by luck.
...
llvm-svn: 30914
2006-10-12 19:13:59 +00:00
694810c227
Some X86ISD::CMP were created with wrong ValueType's.
...
llvm-svn: 30913
2006-10-12 19:12:56 +00:00
8c9422c4b8
mark call adjustments as modifying the SP
...
llvm-svn: 30911
2006-10-12 18:00:26 +00:00
0e0ee36f45
adjcallstack up/down clobbers the sp
...
llvm-svn: 30910
2006-10-12 18:00:14 +00:00
d376e9f4ac
adjcallstackup/down clobbers the stack pointer
...
llvm-svn: 30909
2006-10-12 17:57:58 +00:00
7374bc0577
mark adjcallstack up/down as clobbering and using the SP
...
llvm-svn: 30908
2006-10-12 17:56:34 +00:00
adcaf294d7
Move the Imp tblgen class from the X86 backend to common code.
...
llvm-svn: 30907
2006-10-12 17:49:27 +00:00
b5cda3daa9
Mark ADJCALLSTACKUP/DOWN as clobbering ESP so that virtregmap will notice
...
that it can't assume ESP is unmodified across the instrs.
llvm-svn: 30905
2006-10-12 17:42:56 +00:00
40ec2bebf9
fix compilation failure of smg2000
...
llvm-svn: 30900
2006-10-12 03:55:48 +00:00
d5fcfaa6da
Fold "zero extending vector loads" now that evan added the chain manip stuff.
...
This compiles both tests in X86/vec_ss_load_fold.ll into:
_test1:
movss 4(%esp), %xmm0
subss LCPI1_0, %xmm0
mulss LCPI1_1, %xmm0
minss LCPI1_2, %xmm0
xorps %xmm1, %xmm1
maxss %xmm1, %xmm0
cvttss2si %xmm0, %eax
andl $65535, %eax
ret
instead of:
_test1:
movss LCPI1_0, %xmm0
movss 4(%esp), %xmm1
subss %xmm0, %xmm1
movss LCPI1_1, %xmm0
mulss %xmm0, %xmm1
movss LCPI1_2, %xmm0
minss %xmm0, %xmm1
xorps %xmm0, %xmm0
maxss %xmm0, %xmm1
cvttss2si %xmm1, %eax
andl $65535, %eax
ret
llvm-svn: 30894
2006-10-11 22:09:58 +00:00
4090dc4703
ComplexPatterns sse_load_f32 and sse_load_f64 returns in / out chain operands.
...
llvm-svn: 30892
2006-10-11 21:06:01 +00:00
577ef7694e
Add properties to ComplexPattern.
...
llvm-svn: 30891
2006-10-11 21:03:53 +00:00
fa8cbfd8e8
Reduce the amount of state in the lowering code and drop old pattern ISel functions
...
llvm-svn: 30881
2006-10-11 16:24:51 +00:00
d35734bd1f
Naming consistency.
...
llvm-svn: 30878
2006-10-11 07:10:22 +00:00
6487854b3f
Use cute tblgen tricks to make zap handling more powerful. Specifically,
...
when the dag combiner simplifies an and mask, notice this and allow those bits
to be missing from the zap mask.
This compiles Alpha/zapnot4.ll into:
sll $16,3,$0
zapnot $0,3,$0
ret $31,($26),1
instead of:
ldah $0,1($31)
lda $0,-8($0)
sll $16,3,$1
and $1,$0,$0
ret $31,($26),1
It would be *really* nice to replace the hunk of code in the
AlphaISelDAGToDAG.cpp file that matches (and (srl (x, C), c2) into
(SRL (ZAPNOTi)) with a similar pattern, but I've spent enough time poking
at alpha. Make andrew will do this.
llvm-svn: 30875
2006-10-11 05:13:56 +00:00
a6bbf33cbf
Jimptables working again on alpha.
...
As a bonus, use the GOT node instead of the AlphaISD::GOT for internal stuff.
llvm-svn: 30873
2006-10-11 04:29:42 +00:00
9f86f7c2ab
Remove dead/redundant instructions. These are handled by ZAPNOTi
...
llvm-svn: 30872
2006-10-11 04:12:39 +00:00
4a57e2a6ed
This entry is done. switched to the gcc way of doing things.
...
llvm-svn: 30867
2006-10-11 01:48:03 +00:00
3d74556d74
This has apparently been fixed
...
llvm-svn: 30864
2006-10-11 01:44:46 +00:00
8429e1f6c3
uint <-> double conversion
...
llvm-svn: 30862
2006-10-10 20:38:57 +00:00
b5f1ff336a
add fp sub
...
llvm-svn: 30859
2006-10-10 19:35:01 +00:00
57d109fb08
add double <-> int conversion
...
llvm-svn: 30858
2006-10-10 18:55:14 +00:00
d1a4ea41c9
compare doubles
...
llvm-svn: 30856
2006-10-10 16:33:47 +00:00
d15c892433
initial support for fp compares. Unordered compares not implemented yet
...
llvm-svn: 30854
2006-10-10 12:56:00 +00:00
61b8b43bbe
More isel time load folding checking for nodes that produce flag values.
...
See comment in CanBeFoldedBy() for detailed explanation.
llvm-svn: 30851
2006-10-10 01:46:56 +00:00
57ccb6d372
Don't go too crazy with these AddComplexity. Try matching shufps with load
...
folding first.
llvm-svn: 30848
2006-10-09 21:42:15 +00:00
e646abb7b6
Don't convert to MOVLP if using shufps etc. may allow load folding.
...
llvm-svn: 30847
2006-10-09 21:39:25 +00:00
e71fe34d75
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
...
llvm-svn: 30844
2006-10-09 20:57:25 +00:00
9e29ec371a
add float -> double and double -> float conversion
...
llvm-svn: 30835
2006-10-09 17:50:29 +00:00
396b4a6b7b
add ADDS and ADCS
...
llvm-svn: 30830
2006-10-09 17:18:28 +00:00
e4c3276afc
expand ISD::SELECT
...
llvm-svn: 30829
2006-10-09 16:28:33 +00:00
c154dacb2f
add a note
...
llvm-svn: 30828
2006-10-09 14:18:33 +00:00
41730922bb
expand ISD::EXTLOAD
...
llvm-svn: 30827
2006-10-09 14:13:40 +00:00
78d6c2bf59
most ARM targets are little endian
...
llvm-svn: 30826
2006-10-09 14:12:15 +00:00
398195ebbe
completely disable folding of loads into scalar sse instructions and provide
...
a framework for doing it right. This fixes
CodeGen/X86/2006-10-07-ScalarSSEMiscompile.ll.
Once X86DAGToDAGISel::SelectScalarSSELoad is implemented right, this task
will be done.
llvm-svn: 30817
2006-10-07 21:55:32 +00:00
942009fee5
convert packed FP add/sub/mul/div to use a multiclass.
...
llvm-svn: 30815
2006-10-07 21:17:13 +00:00
4005f4e49c
one multiclass now defines all 8 variants of binary-scalar-sse-fp operations.
...
llvm-svn: 30814
2006-10-07 20:55:57 +00:00
6eaee2c8e3
Switch ADD/MUL/DIV/SUB scalarsse fp ops to a multiclass
...
llvm-svn: 30813
2006-10-07 20:35:44 +00:00
c8c6441821
Random acts of shrinkage
...
llvm-svn: 30812
2006-10-07 19:49:05 +00:00
b5df7e554d
Convert pand/por/pxor to use multiclass
...
llvm-svn: 30811
2006-10-07 19:37:30 +00:00
6138cba5f1
Convert some more instructions over to use a new multiclass.
...
Fix a bug where the asmstring for PSUBQrm was wrong.
llvm-svn: 30810
2006-10-07 19:34:33 +00:00
662ba43f08
Fix a bug where PADDQrm printed paddd instead of paddq.
...
llvm-svn: 30809
2006-10-07 19:15:46 +00:00
29c62a3c88
Add multiclass for SSE2 instructions that correspond to simple binops.
...
llvm-svn: 30808
2006-10-07 19:14:49 +00:00
e0928d9d7b
rename:
...
PDI_binop_rm -> PDI_binop_rm_int
PDI_binop_rmi -> PDI_binop_rmi_int
to make it clear that these are for use with intrinsics.
llvm-svn: 30807
2006-10-07 19:02:31 +00:00
489b63089d
Convert saturating PADD/PSUB's to use a multiclass
...
llvm-svn: 30806
2006-10-07 18:48:46 +00:00
fa2ce8824d
Convert PAVG*, PMADDWD, and PMUL* to use multiclasses.
...
llvm-svn: 30805
2006-10-07 18:39:00 +00:00
cab92e4c0c
Fix typo in packsswb instr definition, where the load had the wrong type.
...
This allows us to use the multiclass for other packs.
llvm-svn: 30804
2006-10-07 18:23:58 +00:00
b50938866b
implement FUITOS and FUITOD
...
llvm-svn: 30803
2006-10-07 14:24:52 +00:00
58c368bc4f
implement FLDD
...
llvm-svn: 30802
2006-10-07 14:03:39 +00:00
40f5dd27f0
implement fadds, faddd, fmuls and fmuld
...
llvm-svn: 30801
2006-10-07 13:46:42 +00:00
e746a9cd6a
handle pmin/pmax with multiclasses
...
llvm-svn: 30800
2006-10-07 07:49:33 +00:00
b14e6a0f8c
simplify pack and shift intrinsics with multiclasses
...
llvm-svn: 30797
2006-10-07 07:06:17 +00:00
521fc4e33f
Use a multiclass to simplify 'SSE2 Integer comparison'
...
llvm-svn: 30796
2006-10-07 06:47:08 +00:00
c6138cec61
move class defns close to uses to make it easier to read
...
llvm-svn: 30795
2006-10-07 06:33:36 +00:00
87e692323c
simplify horizontal op definitions
...
llvm-svn: 30794
2006-10-07 06:31:41 +00:00
3e9fc37458
remove more unneeded type info
...
llvm-svn: 30793
2006-10-07 06:27:03 +00:00
807be0a715
remove unneeded definitions and type info
...
llvm-svn: 30792
2006-10-07 06:19:41 +00:00
5b1358a8eb
remove some unneeded type info
...
llvm-svn: 30791
2006-10-07 06:17:43 +00:00
3414c022af
simplify patterns by merging in operand info
...
llvm-svn: 30790
2006-10-07 05:50:25 +00:00
ca21ce5f08
Factor operands into packed unary classes
...
llvm-svn: 30789
2006-10-07 05:47:20 +00:00
0052c3ff5b
remove dead/duplicate instructions
...
llvm-svn: 30788
2006-10-07 05:41:52 +00:00
904c6e9c92
Pull operand info up into parent class for scalar sse intrinsics.
...
llvm-svn: 30787
2006-10-07 05:26:13 +00:00
e698c90ee9
convert the sole sd unary intrinsic to a multiclass for consistency
...
llvm-svn: 30786
2006-10-07 05:19:31 +00:00
2bb2f050f5
pull operand string into the multiclass
...
llvm-svn: 30785
2006-10-07 05:13:26 +00:00
069679c7b6
Remove RSQRTSS[rm] RCPSS[rm], which are dead.
...
Introduce SS_IntUnary, a multiclass to replace SS_Int[rm].
llvm-svn: 30784
2006-10-07 05:09:48 +00:00
f13a7b376c
eliminate redundancy
...
llvm-svn: 30783
2006-10-07 04:52:09 +00:00
dc3064e223
Set the jt section
...
llvm-svn: 30781
2006-10-06 22:52:33 +00:00
21fa769867
Alpha uses a got
...
llvm-svn: 30778
2006-10-06 22:46:51 +00:00
aa2a12f1a2
add optional input flag to FMRRD
...
llvm-svn: 30774
2006-10-06 20:33:26 +00:00
671f25281d
add support for calling functions that return double
...
llvm-svn: 30771
2006-10-06 19:10:05 +00:00
5fe9680253
80 col violation.
...
llvm-svn: 30770
2006-10-06 18:57:51 +00:00
2421a179e4
ugly codegen
...
llvm-svn: 30769
2006-10-06 17:39:34 +00:00
ef01656ea4
fix some bugs affecting functions with no arguments
...
llvm-svn: 30767
2006-10-06 17:26:30 +00:00
6024ea8383
fix the stack alignment
...
llvm-svn: 30766
2006-10-06 14:29:47 +00:00
5fe7909e18
add support for calling functions that have double arguments
...
llvm-svn: 30765
2006-10-06 12:50:22 +00:00
ff1beda569
Still need to support -mcpu=<> or cross compilation will fail. Doh.
...
llvm-svn: 30764
2006-10-06 09:17:41 +00:00
9274f72e58
Do away with CPU feature list. Just use CPUID to detect MMX, SSE, SSE2, SSE3, and 64-bit support.
...
llvm-svn: 30763
2006-10-06 08:21:07 +00:00
4c1a804a5b
It appears the inline asm in GetCpuIDAndInfo() may clobbers some registers if it isn't inlined (at < -O3). Force it to be inlined.
...
llvm-svn: 30762
2006-10-06 07:50:56 +00:00
df9ac47e5e
Make use of getStore().
...
llvm-svn: 30759
2006-10-05 23:01:46 +00:00
decfeca52d
use a const ref for passing the vector to ArgumentLayout
...
llvm-svn: 30756
2006-10-05 17:46:48 +00:00
e04df41ca2
implement a ArgumentLayout class to factor code common to LowerFORMAL_ARGUMENTS and LowerCALL
...
implement FMDRR
add support for f64 function arguments
llvm-svn: 30754
2006-10-05 16:48:49 +00:00
f2ef243580
Lower some min/max idioms to minss/maxss when unsafe fp math is enabled.
...
llvm-svn: 30748
2006-10-05 04:11:26 +00:00
8cfd10eff3
Don't bother setting JumpTableTextSection, it is about to disappear
...
llvm-svn: 30745
2006-10-05 03:13:59 +00:00
a6a570e02f
Pass the MachineFunction into EmitJumpTableInfo.
...
llvm-svn: 30742
2006-10-05 03:01:21 +00:00
38e2c8a0a2
implement and use getSectionForFunction
...
llvm-svn: 30741
2006-10-05 02:51:36 +00:00
4431699187
Use getSectionForFunction.
...
llvm-svn: 30740
2006-10-05 02:49:23 +00:00
d4d255a408
Use getSectionForFunction
...
llvm-svn: 30739
2006-10-05 02:48:40 +00:00
c8c78982d4
use getSectionForFunction to decide which section to emit code into
...
llvm-svn: 30738
2006-10-05 02:47:13 +00:00
b82247b168
Implement getSectionForFunction, use it when printing function body.
...
llvm-svn: 30737
2006-10-05 02:43:52 +00:00
028d663ee6
Move getSectionForFunction to AsmPrinter, change it to return a string.
...
llvm-svn: 30735
2006-10-05 02:42:20 +00:00
0d236450aa
implement DarwinTargetAsmInfo::getSectionForFunction, use it when outputting
...
function bodies
llvm-svn: 30733
2006-10-05 00:35:50 +00:00
afe6d7a179
Give TargetAsmInfo a virtual dtor, add a new getSectionForFunction method.
...
llvm-svn: 30732
2006-10-05 00:35:16 +00:00
41e22a5419
emit jump table before debug info
...
llvm-svn: 30731
2006-10-05 00:26:05 +00:00
aad26a19f0
Always emit the jump table after the function so it's part of the same 'atom'
...
as the function body.
llvm-svn: 30730
2006-10-05 00:24:46 +00:00
8c5766ef3f
Added option -disable-x86-shuffle-opti to disable X86 specific vector shuffle optimizations.
...
llvm-svn: 30723
2006-10-04 18:33:38 +00:00
412aaabcbe
Formating.
...
llvm-svn: 30722
2006-10-04 18:33:00 +00:00
9259b1efb6
Pattern match min/max nodes when we have sse. This implements
...
CodeGen/X86/scalar_sse_minmax.ll
llvm-svn: 30719
2006-10-04 06:57:07 +00:00
3e11d99a0a
add a note :(
...
llvm-svn: 30717
2006-10-04 05:52:13 +00:00
5d9fd977d3
Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
...
extra operand to LOADX to specify the exact value extension type.
llvm-svn: 30714
2006-10-04 00:56:09 +00:00
68d238801c
Implement floating point constants
...
llvm-svn: 30704
2006-10-03 17:27:58 +00:00
f598d73142
Fix PR933 and CodeGen/X86/2006-10-02-BoolRetCrash.ll
...
llvm-svn: 30703
2006-10-03 17:18:42 +00:00
a36e6cf44f
These don't have immediate operands.
...
llvm-svn: 30694
2006-10-03 06:55:11 +00:00
d55c0a41df
fix the names of the 64bit fp register
...
initial support for returning 64bit floating point numbers
llvm-svn: 30692
2006-10-02 19:30:56 +00:00
1212b4d249
Not needed.
...
llvm-svn: 30674
2006-09-29 22:05:10 +00:00
53f78be49e
add floating point registers
...
implement SINT_TO_FP
llvm-svn: 30673
2006-09-29 21:20:16 +00:00
d9e4bf5285
update comments
...
llvm-svn: 30663
2006-09-28 23:33:12 +00:00
d32cb5ee7f
wrap long lines
...
llvm-svn: 30662
2006-09-28 23:32:43 +00:00
0045295c18
Simplify some code, reformat break's
...
llvm-svn: 30660
2006-09-28 23:19:29 +00:00
78370606d0
Shift amounts are always 32-bits, even in 64-bit mode. This fixes
...
CodeGen/PowerPC/2006-09-28-shift_64.ll
llvm-svn: 30652
2006-09-28 20:48:45 +00:00
3cbd1604f8
add a note about a general improvement to the code generator
...
llvm-svn: 30642
2006-09-28 06:01:17 +00:00
fc36039f86
silence warnings in release build
...
llvm-svn: 30631
2006-09-27 18:29:38 +00:00
67f8cc51f4
Use abstract private/comment directives, to increase portability to ppc/linux
...
llvm-svn: 30621
2006-09-27 02:55:21 +00:00
104aa5dbc1
Various random and minor code cleanups.
...
llvm-svn: 30608
2006-09-26 03:57:53 +00:00
ad4e7eb59e
Compile:
...
int x __attribute__((used));
to:
.data
.comm _x,4 ; 'x'
.no_dead_strip _x
on both x86 and ppc darwin targets.
llvm-svn: 30605
2006-09-26 03:39:53 +00:00
66af390631
Add support for targets that want to do something with the llvm.used list,
...
because they have an aggressive linker that does dead code stripping.
llvm-svn: 30604
2006-09-26 03:38:18 +00:00
f11327daab
more notes
...
llvm-svn: 30598
2006-09-25 17:12:14 +00:00
5e2bacd6be
Fix jump tables to match gcc (and the ABI and whatnot)
...
llvm-svn: 30594
2006-09-24 19:46:56 +00:00
783a4a9d86
Add support for other relocation bases to jump tables, as well as custom asm directives
...
llvm-svn: 30593
2006-09-24 19:45:58 +00:00
68324f8f85
jump table note
...
llvm-svn: 30591
2006-09-24 13:13:10 +00:00
1da0ab2f58
Delete dead code; fix 80 col violations.
...
llvm-svn: 30583
2006-09-22 21:43:59 +00:00
72d4c070c0
add a note
...
llvm-svn: 30581
2006-09-22 11:36:17 +00:00
d31efd190f
Fold AND and ROTL more often
...
llvm-svn: 30577
2006-09-22 05:01:56 +00:00
7b700e517a
more condition codes
...
llvm-svn: 30567
2006-09-21 13:06:26 +00:00
0c71a5adc8
if a constant can't be an immediate, add it to the constant pool
...
llvm-svn: 30566
2006-09-21 11:29:52 +00:00
08a8ccaaf1
implemented
...
llvm-svn: 30559
2006-09-21 06:14:54 +00:00
1c18c0db79
Fit in 80-cols
...
llvm-svn: 30556
2006-09-21 05:46:00 +00:00
c68bbef874
Fix compile error.
...
llvm-svn: 30553
2006-09-21 02:08:31 +00:00
3c5b3df6a0
Adding codegeneration for StdCall & FastCall calling conventions
...
llvm-svn: 30549
2006-09-20 22:03:51 +00:00
ccdaecc448
Account for pseudo-ops correctly
...
llvm-svn: 30548
2006-09-20 20:08:52 +00:00
a81a75c390
The DarwinAsmPrinter need not check for isDarwin. createPPCAsmPrinterPass
...
should create the right asmprinter subclass.
llvm-svn: 30542
2006-09-20 17:12:19 +00:00
8597a2fc4e
Wrap some darwin'isms with isDarwin checks.
...
llvm-svn: 30541
2006-09-20 17:07:15 +00:00
f007f21c8a
catch constants more often
...
llvm-svn: 30534
2006-09-20 15:05:49 +00:00
97a4e99aff
clarify with test case
...
llvm-svn: 30531
2006-09-20 14:48:00 +00:00
e2d138a462
Add Note
...
llvm-svn: 30530
2006-09-20 14:40:01 +00:00
fba9e8f422
item done
...
llvm-svn: 30518
2006-09-20 06:41:56 +00:00
27d8985a71
add a note
...
llvm-svn: 30515
2006-09-20 06:32:10 +00:00
f62f090ea1
This is already done
...
llvm-svn: 30512
2006-09-20 04:59:33 +00:00
da9b1a9322
Improve PPC64 equality comparisons like PPC32 comparisons.
...
llvm-svn: 30510
2006-09-20 04:33:27 +00:00
aa3926b7ea
Two improvements:
...
1. Codegen this comparison:
if (X == 0x8000)
as:
cmplwi cr0, r3, 32768
bne cr0, LBB1_2 ;cond_next
instead of:
lis r2, 0
ori r2, r2, 32768
cmpw cr0, r3, r2
bne cr0, LBB1_2 ;cond_next
2. Codegen this comparison:
if (X == 0x12345678)
as:
xoris r2, r3, 4660
cmplwi cr0, r2, 22136
bne cr0, LBB1_2 ;cond_next
instead of:
lis r2, 4660
ori r2, r2, 22136
cmpw cr0, r3, r2
bne cr0, LBB1_2 ;cond_next
llvm-svn: 30509
2006-09-20 04:25:47 +00:00
ab33d350a7
Add a note that we should match rlwnm better
...
llvm-svn: 30508
2006-09-20 03:59:25 +00:00
601b86513d
Legalize is no longer limited to cleverness with just constant shift amounts.
...
Allow it to be clever when possible and fall back to the gross code when needed.
This allows us to compile:
long long foo1(long long X, int C) {
return X << (C|32);
}
long long foo2(long long X, int C) {
return X << (C&~32);
}
to:
_foo1:
rlwinm r2, r5, 0, 27, 31
slw r3, r4, r2
li r4, 0
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
slw r3, r3, r2
srw r5, r4, r5
or r3, r3, r5
slw r4, r4, r2
blr
instead of:
_foo1:
ori r2, r5, 32
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
llvm-svn: 30507
2006-09-20 03:47:40 +00:00
fa7217f970
fix header
...
add comments
untabify
llvm-svn: 30486
2006-09-19 16:41:40 +00:00
f7d4a9900c
Implement a MachineFunctionPass to fix the mul instruction
...
llvm-svn: 30485
2006-09-19 15:49:25 +00:00
b94df039c0
item done
...
llvm-svn: 30483
2006-09-19 06:19:03 +00:00
3c48ea54ee
Fold the PPCISD shifts when presented with 0 inputs. This occurs for code
...
like:
long long test(long long X, int Y) {
return 1ULL << Y;
}
long long test2(long long X, int Y) {
return -1LL << Y;
}
which we used to compile to:
_test:
li r2, 1
subfic r3, r5, 32
li r4, 0
addi r6, r5, -32
srw r3, r2, r3
slw r4, r4, r5
slw r6, r2, r6
or r3, r4, r3
slw r4, r2, r5
or r3, r3, r6
blr
_test2:
li r2, -1
subfic r3, r5, 32
addi r6, r5, -32
srw r3, r2, r3
slw r4, r2, r5
slw r2, r2, r6
or r3, r4, r3
or r3, r3, r2
blr
Now we produce:
_test:
li r2, 1
addi r3, r5, -32
subfic r4, r5, 32
slw r3, r2, r3
srw r4, r2, r4
or r3, r4, r3
slw r4, r2, r5
blr
_test2:
li r2, -1
subfic r3, r5, 32
addi r6, r5, -32
srw r3, r2, r3
slw r4, r2, r5
slw r2, r2, r6
or r3, r4, r3
or r3, r3, r2
blr
llvm-svn: 30479
2006-09-19 05:22:59 +00:00
f23e3bfcb2
A pass to remove the worst of the replay trap offenders, and as a bonus, align basic blocks when it is free to do so
...
llvm-svn: 30467
2006-09-18 19:44:29 +00:00
3aa3ad780e
Jump tables on Alpha
...
llvm-svn: 30463
2006-09-18 18:01:03 +00:00
523dbc5c19
add a note. Our 64-bit shifts are ~30% slower than gcc's
...
llvm-svn: 30457
2006-09-18 05:36:54 +00:00
4a13d3b391
This is closer to what we really want.
...
llvm-svn: 30451
2006-09-18 04:54:35 +00:00
6f7072c66a
Added some eye-candy for Subtarget type checking
...
Added X86 StdCall & FastCall calling conventions. Codegen will follow.
llvm-svn: 30446
2006-09-17 20:25:45 +00:00
0ab01ff6e2
Small fixes for supporting dll* linkage types
...
llvm-svn: 30441
2006-09-17 13:06:18 +00:00
f7e3478745
add a note noticed through source inspection
...
llvm-svn: 30418
2006-09-16 23:57:51 +00:00
63b113f68c
add a note
...
llvm-svn: 30406
2006-09-16 03:30:19 +00:00
c9dc375d3e
add a nate note
...
llvm-svn: 30399
2006-09-15 20:31:36 +00:00
f8464da015
Remove a unnecessary check.
...
llvm-svn: 30382
2006-09-14 23:55:02 +00:00
2aa98e0363
add a note
...
llvm-svn: 30377
2006-09-14 20:56:30 +00:00
d61d39ec53
Adding dllimport, dllexport and external weak linkage types.
...
DLL* linkages got full (I hope) codegeneration support in C & both x86
assembler backends.
External weak linkage added for future use, we don't provide any
codegeneration, etc. support for it.
llvm-svn: 30374
2006-09-14 18:23:27 +00:00
1463377ddb
add note about switch lowering
...
llvm-svn: 30308
2006-09-13 23:37:16 +00:00
92e5113d48
Skip over first operand when determining REX prefix for two-address code.
...
llvm-svn: 30300
2006-09-13 19:07:28 +00:00
971e33930d
Turn X < 0 -> TEST X,X js
...
llvm-svn: 30294
2006-09-13 17:04:54 +00:00
0c9ae46c5f
The sense of this branch was inverted :(
...
llvm-svn: 30293
2006-09-13 16:56:12 +00:00
3130a756ef
add shifts to addressing mode 1
...
llvm-svn: 30291
2006-09-13 12:09:43 +00:00
706dd3e0d4
Fix a regression in the 32-bit port from the 64-bit port landing.
...
We now compile CodeGen/X86/lea-2.ll into:
_test:
movl 4(%esp), %eax
movl 8(%esp), %ecx
leal -5(%ecx,%eax,4), %eax
ret
instead of:
_test:
movl 4(%esp), %eax
leal (,%eax,4), %eax
addl 8(%esp), %eax
addl $4294967291, %eax
ret
llvm-svn: 30288
2006-09-13 04:45:25 +00:00
e413fea6ac
new note
...
llvm-svn: 30286
2006-09-13 04:19:50 +00:00
3496710f25
new note
...
llvm-svn: 30285
2006-09-13 03:54:54 +00:00
7a627676be
Compile X > -1 -> text X,X; js dest
...
This implements CodeGen/X86/jump_sign.ll.
llvm-svn: 30283
2006-09-13 03:22:10 +00:00
9a083a4121
Reflects MachineConstantPoolEntry changes.
...
llvm-svn: 30279
2006-09-12 21:04:05 +00:00
cfb2c32724
add a note
...
llvm-svn: 30271
2006-09-12 06:36:01 +00:00
8b4de218d9
Testcase noticed from PR906
...
llvm-svn: 30269
2006-09-11 23:00:56 +00:00
6e7286f72a
add compilable testcase
...
llvm-svn: 30268
2006-09-11 22:57:51 +00:00
c7829d62c0
implement SRL and MUL
...
llvm-svn: 30262
2006-09-11 19:24:19 +00:00
bccf9c2f1b
add the correct fallback for ARMDAGToDAGISel::SelectAddrMode1
...
llvm-svn: 30261
2006-09-11 19:23:32 +00:00
e45a79a9e2
partial implementation of the ARM Addressing Mode 1
...
llvm-svn: 30252
2006-09-11 17:25:40 +00:00
ecb0d686f8
call AsmPrinter::doInitialization in ARMAsmPrinter::doInitialization
...
llvm-svn: 30246
2006-09-11 12:49:38 +00:00
21a75acc3e
Updates.
...
llvm-svn: 30245
2006-09-11 05:35:17 +00:00
9e77d9a96b
Update README file.
...
llvm-svn: 30244
2006-09-11 05:25:15 +00:00
4259a0f654
X86ISD::CMP now produces a chain as well as a flag. Make that the chain
...
operand of a conditional branch to allow load folding into CMP / TEST
instructions.
llvm-svn: 30241
2006-09-11 02:19:56 +00:00
a0d95a8da9
Behold, more work on relocations. Things are looking pretty good now.
...
llvm-svn: 30240
2006-09-10 23:03:44 +00:00
fbee8bfe48
Removed unnecessary Mangler creation.
...
llvm-svn: 30239
2006-09-10 21:17:03 +00:00
fdb3a75942
Add cbe support for powi
...
llvm-svn: 30226
2006-09-09 06:17:12 +00:00
69df6132d7
First pass at supporting relocations. Relocations are written correctly to
...
the file now, however the relocated address is currently wrong. Fixing
that will require some deep pondering.
llvm-svn: 30207
2006-09-08 22:42:09 +00:00
de33f66286
Fixed a FuseTwoAddrInst() bug: consider GlobalAddress and JumpTableIndex
...
in addition to immediate operands.
llvm-svn: 30205
2006-09-08 21:08:13 +00:00
d11fb5d13b
implement shl and sra
...
llvm-svn: 30191
2006-09-08 17:36:23 +00:00
6c003a7c2d
Use __USER_LABEL_PREFIX__ to get the prefix added by the current host.
...
llvm-svn: 30190
2006-09-08 17:03:56 +00:00
4443c7d60a
add the eor (xor) instruction
...
llvm-svn: 30189
2006-09-08 16:59:47 +00:00
177405376c
Missing tab
...
llvm-svn: 30188
2006-09-08 13:06:56 +00:00
778769aafb
implement unconditional branches
...
fix select.ll
llvm-svn: 30186
2006-09-08 12:47:03 +00:00
7348403d42
Remove TEST64mr. It's same as TEST64rm since and is commutative.
...
llvm-svn: 30178
2006-09-08 06:56:55 +00:00
11b0a5dbd4
Committing X86-64 support.
...
llvm-svn: 30177
2006-09-08 06:48:29 +00:00
c9db83306f
We actually do support object file writing, so don't return true (error)
...
llvm-svn: 30173
2006-09-08 03:42:15 +00:00
89c5d04b9b
- Identify a vector_shuffle that can be turned into an undef, e.g.
...
shuffle V1, <undef>, <undef, undef, 4, 5>
- Fix some suspicious logic into LowerVectorShuffle that cause less than
optimal code by failing to identify MOVL (move to lowest element of a
vector).
llvm-svn: 30171
2006-09-08 01:50:06 +00:00
ae92ce8798
1. Remove condition on delete.
...
2. Protect and outline createTargetAsmInfo.
3. Misc. kruft.
llvm-svn: 30169
2006-09-07 23:39:26 +00:00
2785d55446
add a new value for the command line optn
...
llvm-svn: 30165
2006-09-07 22:32:28 +00:00
b9e0a9e82f
Fix a cross-build issue. The asmsyntax shouldn't be affected by the build
...
host, it should be affected by the target. Allow the command line option to
override in either case.
llvm-svn: 30164
2006-09-07 22:29:41 +00:00
261779bb45
Make target asm info a property of the target machine.
...
llvm-svn: 30162
2006-09-07 22:06:40 +00:00
0e83541f8b
Break out target asm info into separate files.
...
llvm-svn: 30161
2006-09-07 22:05:02 +00:00
dc4ff5311f
Eliminate X86ISD::TEST, using X86ISD::CMP instead. Match X86ISD::CMP patterns
...
using test, which provides nice simplifications like:
- movl %edi, %ecx
- andl $2, %ecx
- cmpl $0, %ecx
+ testl $2, %edi
je LBB1_11 #cond_next90
There are a couple of dagiselemitter deficiencies that this exposes, they will
be handled later.
llvm-svn: 30156
2006-09-07 20:33:45 +00:00
1b7f09cdf7
Some notes on better load folding we could do
...
llvm-svn: 30155
2006-09-07 20:32:01 +00:00
a9411c0977
Consistency.
...
llvm-svn: 30152
2006-09-07 19:03:48 +00:00
c7abe471fe
Make the x86 asm flavor part of the subtarget info.
...
llvm-svn: 30146
2006-09-07 12:23:47 +00:00
7f3f0973e6
Clean up.
...
llvm-svn: 30140
2006-09-07 01:17:57 +00:00
4c7a3fbdea
Watch out for variable_ops instructions.
...
llvm-svn: 30135
2006-09-06 20:32:45 +00:00
ac22e54131
Variable ops instructions may ignore the last few operands for code emission.
...
llvm-svn: 30134
2006-09-06 20:24:14 +00:00
ef94ebb666
Oops - forgot to update banner.
...
llvm-svn: 30131
2006-09-06 19:21:41 +00:00
681ecbb3b3
Separate target specifc asm properties from asm printers.
...
llvm-svn: 30127
2006-09-06 18:35:33 +00:00
a6211dcdad
Separate target specific asm properties from the asm printers.
...
llvm-svn: 30126
2006-09-06 18:34:40 +00:00
abd8bcbe5e
add the orr instruction
...
llvm-svn: 30125
2006-09-06 18:03:12 +00:00
2656932979
Bugfix to work with the two-addr changes that have been made in the tree recently
...
llvm-svn: 30121
2006-09-05 20:27:32 +00:00
7a150d3113
Fix a few dejagnu failures. e.g. fast-cc-merge-stack-adj.ll
...
llvm-svn: 30113
2006-09-05 08:32:49 +00:00
17c28b2e0e
JIT encoding bug.
...
llvm-svn: 30112
2006-09-05 05:59:25 +00:00
e3d2e1e41e
Update the X86 JIT to make it work with the new two-addr changes. This also
...
adds assertions that check to make sure every operand gets emitted.
llvm-svn: 30110
2006-09-05 02:52:35 +00:00
af23f9b5f6
Completely eliminate def&use operands. Now a register operand is EITHER a
...
def operand or a use operand.
llvm-svn: 30109
2006-09-05 02:31:13 +00:00
13a5dcddce
Fix a long-standing wart in the code generator: two-address instruction lowering
...
actually *removes* one of the operands, instead of just assigning both operands
the same register. This make reasoning about instructions unnecessarily complex,
because you need to know if you are before or after register allocation to match
up operand #'s with the target description file.
Changing this also gets rid of a bunch of hacky code in various places.
This patch also includes changes to fold loads into cmp/test instructions in
the X86 backend, along with a significant simplification to the X86 spill
folding code.
llvm-svn: 30108
2006-09-05 02:12:02 +00:00
3852b2ce7e
jmp_bufs are this big on alpha.
...
llvm-svn: 30107
2006-09-05 00:22:25 +00:00
8386105f3f
add support for returning 64bit values
...
llvm-svn: 30103
2006-09-04 19:05:01 +00:00
49c45d3a13
Fix some X86 JIT failures. This should really come from TargetJITInfo.
...
llvm-svn: 30102
2006-09-04 18:48:41 +00:00
cf6749e4c0
add setJumpBufSize() and setJumpBufAlignment() to target-lowering.
...
Call these from your backend to enjoy setjmp/longjmp goodness, see
lib/Target/IA64/IA64ISelLowering.cpp for an example
llvm-svn: 30095
2006-09-04 06:21:35 +00:00
12e97307a1
Completely rearchitect the interface between targets and the pass manager.
...
This pass:
1. Splits TargetMachine into TargetMachine (generic targets, can be implemented
any way, like the CBE) and LLVMTargetMachine (subclass of TM that is used by
things using libcodegen and other support).
2. Instead of having each target fully populate the passmgr for file or JIT
output, move all this to common code, and give targets hooks they can
implement.
3. Commonalize the target population stuff between file emission and JIT
emission.
4. All (native code) codegen stuff now happens in a FunctionPassManager, which
paves the way for "fast -O0" stuff in the CFE later, and now LLC could
lazily stream .bc files from disk to use less memory.
5. There are now many fewer #includes and the targets don't depend on the
scalar xforms or libanalysis anymore (but codegen does).
6. Changing common code generator pass ordering stuff no longer requires
touching all targets.
7. The JIT now has the option of "-fast" codegen or normal optimized codegen,
which is now orthogonal to the fact that JIT'ing is being done.
llvm-svn: 30081
2006-09-04 04:14:57 +00:00
e8ce162969
Add accessor
...
llvm-svn: 30080
2006-09-04 04:08:58 +00:00
2f93c0fd33
remove #include
...
llvm-svn: 30078
2006-09-04 04:06:01 +00:00
0fc4541c67
Simplify target construction.
...
llvm-svn: 30070
2006-09-03 18:44:02 +00:00
5328ba96e1
add the SETULT condition code
...
llvm-svn: 30067
2006-09-03 13:19:16 +00:00
c585b6919b
add more condition codes
...
llvm-svn: 30056
2006-09-02 20:24:25 +00:00
2c4e0f120f
Oops. Bad typo. Without the check of N1.hasOneUse() bad things can happen.
...
Suppose the TokenFactor can reach the Op:
[Load chain]
^
|
[Load]
^ ^
| |
/ \-
/ |
/ [Op]
/ ^ ^
| .. |
| / |
[TokenFactor] |
^ |
| |
\ /
\ /
[Store]
If we move the Load below the TokenFactor, we would have created a cycle in
the DAG.
llvm-svn: 30040
2006-09-01 22:52:28 +00:00
bad9d2ee49
Use a couple of multiclass patterns to factor some integer ops.
...
llvm-svn: 30039
2006-09-01 22:28:02 +00:00
38e6d1d5af
remove a bunch of comments
...
llvm-svn: 30038
2006-09-01 22:16:22 +00:00
6d464146d0
Minor asm fix.
...
llvm-svn: 29965
2006-08-29 22:14:48 +00:00
b28800f4d5
Remove dead code.
...
llvm-svn: 29962
2006-08-29 21:42:58 +00:00
dfb85155dc
Don't performance load/op/store transformation if op produces a floating point
...
or vector result. X86 does not have load/mod/store variants of those
instructions.
llvm-svn: 29957
2006-08-29 18:37:37 +00:00
358b9ed98a
- Enable x86 isel preprocessing by default unless -fast is specified.
...
- Also disable isel load folding if -fast.
llvm-svn: 29956
2006-08-29 18:28:33 +00:00
2eebe8b05e
Handle callee saved registers in dwarf frame info (lead up to exception
...
handling.)
llvm-svn: 29954
2006-08-29 16:24:26 +00:00
82dc16c0a7
Tidy up options.
...
llvm-svn: 29953
2006-08-29 15:13:10 +00:00
c07feb14b0
Avoid making unneeded load/mod/store transformation which can hurt performance.
...
llvm-svn: 29952
2006-08-29 06:44:17 +00:00
18f0329cfc
Make ppc64 jit kinda work right. About 2/3 of Olden passes with this,
...
there are clearly some encoding bugs lurking in there somewhere.
llvm-svn: 29949
2006-08-29 02:30:59 +00:00
00884b51c5
On Mac, print jump table entries after the function to work around a linker issue.
...
llvm-svn: 29946
2006-08-28 22:14:16 +00:00
64a9e28846
Add an optional pass to preprocess the DAG before x86 isel to allow selecting more load/mod/store instructions.
...
llvm-svn: 29943
2006-08-28 20:10:17 +00:00
e7141c8be6
For PR387:
...
Close out this long standing bug by removing the remaining overloaded
virtual functions in LLVM. The -Woverloaded-virtual option is now turned on.
llvm-svn: 29934
2006-08-28 01:02:49 +00:00
3d27be1333
s|llvm/Support/Visibility.h|llvm/Support/Compiler.h|
...
llvm-svn: 29911
2006-08-27 12:54:02 +00:00
c3acfc0b10
Do not use getTargetNode() and SelectNodeTo() which takes more than 3
...
SDOperand arguments. Use the variants which take an array and number instead.
llvm-svn: 29907
2006-08-27 08:14:06 +00:00
4042e871ce
Fix target matching weights, so that ppc-darwin modules are codegen with the
...
ppc target, not the itanium target, when run on an itanium machine.
This should fix the CodeGen/PowerPC regtest failures on itanium.
llvm-svn: 29903
2006-08-26 21:33:05 +00:00
34b70eea5c
SelectNodeTo now returns a SDNode*.
...
llvm-svn: 29901
2006-08-26 08:00:10 +00:00
61413a3d72
Select() no longer require Result operand by reference.
...
llvm-svn: 29898
2006-08-26 05:34:46 +00:00
ab8297f92d
Match tblgen changes.
...
llvm-svn: 29895
2006-08-26 01:07:58 +00:00
2d48722e92
Match tblgen changes; clean up.
...
llvm-svn: 29894
2006-08-26 01:05:16 +00:00
c664efe223
Give a good error message when we try to jit inline asm.
...
llvm-svn: 29891
2006-08-26 00:47:03 +00:00
1b200574ad
Add a comment.
...
llvm-svn: 29889
2006-08-25 23:29:06 +00:00
d7572fb234
Encode pc-relative conditional branch offset as pc+(num of bytes / 4). The
...
asm printer will print it as offset*4. e.g. bne cr0, $+8.
The PPC code emitter was expecting the offset to be number of instructions, not
number of bytes. This fixes a whole bunch of JIT failures.
llvm-svn: 29885
2006-08-25 21:54:44 +00:00
d51ce619c3
Fix some comments.
...
llvm-svn: 29880
2006-08-25 19:40:59 +00:00
98dc23fd1f
use @ for comments
...
store LR in an arbitrary stack slot
add support for writing varargs functions
llvm-svn: 29876
2006-08-25 17:55:16 +00:00
ac40a81253
We compile this into:
...
_swap_16:
slwi r2, r3, 24
rlwimi r2, r3, 8, 8, 15
srwi r3, r2, 16
blr
now.
llvm-svn: 29864
2006-08-24 23:06:02 +00:00
fb6bc15d5d
Owen implemented this.
...
llvm-svn: 29863
2006-08-24 23:03:33 +00:00
29e4875f57
add the "eq" condition code
...
implement a movcond instruction
llvm-svn: 29857
2006-08-24 17:19:08 +00:00
fe03fe9bf4
create a generic bcond instruction that has a conditional code argument
...
llvm-svn: 29856
2006-08-24 16:13:15 +00:00
e08b9853cc
initial support for branches
...
llvm-svn: 29854
2006-08-24 13:45:55 +00:00
3cb3921a60
Initial checkin of the Mach-O emitter. There's plenty of fixmes, but it
...
does emit linkable .o files in very simple cases.
llvm-svn: 29850
2006-08-23 21:08:52 +00:00
ea500426d6
add a README.txt
...
llvm-svn: 29814
2006-08-22 12:22:46 +00:00
d0dee77718
initial support for select
...
llvm-svn: 29802
2006-08-21 22:00:32 +00:00
9d77f9fd24
add the and instruction
...
llvm-svn: 29793
2006-08-21 13:58:59 +00:00
8a675a5d09
call computeRegisterProperties
...
llvm-svn: 29780
2006-08-20 01:49:49 +00:00
60f1eecd3a
Constify some methods. Patch provided by Anton Vayvod, thanks!
...
llvm-svn: 29756
2006-08-17 22:00:08 +00:00
162f2d5d4c
Revert this patch, the front-end has been fixed to make it unneccesary.
...
llvm-svn: 29752
2006-08-17 18:43:24 +00:00
dfb3f0591d
'g' is handled by the front-end.
...
llvm-svn: 29751
2006-08-17 18:12:28 +00:00
4a063c5ffb
Fix handling of 'g'. Closes 883
...
llvm-svn: 29750
2006-08-17 17:50:12 +00:00
c3ed77e1b9
add a "load effective address"
...
llvm-svn: 29748
2006-08-17 17:09:40 +00:00
1c3210d08d
Add the 'c' constraint as needed by the linux kernel
...
llvm-svn: 29747
2006-08-17 16:07:50 +00:00
fc60fb974c
Add support for S and D constraints, as needed to compile the linux kernel.
...
llvm-svn: 29746
2006-08-17 15:35:43 +00:00
29ab7c42a8
Doh. Incorrectly inverted condition. Also add a isOnlyUse check to match tablegen.
...
llvm-svn: 29741
2006-08-16 23:59:00 +00:00
bf8e751488
Declare the callee saved regs
...
Remove the hard coded store and load of the link register
Implement ARMFrameInfo
llvm-svn: 29727
2006-08-16 14:43:33 +00:00
63d178f473
SelectNodeTo() may return a SDOperand that is different from the input.
...
llvm-svn: 29726
2006-08-16 07:30:09 +00:00
f2a7d5768a
RET_FLAG has an optional input flag, but it does not produce a flag result.
...
llvm-svn: 29725
2006-08-16 07:28:58 +00:00
08a5f38c5c
add a note
...
llvm-svn: 29722
2006-08-16 02:47:44 +00:00
bc485fdc4c
Fix PowerPC/2006-08-15-SelectionCrash.ll and simplify selection code.
...
llvm-svn: 29715
2006-08-15 23:48:22 +00:00
157971b04a
select code like
...
ldr rx, [ry, #offset]
llvm-svn: 29664
2006-08-14 19:01:24 +00:00
984c1a4a8f
Emit .set directives for jump table entries when possible, which reduces
...
the number of relocations in object files, shrinkifying them.
llvm-svn: 29650
2006-08-12 21:29:52 +00:00
095e4ad2ea
Fix a bug in a recent refactoring that broke a bunch of stuff.
...
llvm-svn: 29649
2006-08-12 07:20:05 +00:00
20b461a97f
eliminate extraneous blank line
...
llvm-svn: 29627
2006-08-11 21:08:16 +00:00
ed728e8dc9
Eliminate use of getNode that takes a vector.
...
llvm-svn: 29614
2006-08-11 17:38:39 +00:00
c62914880f
elimiante use of getNode that takes vector of operands.
...
llvm-svn: 29612
2006-08-11 17:22:35 +00:00
56565b5cb9
eliminate use of getNode that takes vector of operands.
...
llvm-svn: 29611
2006-08-11 17:21:12 +00:00
2aa76cf371
eliminate use of getNode that takes vector<SDOperand>. Wrap a really long line.
...
llvm-svn: 29610
2006-08-11 17:19:54 +00:00
d66f14e846
Convert vectors to fixed sized arrays and smallvectors. Eliminate use of getNode that takes a vector.
...
llvm-svn: 29609
2006-08-11 17:18:05 +00:00
66f1fbaaad
Fix miscompilation of float vector returns. Compile code to this:
...
_func:
vsldoi v2, v3, v2, 12
vsldoi v2, v2, v2, 4
blr
instead of:
_func:
vsldoi v2, v3, v2, 12
vsldoi v2, v2, v2, 4
*** vor f1, v2, v2
blr
llvm-svn: 29607
2006-08-11 16:47:32 +00:00
bd1c5a8fb8
Match tablegen changes.
...
llvm-svn: 29604
2006-08-11 09:08:15 +00:00
81b645a76b
CALLSEQ_* produces chain even if that's not needed.
...
llvm-svn: 29603
2006-08-11 09:03:33 +00:00
5c68bba085
Convert more calls of getNode() that takes a vector to pass in the start of an array.
...
llvm-svn: 29601
2006-08-11 07:35:45 +00:00
1c41fc9b06
correctly set LocalAreaOffset of TargetFrameInfo
...
llvm-svn: 29589
2006-08-09 17:37:45 +00:00
f5ce475540
fix the spill code
...
llvm-svn: 29583
2006-08-09 16:41:12 +00:00
58159b36a3
fix the loading of the link register in emitepilogue
...
llvm-svn: 29580
2006-08-09 13:15:47 +00:00
8c41f99e6f
change the addressing mode of the str instruction to reg+imm
...
llvm-svn: 29571
2006-08-08 20:35:03 +00:00
39083e7836
initial support for variable number of arguments
...
llvm-svn: 29567
2006-08-08 13:02:29 +00:00
c24a1d3093
Start eliminating temporary vectors used to create DAG nodes. Instead, pass
...
in the start of an array and a count of operands where applicable. In many
cases, the number of operands is known, so this static array can be allocated
on the stack, avoiding the heap. In many other cases, a SmallVector can be
used, which has the same benefit in the common cases.
I updated a lot of code calling getNode that takes a vector, but ran out of
time. The rest of the code should be updated, and these methods should be
removed.
We should also do the same thing to eliminate the methods that take a
vector of MVT::ValueTypes.
It would be extra nice to convert the dagiselemitter to avoid creating vectors
for operands when calling getTargetNode.
llvm-svn: 29566
2006-08-08 02:23:42 +00:00
72bb66a4b8
Eliminate reachability matrix. It has to be calculated before any instruction
...
selection is done. That's rather expensive especially in situations where it
isn't really needed.
Move back to a searching the predecessors, but make use of topological order
to trim the search space.
llvm-svn: 29559
2006-08-08 00:31:00 +00:00
b9d34bd098
Match tablegen isel changes.
...
llvm-svn: 29549
2006-08-07 22:28:20 +00:00
d5e38e017c
Make XMM, FP register dwarf register numbers consistent with gcc.
...
llvm-svn: 29543
2006-08-07 21:02:39 +00:00
2bcb8c0f05
use a 'register pressure reducing' scheduler
...
make sure only one move is used in a hello world
llvm-svn: 29520
2006-08-04 12:48:42 +00:00
e19f6fde2d
Bug fix: always generate a RET_FLAG in LowerRET
...
fixes ret_null.ll and call.ll
llvm-svn: 29519
2006-08-03 22:50:11 +00:00
fef2c5f0a2
remove some more dead sparcv9 support stuff
...
llvm-svn: 29506
2006-08-03 18:55:44 +00:00
682ff0dd15
remove a dead proto
...
llvm-svn: 29505
2006-08-03 18:51:04 +00:00
f2c14591e6
Get darwin intel debugging up and running.
...
llvm-svn: 29504
2006-08-03 17:27:09 +00:00
a94b9e33af
add and use ARMISD::RET_FLAG
...
llvm-svn: 29499
2006-08-03 17:02:20 +00:00
8f585196e1
Reflect change to AssignTopologicalOrder().
...
llvm-svn: 29480
2006-08-02 22:01:32 +00:00
8101dd67d1
Use of vector<bool> causes some horrendous compile time regression (2x)!
...
Looks like libstdc++ implementation does not scale very well. Switch back
to using directly managed arrays.
llvm-svn: 29469
2006-08-02 09:18:33 +00:00
6025c92e50
Update the readme to remove duplicate information and clarify the loop
...
problem.
llvm-svn: 29468
2006-08-02 05:31:20 +00:00
d573cc7938
Disable LSR at -fast
...
llvm-svn: 29467
2006-08-02 05:29:40 +00:00
8b7bd8264b
start comments with #
...
move the constant pool to .text
correctly print loads of labels
mark R0, R1, R2 and R3 as caller save
llvm-svn: 29451
2006-08-01 18:53:10 +00:00
95035cf001
implement LowerConstantPool and LowerGlobalAddress
...
llvm-svn: 29433
2006-08-01 12:58:43 +00:00
45af287957
Factor topological order code to SelectionDAG. Clean up.
...
llvm-svn: 29430
2006-08-01 08:17:22 +00:00
524129dd64
Fix PR850 and CodeGen/X86/2006-07-31-SingleRegClass.ll.
...
The CFE refers to all single-register constraints (like "A") by their 16-bit
name, even though the 8 or 32-bit version of the register may be needed.
The X86 backend should realize what is going on and redecode the name back
to its proper form.
llvm-svn: 29420
2006-07-31 23:26:50 +00:00
7cc2d19fc1
handle GlobalValue::InternalLinkage in doFinalization
...
llvm-svn: 29417
2006-07-31 20:38:13 +00:00
ac8be4338c
Remove a duplicate pattern.
...
llvm-svn: 29414
2006-07-31 18:43:10 +00:00
2af3a67902
Remove a duplicate pattern/
...
llvm-svn: 29413
2006-07-31 18:42:49 +00:00
ebb592be39
Make functions with an "asm" name propagate that asm name into the cbe.c file.
...
This fixes link errors on programs with these on targets with prefixes.
llvm-svn: 29390
2006-07-28 20:58:47 +00:00
8298265042
Fix some ppc64 issues with vector code.
...
llvm-svn: 29384
2006-07-28 16:45:47 +00:00
e8071ecc3b
Can't spell.
...
llvm-svn: 29383
2006-07-28 06:33:41 +00:00
2e94538b8e
Some clean up.
...
llvm-svn: 29382
2006-07-28 06:05:06 +00:00
e2a3f7014d
Rename IsFoldableBy to CanBeFoldedleBy
...
llvm-svn: 29376
2006-07-28 01:03:48 +00:00
11a4d8c2f4
Node selected into address mode cannot be folded.
...
llvm-svn: 29374
2006-07-28 00:49:31 +00:00
b572401bea
Remove InFlightSet hack. No longer needed.
...
llvm-svn: 29373
2006-07-28 00:47:19 +00:00
3b5e0cafd1
Another duh. Determine topological order before any target node is added.
...
llvm-svn: 29371
2006-07-28 00:10:59 +00:00
f38707b8d4
Brain cramp..
...
llvm-svn: 29370
2006-07-27 23:35:40 +00:00
390dd7eb7d
Allocating too large an array for ReachibilityMatrix.
...
llvm-svn: 29367
2006-07-27 22:35:40 +00:00
87585760ab
Calculate the portion of reachbility matrix on demand.
...
llvm-svn: 29366
2006-07-27 22:10:00 +00:00
d6c0c2dfd9
isNonImmUse is replaced by IsFoldableBy
...
llvm-svn: 29365
2006-07-27 21:19:10 +00:00
78bf1074fc
Resolve BB references with relocation.
...
llvm-svn: 29351
2006-07-27 18:21:10 +00:00
7ec7b467df
synchronizeICache removeed from TargetJITInfo.
...
llvm-svn: 29348
2006-07-27 17:33:48 +00:00
691a63d564
Use reachbility information to determine whether a node can be folded into another during isel.
...
llvm-svn: 29346
2006-07-27 16:44:36 +00:00
89e5cbd897
emit global constants
...
llvm-svn: 29344
2006-07-27 11:38:51 +00:00
f300896420
Remove NodeDepth
...
llvm-svn: 29338
2006-07-27 06:40:15 +00:00
85ea83e821
Add some advice
...
llvm-svn: 29324
2006-07-27 04:24:14 +00:00
3b4866e194
Use the predicate.
...
llvm-svn: 29322
2006-07-27 02:05:13 +00:00
787565024a
Support jump tables when in PIC relocation model
...
llvm-svn: 29318
2006-07-27 01:13:04 +00:00
c169b8798f
Prevent creation of MachineDebugInfo for intel unless it is darwin. RC842.
...
llvm-svn: 29317
2006-07-27 01:12:23 +00:00
23a21c19d9
New entry.
...
llvm-svn: 29310
2006-07-26 21:49:52 +00:00
9e56e5c003
Rename RelocModel::PIC to PIC_, to avoid conflicts with -DPIC.
...
llvm-svn: 29307
2006-07-26 21:12:04 +00:00
f6acb34d23
- Refactor the code that resolve basic block references to a TargetJITInfo
...
method.
- Added synchronizeICache() to TargetJITInfo. It is called after each block
of code is emitted to flush the icache. This ensures correct execution
on targets that have separate dcache and icache.
- Added PPC / Mac OS X specific code to do icache flushing.
llvm-svn: 29276
2006-07-25 20:40:54 +00:00
66ed41cac1
Can't commute shufps. The high / low parts elements come from different vectors.
...
llvm-svn: 29275
2006-07-25 20:25:40 +00:00
8902fd702b
implement function calling of functions with up to 4 arguments
...
llvm-svn: 29274
2006-07-25 20:17:20 +00:00
c0577648c0
Done.
...
llvm-svn: 29262
2006-07-21 23:07:23 +00:00
976c93a110
implemented sub
...
correctly update the stack pointer in the prologue and epilogue
llvm-svn: 29244
2006-07-21 12:26:16 +00:00
74065bedf2
This opt is now handled in DAG combine.
...
llvm-svn: 29243
2006-07-21 08:26:46 +00:00
4cf0238720
A splat of a vector constant of all zero or all one is the vector constant.
...
llvm-svn: 29234
2006-07-20 23:09:47 +00:00
f98bc5288e
Missing a space.
...
llvm-svn: 29233
2006-07-20 22:52:28 +00:00
683b966485
Clean up.
...
llvm-svn: 29228
2006-07-20 21:37:39 +00:00
8a881f2309
New entry.
...
llvm-svn: 29215
2006-07-19 21:29:30 +00:00
181fb1c4d7
Do once flag never set to true.
...
llvm-svn: 29214
2006-07-19 19:33:08 +00:00
7c860afec6
Tidy up a few things.
...
llvm-svn: 29213
2006-07-19 19:32:06 +00:00
18debc21db
Reduce size of routine. Shrinks .o by 37%.
...
llvm-svn: 29210
2006-07-19 17:53:32 +00:00
4f8eb5ccaf
bswapped load/store instructions are only availble in indexed addressing form.
...
As such, use xoaddr (indexed only), not xaddr for address selection.
This fixes CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll, a crash compiling lencod.
llvm-svn: 29208
2006-07-19 17:15:36 +00:00
5ba7c23cdd
Bug#834 ICE (crash in code generator?) when building PCH .
...
Missing Darwin check in Intel ATT ASM printer.
llvm-svn: 29204
2006-07-19 11:54:50 +00:00
968a0b0309
Misc. new entry.
...
llvm-svn: 29202
2006-07-19 06:06:24 +00:00
02d8836cd5
INC / DEC instructions have shorter code size than ADD32ri8, etc.
...
llvm-svn: 29194
2006-07-19 00:27:29 +00:00
c767acd25a
Add code size to target instruction use it as the 3rd isel sorting tie-breaker.
...
llvm-svn: 29193
2006-07-19 00:24:41 +00:00
bf3a17cd32
initial prologue and epilogue implementation. Need to define add and sub before finishing it :-)
...
llvm-svn: 29175
2006-07-18 17:00:30 +00:00
b00b6c2e86
Make the implicit def instructions look like other instrs.
...
llvm-svn: 29174
2006-07-18 16:33:26 +00:00
75269be065
skeleton of a lowerCall implementation for ARM
...
llvm-svn: 29159
2006-07-16 01:02:57 +00:00
e1758d4cef
Remove what little AIX support we have. It has never been tested and isn't
...
complete.
llvm-svn: 29156
2006-07-15 01:24:23 +00:00
2e1d01541a
Add an out-of-line virtual method for X86DwarfWriter to give it a home.
...
llvm-svn: 29153
2006-07-14 23:05:05 +00:00
96aecb5d76
Add missing PPC64 extload/truncstores
...
llvm-svn: 29140
2006-07-14 04:42:02 +00:00
950dffaed6
Add a note
...
llvm-svn: 29139
2006-07-14 04:07:29 +00:00
077b86a078
Another fix in the rotate encodings, needed when the first two operands are not
...
the same.
llvm-svn: 29136
2006-07-13 21:52:41 +00:00
b42a945fd2
Print negative immediates as negative values instead of large constants
...
when using the immshifted addressing mode.
llvm-svn: 29130
2006-07-12 23:24:02 +00:00
dd57ac4871
Fix encoding of rotates, such as rldicl
...
llvm-svn: 29128
2006-07-12 22:08:13 +00:00
5b17dee741
Implement PPC64 relocations types
...
llvm-svn: 29125
2006-07-12 21:23:20 +00:00
1ec5e73b32
An overaggressive #ifdef allows a function to fall off the bottom of the
...
function instead of returning a value. This sometimes allowed the ppc32 jit
to be used in 64-bit mode.
llvm-svn: 29123
2006-07-12 20:42:10 +00:00
c8db10725b
Add information preventing several register class constraints from working.
...
This implements PR828 and CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll
llvm-svn: 29118
2006-07-12 16:59:49 +00:00
6e662083d9
The PPC64 JIT needs register numbers to encode instructions.
...
llvm-svn: 29114
2006-07-11 20:53:55 +00:00
d5a086ab12
Emit inc / dec of registers as one byte instruction.
...
llvm-svn: 29110
2006-07-11 19:49:49 +00:00
f7300b2706
It was pointed out that DEBUG() is only available with -debug.
...
llvm-svn: 29106
2006-07-11 18:25:13 +00:00
c3d341ea98
Ensure that dump calls that are associated with asserts are removed from
...
non-debug build.
llvm-svn: 29105
2006-07-11 17:58:07 +00:00
185c5c2bdf
add the memri memory operand
...
this makes it possible for ldr instructions with non-zero immediate
llvm-svn: 29103
2006-07-11 11:36:48 +00:00
298ef37e02
Implement the inline asm 'A' constraint. This implements PR825 and
...
CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll
llvm-svn: 29101
2006-07-11 02:54:03 +00:00
71227c23b1
In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones.
...
llvm-svn: 29096
2006-07-11 00:48:23 +00:00
32860f42bb
New entry.
...
llvm-svn: 29091
2006-07-10 21:42:16 +00:00
79cf9a5342
Fixed stack objects do not specify alignments, but their offsets are known.
...
Use that information when doing the transformation to merge multiple loads
into a 128-bit load.
llvm-svn: 29090
2006-07-10 21:37:44 +00:00
a7976d329e
Implement Regression/CodeGen/PowerPC/bswap-load-store.ll by folding bswaps
...
into i16/i32 load/stores.
llvm-svn: 29089
2006-07-10 20:56:58 +00:00
9aabc1e16f
Mark internal function static
...
llvm-svn: 29085
2006-07-10 19:53:12 +00:00
e40a7e2aa2
create the raddr addressing mode that matches any register and the frame index
...
use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot
llvm-svn: 29079
2006-07-10 01:41:35 +00:00
af5ae57333
Fix a typo that causes 2006-07-07-ComputeMaskedBits.ll to fail.
...
llvm-svn: 29072
2006-07-07 21:37:21 +00:00
5987cfb7b1
X86 target specific DAG combine: turn build_vector (load x), (load x+4),
...
(load x+8), (load x+12), <0, 1, 2, 3> to a single 128-bit load (aligned and
unaligned).
e.g.
__m128 test(float a, float b, float c, float d) {
return _mm_set_ps(d, c, b, a);
}
_test:
movups 4(%esp), %xmm0
ret
llvm-svn: 29042
2006-07-07 08:33:52 +00:00
59b6e8a683
Undisable ppc64 jit
...
llvm-svn: 29011
2006-07-06 17:10:42 +00:00
0441746468
Added option -code-model to set code model (only used in 64-bit) mode. Valid
...
values include small, kernel, medium, large, and default.
llvm-svn: 29009
2006-07-06 01:53:36 +00:00
0261242aa6
Reorg. No functionality change.
...
llvm-svn: 28999
2006-07-05 22:17:51 +00:00
41816100f4
Fix JIT on non MacOS X i386 systems.
...
llvm-svn: 28992
2006-07-05 07:09:13 +00:00
01078dc60b
These are already implemented
...
llvm-svn: 28990
2006-07-03 18:00:29 +00:00
042f5076ed
0 offsets for memory operands
...
llvm-svn: 28989
2006-07-03 17:57:34 +00:00
390922f979
Should just use xorps to clear XMM registers for all data types. pxor is also one byte longer.
...
llvm-svn: 28984
2006-06-29 18:04:54 +00:00
28a95491d9
Let X86CompilationCallback pass previous frame and return address to X86CompilationCallback2. Remove alloca hack.
...
llvm-svn: 28982
2006-06-29 01:48:36 +00:00
fa9e60895b
Add shift and rotate by 1 instructions / patterns.
...
llvm-svn: 28980
2006-06-29 00:36:51 +00:00
fc8cdda070
Always use xorps to clear XMM registers.
...
llvm-svn: 28979
2006-06-29 00:34:23 +00:00
56737d4fe3
Move .literal4 and .literal8 support into AsmPrinter.cpp
...
llvm-svn: 28978
2006-06-29 00:33:06 +00:00
0cc5907728
Hide x86 symbols
...
llvm-svn: 28976
2006-06-28 23:27:49 +00:00
996795b0dd
Use hidden visibility to make symbols in an anonymous namespace get
...
dropped. This shrinks libllvmgcc.dylib another 67K
llvm-svn: 28975
2006-06-28 23:17:24 +00:00
2f8c2d8ef2
shrink libllvmgcc.dylib another 25K
...
llvm-svn: 28971
2006-06-28 22:00:36 +00:00
87813744ba
Doh.
...
llvm-svn: 28963
2006-06-28 17:56:43 +00:00
0687b04455
Oops. Need to keep CP index.
...
llvm-svn: 28958
2006-06-28 07:55:24 +00:00
7f88856d95
Darwin puts float and double literal constants into literal4 and literal8 sections.
...
llvm-svn: 28957
2006-06-28 07:35:41 +00:00
a53a22e5fe
this case isn't handled
...
llvm-svn: 28948
2006-06-27 23:19:14 +00:00
f6f5aff038
handle the "mov reg1, reg2" case in isMoveInstr
...
llvm-svn: 28945
2006-06-27 21:52:45 +00:00
ca9c488528
Don't match 64-bit bitfield inserts into rlwimi's. todo add rldimi. :)
...
llvm-svn: 28944
2006-06-27 21:08:52 +00:00
f882c54505
Fix ppc64 jump tables
...
llvm-svn: 28941
2006-06-27 20:46:17 +00:00
2aed9ebded
Remove dead code.
...
llvm-svn: 28938
2006-06-27 20:34:14 +00:00
82ab3e21b1
Print stubs for external globals right.
...
llvm-svn: 28936
2006-06-27 20:20:53 +00:00
8aed3cc46b
Implement 64-bit select, bswap, etc.
...
llvm-svn: 28935
2006-06-27 20:14:52 +00:00
a2af3f47ea
Add a pattern for i64 sra. Print 8-byte units with a space between the .quad
...
and the data
llvm-svn: 28934
2006-06-27 20:07:26 +00:00
db9a95b775
Fix rewriting frame offsets with ixaddr instructions, which implicitly shift
...
the offset two bits to the left.
llvm-svn: 28933
2006-06-27 18:55:49 +00:00
a07410c95b
PPC doesn't have bit converts to/from i64
...
llvm-svn: 28932
2006-06-27 18:40:08 +00:00
3b5873456e
Add 64-bit MTCTR so that indirect calls work.
...
llvm-svn: 28931
2006-06-27 18:36:44 +00:00
e27d51e0d8
Fix an incorrect store pattern. This fixes em3d.
...
llvm-svn: 28930
2006-06-27 18:22:50 +00:00
d48ce27532
Implement 64-bit undef, sub, shl/shr, srem/urem
...
llvm-svn: 28929
2006-06-27 18:18:41 +00:00
cb5a84f446
Use i32 for shift amounts instead of i64. This gets bisort working.
...
llvm-svn: 28927
2006-06-27 17:34:57 +00:00
f7fd88356a
Add zextload from i32 -> i64, with this, perimeter works.
...
llvm-svn: 28926
2006-06-27 17:30:08 +00:00
1df0839067
Print darwin stub stuff correctly in 64-bit mode. With this, treeadd works in
...
ppc64 mode!
llvm-svn: 28923
2006-06-27 01:02:25 +00:00
9a40cca40f
Fix variable shadowing issue
...
llvm-svn: 28922
2006-06-27 00:10:13 +00:00
97b3da1519
Implement a bunch of 64-bit cleanliness work. With this, treeadd builds (but
...
doesn't work right).
llvm-svn: 28921
2006-06-27 00:04:13 +00:00
7ecbd301b1
Rearrange compares, add ADDI8, add sext from 32-to-64 bit register
...
llvm-svn: 28920
2006-06-26 23:53:10 +00:00
ec78cade34
Improve PPC64 calling convention support
...
llvm-svn: 28919
2006-06-26 22:48:35 +00:00
b6a65f4661
Remove two more definitions
...
llvm-svn: 28918
2006-06-26 22:47:37 +00:00
86e6046515
remove two unused instructions.
...
llvm-svn: 28917
2006-06-26 22:44:13 +00:00
38c5aee959
Simplify X86CompilationCallback: always align to 16-byte boundary; don't save EAX/EDX if unnecessary.
...
llvm-svn: 28910
2006-06-24 08:36:10 +00:00
a7b2bd5997
Add and sort "sections" in debug lines. This always stepping through
...
code in sections other than ".text", including weak sections like ctors and
dtors.
llvm-svn: 28909
2006-06-23 12:51:53 +00:00
0c9b90aba3
Eliminate unneeded parameter.
...
llvm-svn: 28907
2006-06-22 00:02:55 +00:00
fc1b27dad1
variable_ops instructions such as call can have any number of operands.
...
llvm-svn: 28906
2006-06-21 23:37:07 +00:00
680ac12e53
Add memory operand and int regs
...
llvm-svn: 28896
2006-06-21 15:42:36 +00:00
b0316eada6
inline asm, at least for floats
...
llvm-svn: 28895
2006-06-21 13:37:27 +00:00
336313ce3d
fix argument problem
...
llvm-svn: 28893
2006-06-21 01:00:43 +00:00
dc38e6f322
Correct returns of 64-bit values, though they seemed to work before...
...
llvm-svn: 28892
2006-06-21 00:34:03 +00:00
1f1b096142
Make these predicates correct in 64-bit mode too.
...
llvm-svn: 28890
2006-06-20 23:21:20 +00:00
52a956da52
Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit file
...
llvm-svn: 28889
2006-06-20 23:18:58 +00:00
5705d4d519
remove unused flag
...
llvm-svn: 28888
2006-06-20 23:15:07 +00:00
9d65f3507e
add some logical ops
...
llvm-svn: 28887
2006-06-20 23:11:59 +00:00
7a856a6d88
remove some unused patterns
...
llvm-svn: 28886
2006-06-20 23:11:36 +00:00
d881f8257b
Add some more immediate patterns. This allows us to compile:
...
void test6() {
Y = 0xABCD0123BCDE4567;
}
into:
_test6:
lis r2, -21555
lis r3, ha16(_Y)
ori r2, r2, 291
rldicr r2, r2, 32, 31
oris r2, r2, 48350
ori r2, r2, 17767
std r2, lo16(_Y)(r3)
blr
llvm-svn: 28885
2006-06-20 23:03:01 +00:00
9834ad2fc6
Instead of li/xoris use li/oris. Note that this doesn't work if bit 15 is
...
set, so disable the pattern in that case.
llvm-svn: 28884
2006-06-20 22:38:59 +00:00
7e742e46ac
Add some 64-bit logical ops.
...
Split imm16Shifted into a sext/zext form for 64-bit support.
Add some patterns for immediate formation. For example, we now compile this:
static unsigned long long Y;
void test3() {
Y = 0xF0F00F00;
}
into:
_test3:
li r2, 3840
lis r3, ha16(_Y)
xoris r2, r2, 61680
std r2, lo16(_Y)(r3)
blr
GCC produces:
_test3:
li r0,0
lis r2,ha16(_Y)
ori r0,r0,61680
sldi r0,r0,16
ori r0,r0,3840
std r0,lo16(_Y)(r2)
blr
llvm-svn: 28883
2006-06-20 22:34:10 +00:00
164a221b65
__i386__, __i386, etc. are not defined for x86-64. Use __x86_64__.
...
llvm-svn: 28881
2006-06-20 22:11:12 +00:00
d6e160d14d
64-bit bugfix: 0xFFFF0000 cannot be formed with a single lis.
...
llvm-svn: 28880
2006-06-20 21:39:30 +00:00
2d4e8f7e86
Add some patterns for globals, so we can now compile this:
...
static unsigned long long X, Y;
void test1() {
X = Y;
}
into:
_test1:
lis r2, ha16(_Y)
lis r3, ha16(_X)
ld r2, lo16(_Y)(r2)
std r2, lo16(_X)(r3)
blr
llvm-svn: 28879
2006-06-20 21:23:06 +00:00
868a75bec6
Remove some now-unneeded casts from instruction patterns. With the casts
...
removed, tblgen produces identical output to with them in.
llvm-svn: 28867
2006-06-20 00:39:56 +00:00
94d18df658
Add some patterns for ppc64
...
llvm-svn: 28866
2006-06-20 00:38:36 +00:00
dbec49d574
Remove some ugly now-redundant casts.
...
llvm-svn: 28864
2006-06-20 00:25:29 +00:00
55594634d7
Fix some mismatched type constraints
...
llvm-svn: 28862
2006-06-20 00:12:37 +00:00
cd58e9d8b9
Minor clean up.
...
llvm-svn: 28860
2006-06-19 19:25:30 +00:00
a88966fd5e
initial implementation of ARMRegisterInfo::eliminateFrameIndex
...
fixes test/Regression/CodeGen/ARM/ret_arg5.ll
llvm-svn: 28854
2006-06-18 00:08:07 +00:00
a54b9643aa
A new entry.
...
llvm-svn: 28848
2006-06-17 00:45:49 +00:00
49cadab385
Implement the getPointerRegClass method, which is required for the ptr_rc
...
magic to work.
llvm-svn: 28847
2006-06-17 00:01:04 +00:00
d2e9a67cd9
Later models likely to have Yonah like attributes.
...
llvm-svn: 28843
2006-06-16 21:58:49 +00:00
638ee4ee15
Upgrade some load/store instructions to use the proper addressing mode stuff.
...
llvm-svn: 28841
2006-06-16 21:29:41 +00:00
e8fe5e2bf4
In 64-bit mode, addr mode operands use G8RC instead of GPRC.
...
llvm-svn: 28840
2006-06-16 21:29:03 +00:00
a5190ae7a9
fix some assumptions that pointers can only be 32-bits. With this, we can
...
now compile:
static unsigned long X;
void test1() {
X = 0;
}
into:
_test1:
lis r2, ha16(_X)
li r3, 0
stw r3, lo16(_X)(r2)
blr
Totally amazing :)
llvm-svn: 28839
2006-06-16 21:01:35 +00:00
b429983988
Split 64-bit instructions out into a separate .td file
...
llvm-svn: 28838
2006-06-16 20:22:01 +00:00
61d703183e
Force 64-bit register availability in 64-bit mode. For real.
...
llvm-svn: 28837
2006-06-16 20:05:06 +00:00
a7d9db2fa5
Remove the -darwin and -aix llc options, inferring darwinism and aixism from
...
the target triple & subtarget info. woo.
llvm-svn: 28835
2006-06-16 18:50:48 +00:00
f3b5b92e58
Don't pass target name into TargetData anymore, it is never used or needed.
...
Remove explicit casts to std::string now that there is no overload resolution
issues in the TargetData ctors.
llvm-svn: 28830
2006-06-16 18:22:52 +00:00
7f043b52ff
Remove ctor with each piece specifyable (which causes overload ambiguities),
...
add a new init method.
llvm-svn: 28828
2006-06-16 18:11:26 +00:00
16682fff2b
Document the subtarget features better, make sure that 64-bit mode, 64-bit
...
support, and 64-bit register use are all consistent with each other.
Add a new "IsPPC" feature, to distinguish ppc32 vs ppc64 targets, use this
to configure TargetData differently. This not makes ppc64 blow up on lots
of stuff :)
llvm-svn: 28825
2006-06-16 17:50:12 +00:00
a35f306740
Rename some subtarget features. A CPU now can *have* 64-bit instructions,
...
can in 32-bit mode we can choose to optionally *use* 64-bit registers.
llvm-svn: 28824
2006-06-16 17:34:12 +00:00
0c4aa14deb
First baby step towards ppc64 support. This adds a new -march=ppc64 backend
...
that is currently just like ppc32 :)
llvm-svn: 28813
2006-06-16 01:37:27 +00:00
cb29586ce4
Add a note that Nate noticed.
...
llvm-svn: 28808
2006-06-15 21:33:31 +00:00
19f964e048
1. Support standard dwarf format (was bootstrapping in Apple format.)
...
2. Add vector support.
llvm-svn: 28807
2006-06-15 20:51:43 +00:00
66f0e09313
Vector extract / insert index operand should have ptr type.
...
llvm-svn: 28798
2006-06-15 08:19:05 +00:00
94bb93f8f7
Type of extract_element index operand should be iPTR.
...
llvm-svn: 28797
2006-06-15 08:18:06 +00:00
de7156f12c
Type of vector extract / insert index operand should be iPTR.
...
llvm-svn: 28796
2006-06-15 08:14:54 +00:00
c8734381ac
X86 call instructions can take variable number of operands. Parameters of
...
vector types are passed via XMM registers.
llvm-svn: 28789
2006-06-14 22:24:55 +00:00
37c1c44c14
add a note
...
llvm-svn: 28787
2006-06-14 21:26:18 +00:00
ca25486603
Add argument registers to the end of call operand list (partial fix).
...
llvm-svn: 28783
2006-06-14 18:17:40 +00:00
f67bec0579
Place dwarf headers at earliest possible point. Well behaved when skipping
...
functions.
llvm-svn: 28781
2006-06-14 11:35:03 +00:00
7c69df968c
I am sure I had commited this workaround before. Perhaps soon I should sort it all out
...
llvm-svn: 28772
2006-06-13 20:34:47 +00:00
f570feeae3
It really helps to be returning to the correct place
...
llvm-svn: 28769
2006-06-13 18:27:39 +00:00
c5bb8ab1d5
Port some bugfixes in shift handling from SimplifyDemandedBits over to
...
ComputeMaskedBits. DemandedMasks and KnownZero/One masks should never have
bits set out of the range of the base datatype.
llvm-svn: 28768
2006-06-13 16:52:37 +00:00
8cac9cd5f6
TargetLowering::ComputeMaskedBits was not clearing reciprocal bits on shifts.
...
llvm-svn: 28765
2006-06-13 13:08:58 +00:00
17ca732b6a
Cygwin support: use _alloca to allocate stack if > 4k. Patch by Anton Korobeynikov.
...
llvm-svn: 28764
2006-06-13 05:14:44 +00:00
ac59ab515a
Gaar! Don't use r11 for CR save/restore, use R0. R11 can be register
...
allocated, thus live across the save/reload. This fixes
llc-beta /MultiSource/Applications/spiff/spiff
llc-beta /MultiSource/Benchmarks/sim/sim:
llc-beta /MultiSource/Benchmarks/Ptrdist/bc/bc
llc-beta /MultiSource/Benchmarks/McCat/12-IOtest/iotest:
llc-beta /MultiSource/Benchmarks/FreeBench/fourinarow/fourinarow
llc-beta /MultiSource/Benchmarks/Fhourstones-3.1/fhourstones3.1
llc-beta /MultiSource/Benchmarks/mediabench/adpcm/rawdaudio/rawdaudio
llc-beta /MultiSource/Benchmarks/mediabench/adpcm/rawcaudio/rawcaudio
llc-beta /MultiSource/Benchmarks/mediabench/g721/g721encode/encode
llc-beta /MultiSource/Benchmarks/mediabench/jpeg/jpeg-6a/cjpeg
and probably others, with -regalloc=local.
llvm-svn: 28761
2006-06-12 23:59:16 +00:00
6b043a24a1
Fix spilling and reloading of CR regs to reload the right values. This fixes
...
Olden/power (and probably others) with -regalloc=local.
llvm-svn: 28760
2006-06-12 21:50:57 +00:00
80528499cf
Let the alpha breakage begin. First Formals and RET. next Calls
...
llvm-svn: 28753
2006-06-12 18:09:24 +00:00
0e57b2cb92
Start on my todo list
...
llvm-svn: 28752
2006-06-12 16:07:18 +00:00
4e76015e0b
lower more then 4 formal arguments. The offset is currently hard coded.
...
implement SelectFrameIndex
llvm-svn: 28751
2006-06-12 12:28:08 +00:00
b055c8737f
Work around a nasty tblgen bug where it doesn't add operands for varargs
...
nodes correctly.
llvm-svn: 28745
2006-06-10 01:15:02 +00:00
006b2c6ab9
Fix a problem exposed by the local allocator. CALL instructions are not marked
...
as using incoming argument registers, so the local allocator would clobber them
between their set and use. To fix this, we give the call instructions a variable
number of uses in the CALL MachineInstr itself, so live variables understands
the live ranges of these register arguments.
llvm-svn: 28744
2006-06-10 01:14:28 +00:00
beedf824e3
Comments to appease sabre.
...
llvm-svn: 28737
2006-06-09 06:25:10 +00:00
0e14a56d35
Minor compilation speed improvement.
...
llvm-svn: 28736
2006-06-09 06:24:42 +00:00
ba1ed585ee
Add support for "m" inline asm constraints.
...
llvm-svn: 28728
2006-06-08 18:03:49 +00:00
dc614c193e
Added X86FunctionInfo subclass of MachineFunction to record whether the
...
function that is being lowered is forced to use FP. Currently this is only
true for main() / Cygwin.
llvm-svn: 28703
2006-06-06 23:30:24 +00:00
16826c3503
Now that PR633 is implemented, the CBE can know to emit _setjmp/_longjmp
...
when available. This speeds up hexxagon from 18.61s to 16.61s with the CBE on
PPC Mac OS (for reference, LLC is 15.48s and GCC is 23.35s).
llvm-svn: 28697
2006-06-06 21:45:47 +00:00
c8587d4b81
Add PowerPC intrinsics to support dcbz[l]
...
llvm-svn: 28696
2006-06-06 21:29:23 +00:00
6306becc49
add R0 to liveout
...
expand "ret null" (implements test/Regression/CodeGen/ARM/ret_void.ll)
note that a Flag link is missing between the copy and the branch
llvm-svn: 28691
2006-06-05 22:26:14 +00:00
0f29df98a1
A few new entries.
...
llvm-svn: 28683
2006-06-04 09:08:00 +00:00
0de66677e7
Be consistent with gcc.
...
llvm-svn: 28682
2006-06-04 07:24:07 +00:00
b47461350c
ignore ordered/unordered for now
...
llvm-svn: 28679
2006-06-04 00:25:51 +00:00
e8a42360c5
Cygwin support. Patch by Anton Korobeynikov!
...
llvm-svn: 28672
2006-06-02 22:38:37 +00:00
a2efb9f3ec
Use xor to clear a register.
...
llvm-svn: 28667
2006-06-02 21:20:34 +00:00
7ae8632cb4
Incorrect AT&T opcode.
...
llvm-svn: 28666
2006-06-02 21:09:10 +00:00
8fd1036612
Add mingw support, patch contributed by Anton
...
llvm-svn: 28661
2006-06-02 18:54:01 +00:00
4442a70b3a
Silence -pedantic warning
...
llvm-svn: 28633
2006-06-01 17:17:06 +00:00
b47b8a9fad
Silence -pedantic warning.
...
llvm-svn: 28630
2006-06-01 17:13:10 +00:00
2b2c1be49c
Typos
...
llvm-svn: 28617
2006-06-01 05:53:27 +00:00
75f29be136
For PR786:
...
Don't warn about -pedantic errors. Add a note to the PR instead.
llvm-svn: 28616
2006-06-01 05:49:51 +00:00
a62f097c96
For PR786:
...
Turn -pedantic and -Wno-long-long compile flags on by default. In a few
places, avoid the warnings by removing these options in the local makefile.
One notable exception: lib/Target/CBackend/Writer.cpp. These warnings are
left on as a reminder to developers to clean them up.
llvm-svn: 28614
2006-06-01 01:55:21 +00:00
a647c7ff42
Use archive libraries instead of object files for VMCore, BCReader,
...
BCWriter, and bzip2 libraries. Adjust the various makefiles to accommodate
these changes. This was done to speed up link times.
llvm-svn: 28610
2006-06-01 01:30:27 +00:00
2489ccdd90
Remove a warning
...
llvm-svn: 28607
2006-06-01 00:30:39 +00:00
cfaffdd335
Rename ASM modifier trunc8, trunc16 to subreg8, subreg16.
...
llvm-svn: 28606
2006-05-31 22:34:26 +00:00
ff82596981
Fix casting so there's no warning on Alpha.
...
llvm-svn: 28605
2006-05-31 22:26:11 +00:00
cf70c7f42d
Sign extender
...
llvm-svn: 28603
2006-05-31 22:05:11 +00:00
25e44e008d
Rename instructions for consistency sake.
...
llvm-svn: 28594
2006-05-31 19:00:07 +00:00
8abf45e22d
Select vector_shuffle v1, undef <2, 3, ?, ?> to MOVHLPS.
...
llvm-svn: 28582
2006-05-31 00:51:37 +00:00
550cb663e8
Remove dead code.
...
llvm-svn: 28581
2006-05-31 00:50:42 +00:00
ddced95d8f
A new entry
...
llvm-svn: 28579
2006-05-30 23:56:31 +00:00
57399704b3
MAXP{D|S} and MINP{D|S} are commutable.
...
llvm-svn: 28578
2006-05-30 23:47:30 +00:00
c0f90bef47
Commute shufps / shufpd.
...
llvm-svn: 28577
2006-05-30 23:34:30 +00:00
f21045a5cd
Somehow I lost a condition when I was shuffling some code around. Anyway,
...
only transform a shufps to pshufd when the first two operands are the same.
llvm-svn: 28575
2006-05-30 22:13:36 +00:00
c8c172eaae
Fix a build breaker.
...
llvm-svn: 28574
2006-05-30 21:45:53 +00:00
a4fc5b8699
Oops. PSHUFD is only available with SSE2.
...
llvm-svn: 28573
2006-05-30 21:30:59 +00:00
a5d4587296
Add a note
...
llvm-svn: 28572
2006-05-30 21:29:15 +00:00
b9342afa56
Always reserve space for 8 spilled GPRs. GCC apparently assumes that this
...
space will be available, even if the callee isn't varargs.
llvm-svn: 28571
2006-05-30 21:21:04 +00:00
66f849bd7b
Allow shufps x, x, mask to be converted to pshufd x, mask to save a move.
...
llvm-svn: 28565
2006-05-30 20:26:50 +00:00
b33e54ead7
Remove bogus comment.
...
llvm-svn: 28564
2006-05-30 20:24:48 +00:00
5bc60da112
Expand ret into "CopyToReg;BRIND"
...
llvm-svn: 28559
2006-05-30 17:33:19 +00:00
02420144ab
Add a note about integer multiplication by constants.
...
llvm-svn: 28551
2006-05-30 07:37:37 +00:00
734e1e241b
A addressing mode folding enhancement:
...
Fold c2 in (x << c1) | c2 where (c2 < c1)
e.g.
int test(int x) {
return (x << 3) + 7;
}
This can be codegen'd as:
leal 7(,%eax,8), %eax
llvm-svn: 28550
2006-05-30 06:59:36 +00:00
749138582e
Some new entries about truncate / anyext
...
llvm-svn: 28548
2006-05-30 06:23:50 +00:00
64d8692dee
Ignore generated files
...
llvm-svn: 28520
2006-05-27 01:23:30 +00:00
a3add0fea8
Change RET node to include signness information of the return values. i.e.
...
RET chain, value1, sign1, value2, sign2, ...
llvm-svn: 28510
2006-05-26 23:10:12 +00:00
b92f418408
Vector argument must be passed in memory location aligned on 16-byte boundary.
...
llvm-svn: 28505
2006-05-26 20:37:47 +00:00
bfb5ea6875
Mac OS X ABI document lied. The first four XMM registers are used to pass
...
vector arguments, not three.
llvm-svn: 28504
2006-05-26 19:22:06 +00:00
a01e799927
Minor update to make the code more clear
...
llvm-svn: 28499
2006-05-26 18:39:59 +00:00
cbfb3d07e0
Update more comments.
...
llvm-svn: 28498
2006-05-26 18:37:16 +00:00
763f9b00f0
Fix some comments.
...
llvm-svn: 28497
2006-05-26 18:25:43 +00:00
83dc51d7ff
No need to handle illegal types.
...
llvm-svn: 28496
2006-05-26 18:22:49 +00:00
87bc1a9b0b
On ARM, alignment is in bits
...
Add lr as a hard coded operand of bx
llvm-svn: 28494
2006-05-26 10:56:17 +00:00
70145f2d5e
Remove a couple of bogus casts.
...
llvm-svn: 28493
2006-05-26 08:04:31 +00:00
Evan Cheng