dfbf91e59d
more shotenning
...
llvm-svn: 31331
2006-10-31 23:46:56 +00:00
a41c2d6432
Nuke dead code.
...
llvm-svn: 31327
2006-10-31 21:53:31 +00:00
44daa50bed
allow the address of a global to be used with the "i" constraint when in
...
-static mode. This implements PR882.
llvm-svn: 31326
2006-10-31 20:13:11 +00:00
60ce558aaa
implement the 'c' inline asm modifier character
...
llvm-svn: 31325
2006-10-31 20:12:30 +00:00
8b20fa42da
Let us play simplify the td file (and fix a few missed sub and mul patterns).
...
llvm-svn: 31322
2006-10-31 19:52:12 +00:00
f6a6966cd2
handle "st" as "st(0)"
...
llvm-svn: 31320
2006-10-31 19:42:44 +00:00
8c6949e5b2
Change the prototype for TargetLowering::isOperandValidForConstraint
...
llvm-svn: 31318
2006-10-31 19:40:43 +00:00
692e4155aa
Add all that branch mangling niftiness
...
llvm-svn: 31313
2006-10-31 16:49:55 +00:00
4e825336a0
add support for calling functions when the caller has variable sized objects
...
llvm-svn: 31312
2006-10-31 13:03:26 +00:00
aa4c0f9374
1. Clean up code due to changes in SwitchTo*Section(2)
...
2. Added partial debug support for mingw\cygwin targets (the same as
Linux\ELF). Please note, that currently mingw\cygwin uses 'stabs' format
for storing debug info by default, thus many (runtime) libraries has
this information included. These formats shouldn't be mixed in one binary
('stabs' & 'DWARF'), otherwise binutils tools will be confused.
llvm-svn: 31311
2006-10-31 08:31:24 +00:00
49993529eb
Unbreaking static ctors patch.
...
Defaulting second arguments of SwitchTo*Section, this should make things
somehow clearer.
llvm-svn: 31306
2006-10-31 06:11:06 +00:00
2545fe6d93
Make this compile again.
...
llvm-svn: 31304
2006-10-31 01:45:56 +00:00
de5ecd6bc1
Apply Aton's LLVM patch for PR973: Linux ctors / dtors support.
...
llvm-svn: 31303
2006-10-31 01:26:55 +00:00
3e36e07db2
fix miscompilation of llvm.isunordered, where we branched on the opposite
...
condition. This fixes miscompilation of Olden/bh and many others.
llvm-svn: 31301
2006-10-30 23:02:25 +00:00
b51b5c0b1f
Add debug support for X86/ELF targets (Linux). This allows llvm-gcc4
...
generated object modules to be debugged with gdb. Hopefully this helps
pre-release debugging.
llvm-svn: 31299
2006-10-30 22:32:30 +00:00
7443600ef8
fix wonky indentation
...
llvm-svn: 31298
2006-10-30 22:27:23 +00:00
0d41d19427
All targets expand BR_JT for now.
...
llvm-svn: 31294
2006-10-30 08:02:39 +00:00
113f7470e6
implement the BlockHasNoFallThrough hook
...
llvm-svn: 31264
2006-10-28 17:35:02 +00:00
53ebf20c26
add another target hook for branch folding.
...
llvm-svn: 31262
2006-10-28 17:29:57 +00:00
ae8c29a7d3
Doh. Must check if GV is constant first before putting it in .cstring.
...
llvm-svn: 31253
2006-10-28 05:56:51 +00:00
0d782b4c60
Doh. Must check if GV is constant first.
...
llvm-svn: 31252
2006-10-28 05:56:06 +00:00
a6873c0f88
don't dist internal readme
...
llvm-svn: 31247
2006-10-28 00:51:15 +00:00
acc6b37d0d
don't dist internal readme's
...
llvm-svn: 31246
2006-10-28 00:49:54 +00:00
3be52bb570
don't distribute internal readme's
...
llvm-svn: 31245
2006-10-28 00:48:27 +00:00
247e09a07c
Make sure all the readme files get distributed.
...
llvm-svn: 31244
2006-10-28 00:11:39 +00:00
28174f5a3a
this doesn't occur any more in mason
...
llvm-svn: 31236
2006-10-27 22:02:19 +00:00
4c0cc53da1
the code in question is now:
...
cmpw cr0, r7, r3
ble cr0, LBB1_5 ;bb25
LBB1_8: ;bb17
cmpw cr0, r8, r5
bgt cr0, LBB1_2 ;bb
which is just as good as crnand.
llvm-svn: 31235
2006-10-27 22:00:55 +00:00
e056dd5928
Fixed a significant bug where unpcklpd is incorrectly used to extract element 1 from a v2f64 value.
...
llvm-svn: 31228
2006-10-27 21:08:32 +00:00
bf3df77758
Fix for PR968: expand vector sdiv, udiv, srem, urem.
...
llvm-svn: 31220
2006-10-27 18:49:08 +00:00
e54243f030
Initialize CStringSection member var.
...
llvm-svn: 31214
2006-10-27 16:14:06 +00:00
f53ae69365
Change load PatFrag to ignore indexed load.
...
llvm-svn: 31210
2006-10-26 21:55:50 +00:00
e1e06c2de8
Place cstrings in .cstring section.
...
llvm-svn: 31207
2006-10-26 21:48:57 +00:00
392f645783
Put cstrings in .cstring section when compiling for Mac OS X.
...
llvm-svn: 31203
2006-10-26 19:18:18 +00:00
a23166d6a4
initial support for frame pointers
...
llvm-svn: 31197
2006-10-26 13:31:26 +00:00
c6b52da458
Enclose a case in { and } so that the pickier compilers don't complain.
...
llvm-svn: 31196
2006-10-26 06:17:40 +00:00
7e80b0b31e
For PR950:
...
Make necessary changes to support DIV -> [SUF]Div. This changes llvm to
have three division instructions: signed, unsigned, floating point. The
bytecode and assembler are bacwards compatible, however.
llvm-svn: 31195
2006-10-26 06:15:43 +00:00
c415c5be49
During vector shuffle lowering, we sometimes commute a vector shuffle to try
...
to match MOVL (movss, movsd, etc.). Don't forget to commute it back and try
unpck* and shufp* if that doesn't pan out.
llvm-svn: 31186
2006-10-25 21:49:50 +00:00
7e065ff7e4
X86ISD::PEXTRW 3rd operand type is always target pointer type.
...
llvm-svn: 31185
2006-10-25 21:35:05 +00:00
798b306311
Remove -disable-x86-shuffle-opti
...
llvm-svn: 31183
2006-10-25 20:48:19 +00:00
71b99297aa
Move getPreferredAlignmentLog from AsmPrinter to TargetData
...
llvm-svn: 31171
2006-10-24 20:32:14 +00:00
bd29281e97
expand ISD::VACOPY
...
llvm-svn: 31170
2006-10-24 20:15:21 +00:00
9030fc690a
Fix CodeGen/IA64/ret-0.ll, which has apparently been broken since some of the
...
isel changes happened months ago.
llvm-svn: 31164
2006-10-24 17:09:43 +00:00
ed32883b27
fix warning about missing newline at end of file
...
llvm-svn: 31162
2006-10-24 17:07:11 +00:00
aaeede0aa2
implement uncond branch insertion, mark branches with isBranch.
...
llvm-svn: 31160
2006-10-24 16:47:57 +00:00
ccd7704354
implement uncond branch insertion for the branch folding pass
...
llvm-svn: 31159
2006-10-24 16:44:55 +00:00
042d56230e
implement uncond branch insertion so alpha works work branchfolding.
...
llvm-svn: 31158
2006-10-24 16:41:36 +00:00
b7267bd034
implement uncond branch insertion for sparc to fix regressions from last night
...
due to branchfolding
llvm-svn: 31157
2006-10-24 16:39:19 +00:00
f054003ba7
new bad case
...
llvm-svn: 31156
2006-10-24 16:12:47 +00:00
d43e8a7429
Add intrinsics for the rest of the DCB* instructions.
...
llvm-svn: 31148
2006-10-24 01:08:42 +00:00
b43efe86f5
implement STRB and STRH
...
llvm-svn: 31138
2006-10-23 20:34:27 +00:00
cd5f662c7b
expand ISD::MEMSET
...
llvm-svn: 31137
2006-10-23 20:08:22 +00:00
bb3084546a
this part implemented.
...
llvm-svn: 31122
2006-10-22 21:40:12 +00:00
41a83d7871
Do section switching right way for Mingw\Cygwin and Linux.
...
This will allow (after llvm-gcc linkage fix) more dummy tests using
libstdc++ to pass on mingw :)
llvm-svn: 31120
2006-10-22 21:37:13 +00:00
aa1c614784
Don't generate a prototype for _setjmp. At least on Linux, this function
...
has a different prototype than the one #included from <setjmp.h>. This
patch fixes siod and a number of other test cases on Linux that were
failing the CBE because of this _setjmp issue.
llvm-svn: 31112
2006-10-22 09:58:21 +00:00
23f22de26f
Implement support for branch reversal, fix a bug in branch analysis.
...
This provides stuff like:
cmpw cr0, r15, r29
mr r14, r15
- bge cr0, LBB3_111 ;bb656
- b LBB3_90 ;bb501
+ blt cr0, LBB3_90 ;bb501
LBB3_111: ;bb656
lwz r18, 68(r1)
which is particularly good for dispatch group formation.
llvm-svn: 31101
2006-10-21 06:03:11 +00:00
3a897f31fa
Implement support for branch condition reversal.
...
llvm-svn: 31099
2006-10-21 05:52:40 +00:00
d881660366
Simplify code, no functionality change
...
llvm-svn: 31097
2006-10-21 05:42:09 +00:00
94e04442eb
implement support for inserting a cond branch
...
llvm-svn: 31096
2006-10-21 05:36:13 +00:00
6fca75ec05
allow insertion of a conditional branch with fall-through
...
llvm-svn: 31095
2006-10-21 05:34:23 +00:00
20e75d4635
update assert message
...
llvm-svn: 31093
2006-10-21 04:42:29 +00:00
8366b874a9
bugfix
...
llvm-svn: 31074
2006-10-20 20:44:34 +00:00
c0fb567e23
Implement branch analysis/xform hooks required by the branch folding pass.
...
llvm-svn: 31065
2006-10-20 17:42:20 +00:00
e0fc4dfc22
For PR950:
...
This patch implements the first increment for the Signless Types feature.
All changes pertain to removing the ConstantSInt and ConstantUInt classes
in favor of just using ConstantInt.
llvm-svn: 31063
2006-10-20 07:07:24 +00:00
336d62e99a
use Pat to implement extloadi8 and extloadi16
...
llvm-svn: 31052
2006-10-19 17:05:03 +00:00
f8274c0318
implement undef
...
llvm-svn: 31049
2006-10-19 13:45:00 +00:00
ea67b973c2
print common symbols
...
llvm-svn: 31048
2006-10-19 13:30:40 +00:00
ff62819e2f
implement extloadi8 and extloadi16
...
llvm-svn: 31047
2006-10-19 12:45:04 +00:00
3c563c5072
expand SIGN_EXTEND_INREG
...
llvm-svn: 31046
2006-10-19 12:06:50 +00:00
b260306625
expand brind so that we don't have to implement jump tables right now
...
llvm-svn: 31045
2006-10-19 10:56:43 +00:00
f4aeff00c2
fit in 80 cols
...
llvm-svn: 31039
2006-10-18 18:26:48 +00:00
35a1471046
add a note
...
llvm-svn: 31038
2006-10-18 17:04:09 +00:00
bad440742e
add blx
...
llvm-svn: 31037
2006-10-18 16:21:43 +00:00
01dd97a8aa
add isTerminatortto b and bcond
...
llvm-svn: 31036
2006-10-18 16:20:57 +00:00
b21e8d2e12
implement CallingConv::Fast as CallingConv::C
...
llvm-svn: 31034
2006-10-18 12:03:07 +00:00
24b7ac303c
Fixed mingw\cygwin linkonce linkage once again.
...
Added workaround for linker bug with linkonce sections.
Changed sections prefix to allow linker merge them
(PE loader doesn't like too much long-named sections :) )
All of this unbreaks libstdc++ on mingw32 allowing (small)
programs to be compiled, linked and run.
llvm-svn: 31033
2006-10-18 09:12:29 +00:00
454436dcc5
set the ppc64 stack pointer right, dynamic alloca now works for ppc64
...
llvm-svn: 31028
2006-10-18 01:20:43 +00:00
ab4df83426
Expand alloca for ppc64
...
llvm-svn: 31027
2006-10-18 01:18:48 +00:00
0408e5b7ce
expose DWARF_LABEL opcode# so the branch folder can update debug info properly.
...
llvm-svn: 31024
2006-10-17 22:41:45 +00:00
ba8f296167
expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM
...
llvm-svn: 31014
2006-10-17 21:05:33 +00:00
3968263ca8
add the FPUnaryOp and DFPUnaryOp classes
...
llvm-svn: 31013
2006-10-17 20:45:22 +00:00
99bf133d58
add FABSS and FABSD
...
llvm-svn: 31012
2006-10-17 20:33:13 +00:00
75b01beb2f
Adding linkonce linkage codegeneration support for mingw32\cygwin
...
targets.
llvm-svn: 31011
2006-10-17 20:29:49 +00:00
2d7d14262a
remove extra [] in stores
...
llvm-svn: 31008
2006-10-17 18:29:14 +00:00
a61f0105bd
add support for inserting an uncond branch
...
llvm-svn: 31003
2006-10-17 18:06:55 +00:00
19398ec86e
initial implementation of addressing mode 5
...
llvm-svn: 31002
2006-10-17 18:04:53 +00:00
feb50708eb
add the immediate to the Offset in eliminateFrameIndex
...
llvm-svn: 30998
2006-10-17 14:34:02 +00:00
418c8e69bb
add FSTD and FSTS
...
llvm-svn: 30996
2006-10-17 13:36:07 +00:00
c31ee94920
add FCPYS and FCPYD
...
llvm-svn: 30995
2006-10-17 13:13:23 +00:00
2794184191
Use S_debug for dwarf info.
...
llvm-svn: 30994
2006-10-17 11:30:57 +00:00
a3e1ad7a61
Proper fix.
...
llvm-svn: 30993
2006-10-17 00:24:49 +00:00
ed60d16ac7
One more try.
...
llvm-svn: 30992
2006-10-16 23:44:08 +00:00
1367ff084d
Unbreak x86-64 build.
...
llvm-svn: 30990
2006-10-16 22:53:28 +00:00
afdd47ace4
add fdivs e fdivd
...
llvm-svn: 30988
2006-10-16 21:50:04 +00:00
f719c5f43d
expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS
...
llvm-svn: 30987
2006-10-16 21:10:32 +00:00
afb610468b
Added a X86CompilationCallback variant which saves XMM argument registers for targets with SSE.
...
llvm-svn: 30986
2006-10-16 21:01:55 +00:00
a8b4aeace0
Proper fix for rdar://problem/4770604 Thanks to Stuart Hastings!
...
llvm-svn: 30985
2006-10-16 21:00:37 +00:00
e341d60f53
define the DFPBinOp class
...
llvm-svn: 30981
2006-10-16 18:39:22 +00:00
f63752f94b
add the FPBinOp class
...
llvm-svn: 30980
2006-10-16 18:32:36 +00:00
b23dc14135
define the Addr1BinOp class
...
llvm-svn: 30979
2006-10-16 18:18:14 +00:00
203922d083
define the IntBinOp class and use it to implement the multiply instructions
...
llvm-svn: 30978
2006-10-16 17:57:20 +00:00
c4abf8dc5b
fix assembly syntax
...
llvm-svn: 30977
2006-10-16 17:38:12 +00:00
677ee8390d
implement LDRB, LDRSB, LDRH and LDRSH
...
llvm-svn: 30976
2006-10-16 17:17:22 +00:00
595dc4c884
implement smull and umull
...
llvm-svn: 30975
2006-10-16 16:33:29 +00:00
949bcc94ea
Avoid getting into an infinite loop when -disable-x86-shuffle-opti is specified.
...
llvm-svn: 30974
2006-10-16 06:36:00 +00:00
ff1a712794
SelectScalarSSELoad should call CanBeFoldedBy as well.
...
llvm-svn: 30973
2006-10-16 06:34:55 +00:00
34e051d537
Align stack size to DWORD boundary
...
llvm-svn: 30964
2006-10-14 20:53:35 +00:00
2b7f635951
expand ISD::BRCOND
...
llvm-svn: 30963
2006-10-14 17:59:54 +00:00
4c1baf1528
fix some fp condition codes
...
use non trapping comparison instructions
llvm-svn: 30962
2006-10-14 13:42:53 +00:00
b86375cfd0
Corrected load folding check. We need to start from the root of the sub-dag
...
being matched and ensure there isn't a non-direct path to the load (i.e. a
path that goes out of the sub-dag.)
llvm-svn: 30958
2006-10-14 08:33:25 +00:00
a47294ed7a
implement branch inspection/modification methods.
...
llvm-svn: 30946
2006-10-13 21:21:17 +00:00
ab51cf2e78
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
...
llvm-svn: 30945
2006-10-13 21:14:26 +00:00
63007919dc
remove some dead code
...
llvm-svn: 30938
2006-10-13 20:40:42 +00:00
be131662c3
add note
...
llvm-svn: 30937
2006-10-13 20:20:58 +00:00
cf56917053
set isBarrier correctly
...
llvm-svn: 30936
2006-10-13 19:10:34 +00:00
4dc4f30a48
Correctly handle instruction separators.
...
llvm-svn: 30935
2006-10-13 17:56:02 +00:00
95129a7f22
Expose method and ivars for measuring inline asm length properly.
...
llvm-svn: 30934
2006-10-13 17:50:07 +00:00
5ab3166f74
add FNEGS and FNEGD
...
llvm-svn: 30932
2006-10-13 17:37:35 +00:00
d6050c3149
add SBCS and SUBS
...
llvm-svn: 30930
2006-10-13 17:19:20 +00:00
79d9807c87
implement calls to functions that return long
...
llvm-svn: 30929
2006-10-13 16:47:22 +00:00
3874a168d0
implement unordered floating point compares
...
llvm-svn: 30928
2006-10-13 13:14:59 +00:00
03fda13dbb
add a note
...
llvm-svn: 30921
2006-10-12 22:01:26 +00:00
a7956d2894
Doh. This wasn't causing problems by luck.
...
llvm-svn: 30914
2006-10-12 19:13:59 +00:00
694810c227
Some X86ISD::CMP were created with wrong ValueType's.
...
llvm-svn: 30913
2006-10-12 19:12:56 +00:00
8c9422c4b8
mark call adjustments as modifying the SP
...
llvm-svn: 30911
2006-10-12 18:00:26 +00:00
0e0ee36f45
adjcallstack up/down clobbers the sp
...
llvm-svn: 30910
2006-10-12 18:00:14 +00:00
d376e9f4ac
adjcallstackup/down clobbers the stack pointer
...
llvm-svn: 30909
2006-10-12 17:57:58 +00:00
7374bc0577
mark adjcallstack up/down as clobbering and using the SP
...
llvm-svn: 30908
2006-10-12 17:56:34 +00:00
adcaf294d7
Move the Imp tblgen class from the X86 backend to common code.
...
llvm-svn: 30907
2006-10-12 17:49:27 +00:00
b5cda3daa9
Mark ADJCALLSTACKUP/DOWN as clobbering ESP so that virtregmap will notice
...
that it can't assume ESP is unmodified across the instrs.
llvm-svn: 30905
2006-10-12 17:42:56 +00:00
40ec2bebf9
fix compilation failure of smg2000
...
llvm-svn: 30900
2006-10-12 03:55:48 +00:00
d5fcfaa6da
Fold "zero extending vector loads" now that evan added the chain manip stuff.
...
This compiles both tests in X86/vec_ss_load_fold.ll into:
_test1:
movss 4(%esp), %xmm0
subss LCPI1_0, %xmm0
mulss LCPI1_1, %xmm0
minss LCPI1_2, %xmm0
xorps %xmm1, %xmm1
maxss %xmm1, %xmm0
cvttss2si %xmm0, %eax
andl $65535, %eax
ret
instead of:
_test1:
movss LCPI1_0, %xmm0
movss 4(%esp), %xmm1
subss %xmm0, %xmm1
movss LCPI1_1, %xmm0
mulss %xmm0, %xmm1
movss LCPI1_2, %xmm0
minss %xmm0, %xmm1
xorps %xmm0, %xmm0
maxss %xmm0, %xmm1
cvttss2si %xmm1, %eax
andl $65535, %eax
ret
llvm-svn: 30894
2006-10-11 22:09:58 +00:00
4090dc4703
ComplexPatterns sse_load_f32 and sse_load_f64 returns in / out chain operands.
...
llvm-svn: 30892
2006-10-11 21:06:01 +00:00
577ef7694e
Add properties to ComplexPattern.
...
llvm-svn: 30891
2006-10-11 21:03:53 +00:00
fa8cbfd8e8
Reduce the amount of state in the lowering code and drop old pattern ISel functions
...
llvm-svn: 30881
2006-10-11 16:24:51 +00:00
d35734bd1f
Naming consistency.
...
llvm-svn: 30878
2006-10-11 07:10:22 +00:00
6487854b3f
Use cute tblgen tricks to make zap handling more powerful. Specifically,
...
when the dag combiner simplifies an and mask, notice this and allow those bits
to be missing from the zap mask.
This compiles Alpha/zapnot4.ll into:
sll $16,3,$0
zapnot $0,3,$0
ret $31,($26),1
instead of:
ldah $0,1($31)
lda $0,-8($0)
sll $16,3,$1
and $1,$0,$0
ret $31,($26),1
It would be *really* nice to replace the hunk of code in the
AlphaISelDAGToDAG.cpp file that matches (and (srl (x, C), c2) into
(SRL (ZAPNOTi)) with a similar pattern, but I've spent enough time poking
at alpha. Make andrew will do this.
llvm-svn: 30875
2006-10-11 05:13:56 +00:00
a6bbf33cbf
Jimptables working again on alpha.
...
As a bonus, use the GOT node instead of the AlphaISD::GOT for internal stuff.
llvm-svn: 30873
2006-10-11 04:29:42 +00:00
9f86f7c2ab
Remove dead/redundant instructions. These are handled by ZAPNOTi
...
llvm-svn: 30872
2006-10-11 04:12:39 +00:00
4a57e2a6ed
This entry is done. switched to the gcc way of doing things.
...
llvm-svn: 30867
2006-10-11 01:48:03 +00:00
3d74556d74
This has apparently been fixed
...
llvm-svn: 30864
2006-10-11 01:44:46 +00:00
8429e1f6c3
uint <-> double conversion
...
llvm-svn: 30862
2006-10-10 20:38:57 +00:00
b5f1ff336a
add fp sub
...
llvm-svn: 30859
2006-10-10 19:35:01 +00:00
57d109fb08
add double <-> int conversion
...
llvm-svn: 30858
2006-10-10 18:55:14 +00:00
d1a4ea41c9
compare doubles
...
llvm-svn: 30856
2006-10-10 16:33:47 +00:00
d15c892433
initial support for fp compares. Unordered compares not implemented yet
...
llvm-svn: 30854
2006-10-10 12:56:00 +00:00
61b8b43bbe
More isel time load folding checking for nodes that produce flag values.
...
See comment in CanBeFoldedBy() for detailed explanation.
llvm-svn: 30851
2006-10-10 01:46:56 +00:00
57ccb6d372
Don't go too crazy with these AddComplexity. Try matching shufps with load
...
folding first.
llvm-svn: 30848
2006-10-09 21:42:15 +00:00
e646abb7b6
Don't convert to MOVLP if using shufps etc. may allow load folding.
...
llvm-svn: 30847
2006-10-09 21:39:25 +00:00
e71fe34d75
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
...
llvm-svn: 30844
2006-10-09 20:57:25 +00:00
9e29ec371a
add float -> double and double -> float conversion
...
llvm-svn: 30835
2006-10-09 17:50:29 +00:00
396b4a6b7b
add ADDS and ADCS
...
llvm-svn: 30830
2006-10-09 17:18:28 +00:00
e4c3276afc
expand ISD::SELECT
...
llvm-svn: 30829
2006-10-09 16:28:33 +00:00
c154dacb2f
add a note
...
llvm-svn: 30828
2006-10-09 14:18:33 +00:00
41730922bb
expand ISD::EXTLOAD
...
llvm-svn: 30827
2006-10-09 14:13:40 +00:00
78d6c2bf59
most ARM targets are little endian
...
llvm-svn: 30826
2006-10-09 14:12:15 +00:00
398195ebbe
completely disable folding of loads into scalar sse instructions and provide
...
a framework for doing it right. This fixes
CodeGen/X86/2006-10-07-ScalarSSEMiscompile.ll.
Once X86DAGToDAGISel::SelectScalarSSELoad is implemented right, this task
will be done.
llvm-svn: 30817
2006-10-07 21:55:32 +00:00
942009fee5
convert packed FP add/sub/mul/div to use a multiclass.
...
llvm-svn: 30815
2006-10-07 21:17:13 +00:00
4005f4e49c
one multiclass now defines all 8 variants of binary-scalar-sse-fp operations.
...
llvm-svn: 30814
2006-10-07 20:55:57 +00:00
6eaee2c8e3
Switch ADD/MUL/DIV/SUB scalarsse fp ops to a multiclass
...
llvm-svn: 30813
2006-10-07 20:35:44 +00:00
c8c6441821
Random acts of shrinkage
...
llvm-svn: 30812
2006-10-07 19:49:05 +00:00
b5df7e554d
Convert pand/por/pxor to use multiclass
...
llvm-svn: 30811
2006-10-07 19:37:30 +00:00
6138cba5f1
Convert some more instructions over to use a new multiclass.
...
Fix a bug where the asmstring for PSUBQrm was wrong.
llvm-svn: 30810
2006-10-07 19:34:33 +00:00
662ba43f08
Fix a bug where PADDQrm printed paddd instead of paddq.
...
llvm-svn: 30809
2006-10-07 19:15:46 +00:00
29c62a3c88
Add multiclass for SSE2 instructions that correspond to simple binops.
...
llvm-svn: 30808
2006-10-07 19:14:49 +00:00
e0928d9d7b
rename:
...
PDI_binop_rm -> PDI_binop_rm_int
PDI_binop_rmi -> PDI_binop_rmi_int
to make it clear that these are for use with intrinsics.
llvm-svn: 30807
2006-10-07 19:02:31 +00:00
489b63089d
Convert saturating PADD/PSUB's to use a multiclass
...
llvm-svn: 30806
2006-10-07 18:48:46 +00:00
fa2ce8824d
Convert PAVG*, PMADDWD, and PMUL* to use multiclasses.
...
llvm-svn: 30805
2006-10-07 18:39:00 +00:00
cab92e4c0c
Fix typo in packsswb instr definition, where the load had the wrong type.
...
This allows us to use the multiclass for other packs.
llvm-svn: 30804
2006-10-07 18:23:58 +00:00
b50938866b
implement FUITOS and FUITOD
...
llvm-svn: 30803
2006-10-07 14:24:52 +00:00
58c368bc4f
implement FLDD
...
llvm-svn: 30802
2006-10-07 14:03:39 +00:00
40f5dd27f0
implement fadds, faddd, fmuls and fmuld
...
llvm-svn: 30801
2006-10-07 13:46:42 +00:00
e746a9cd6a
handle pmin/pmax with multiclasses
...
llvm-svn: 30800
2006-10-07 07:49:33 +00:00
b14e6a0f8c
simplify pack and shift intrinsics with multiclasses
...
llvm-svn: 30797
2006-10-07 07:06:17 +00:00
521fc4e33f
Use a multiclass to simplify 'SSE2 Integer comparison'
...
llvm-svn: 30796
2006-10-07 06:47:08 +00:00
c6138cec61
move class defns close to uses to make it easier to read
...
llvm-svn: 30795
2006-10-07 06:33:36 +00:00
87e692323c
simplify horizontal op definitions
...
llvm-svn: 30794
2006-10-07 06:31:41 +00:00
3e9fc37458
remove more unneeded type info
...
llvm-svn: 30793
2006-10-07 06:27:03 +00:00
807be0a715
remove unneeded definitions and type info
...
llvm-svn: 30792
2006-10-07 06:19:41 +00:00
5b1358a8eb
remove some unneeded type info
...
llvm-svn: 30791
2006-10-07 06:17:43 +00:00
3414c022af
simplify patterns by merging in operand info
...
llvm-svn: 30790
2006-10-07 05:50:25 +00:00
ca21ce5f08
Factor operands into packed unary classes
...
llvm-svn: 30789
2006-10-07 05:47:20 +00:00
0052c3ff5b
remove dead/duplicate instructions
...
llvm-svn: 30788
2006-10-07 05:41:52 +00:00
904c6e9c92
Pull operand info up into parent class for scalar sse intrinsics.
...
llvm-svn: 30787
2006-10-07 05:26:13 +00:00
e698c90ee9
convert the sole sd unary intrinsic to a multiclass for consistency
...
llvm-svn: 30786
2006-10-07 05:19:31 +00:00
2bb2f050f5
pull operand string into the multiclass
...
llvm-svn: 30785
2006-10-07 05:13:26 +00:00
069679c7b6
Remove RSQRTSS[rm] RCPSS[rm], which are dead.
...
Introduce SS_IntUnary, a multiclass to replace SS_Int[rm].
llvm-svn: 30784
2006-10-07 05:09:48 +00:00
f13a7b376c
eliminate redundancy
...
llvm-svn: 30783
2006-10-07 04:52:09 +00:00
dc3064e223
Set the jt section
...
llvm-svn: 30781
2006-10-06 22:52:33 +00:00
21fa769867
Alpha uses a got
...
llvm-svn: 30778
2006-10-06 22:46:51 +00:00
aa2a12f1a2
add optional input flag to FMRRD
...
llvm-svn: 30774
2006-10-06 20:33:26 +00:00
671f25281d
add support for calling functions that return double
...
llvm-svn: 30771
2006-10-06 19:10:05 +00:00
5fe9680253
80 col violation.
...
llvm-svn: 30770
2006-10-06 18:57:51 +00:00
2421a179e4
ugly codegen
...
llvm-svn: 30769
2006-10-06 17:39:34 +00:00
ef01656ea4
fix some bugs affecting functions with no arguments
...
llvm-svn: 30767
2006-10-06 17:26:30 +00:00
6024ea8383
fix the stack alignment
...
llvm-svn: 30766
2006-10-06 14:29:47 +00:00
5fe7909e18
add support for calling functions that have double arguments
...
llvm-svn: 30765
2006-10-06 12:50:22 +00:00
ff1beda569
Still need to support -mcpu=<> or cross compilation will fail. Doh.
...
llvm-svn: 30764
2006-10-06 09:17:41 +00:00
9274f72e58
Do away with CPU feature list. Just use CPUID to detect MMX, SSE, SSE2, SSE3, and 64-bit support.
...
llvm-svn: 30763
2006-10-06 08:21:07 +00:00
4c1a804a5b
It appears the inline asm in GetCpuIDAndInfo() may clobbers some registers if it isn't inlined (at < -O3). Force it to be inlined.
...
llvm-svn: 30762
2006-10-06 07:50:56 +00:00
df9ac47e5e
Make use of getStore().
...
llvm-svn: 30759
2006-10-05 23:01:46 +00:00
decfeca52d
use a const ref for passing the vector to ArgumentLayout
...
llvm-svn: 30756
2006-10-05 17:46:48 +00:00
e04df41ca2
implement a ArgumentLayout class to factor code common to LowerFORMAL_ARGUMENTS and LowerCALL
...
implement FMDRR
add support for f64 function arguments
llvm-svn: 30754
2006-10-05 16:48:49 +00:00
f2ef243580
Lower some min/max idioms to minss/maxss when unsafe fp math is enabled.
...
llvm-svn: 30748
2006-10-05 04:11:26 +00:00
8cfd10eff3
Don't bother setting JumpTableTextSection, it is about to disappear
...
llvm-svn: 30745
2006-10-05 03:13:59 +00:00
a6a570e02f
Pass the MachineFunction into EmitJumpTableInfo.
...
llvm-svn: 30742
2006-10-05 03:01:21 +00:00
38e2c8a0a2
implement and use getSectionForFunction
...
llvm-svn: 30741
2006-10-05 02:51:36 +00:00
4431699187
Use getSectionForFunction.
...
llvm-svn: 30740
2006-10-05 02:49:23 +00:00
d4d255a408
Use getSectionForFunction
...
llvm-svn: 30739
2006-10-05 02:48:40 +00:00
c8c78982d4
use getSectionForFunction to decide which section to emit code into
...
llvm-svn: 30738
2006-10-05 02:47:13 +00:00
b82247b168
Implement getSectionForFunction, use it when printing function body.
...
llvm-svn: 30737
2006-10-05 02:43:52 +00:00
028d663ee6
Move getSectionForFunction to AsmPrinter, change it to return a string.
...
llvm-svn: 30735
2006-10-05 02:42:20 +00:00
0d236450aa
implement DarwinTargetAsmInfo::getSectionForFunction, use it when outputting
...
function bodies
llvm-svn: 30733
2006-10-05 00:35:50 +00:00
afe6d7a179
Give TargetAsmInfo a virtual dtor, add a new getSectionForFunction method.
...
llvm-svn: 30732
2006-10-05 00:35:16 +00:00
41e22a5419
emit jump table before debug info
...
llvm-svn: 30731
2006-10-05 00:26:05 +00:00
aad26a19f0
Always emit the jump table after the function so it's part of the same 'atom'
...
as the function body.
llvm-svn: 30730
2006-10-05 00:24:46 +00:00
8c5766ef3f
Added option -disable-x86-shuffle-opti to disable X86 specific vector shuffle optimizations.
...
llvm-svn: 30723
2006-10-04 18:33:38 +00:00
412aaabcbe
Formating.
...
llvm-svn: 30722
2006-10-04 18:33:00 +00:00
9259b1efb6
Pattern match min/max nodes when we have sse. This implements
...
CodeGen/X86/scalar_sse_minmax.ll
llvm-svn: 30719
2006-10-04 06:57:07 +00:00
3e11d99a0a
add a note :(
...
llvm-svn: 30717
2006-10-04 05:52:13 +00:00
5d9fd977d3
Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
...
extra operand to LOADX to specify the exact value extension type.
llvm-svn: 30714
2006-10-04 00:56:09 +00:00
68d238801c
Implement floating point constants
...
llvm-svn: 30704
2006-10-03 17:27:58 +00:00
f598d73142
Fix PR933 and CodeGen/X86/2006-10-02-BoolRetCrash.ll
...
llvm-svn: 30703
2006-10-03 17:18:42 +00:00
a36e6cf44f
These don't have immediate operands.
...
llvm-svn: 30694
2006-10-03 06:55:11 +00:00
d55c0a41df
fix the names of the 64bit fp register
...
initial support for returning 64bit floating point numbers
llvm-svn: 30692
2006-10-02 19:30:56 +00:00
1212b4d249
Not needed.
...
llvm-svn: 30674
2006-09-29 22:05:10 +00:00
53f78be49e
add floating point registers
...
implement SINT_TO_FP
llvm-svn: 30673
2006-09-29 21:20:16 +00:00
d9e4bf5285
update comments
...
llvm-svn: 30663
2006-09-28 23:33:12 +00:00
d32cb5ee7f
wrap long lines
...
llvm-svn: 30662
2006-09-28 23:32:43 +00:00
0045295c18
Simplify some code, reformat break's
...
llvm-svn: 30660
2006-09-28 23:19:29 +00:00
78370606d0
Shift amounts are always 32-bits, even in 64-bit mode. This fixes
...
CodeGen/PowerPC/2006-09-28-shift_64.ll
llvm-svn: 30652
2006-09-28 20:48:45 +00:00
3cbd1604f8
add a note about a general improvement to the code generator
...
llvm-svn: 30642
2006-09-28 06:01:17 +00:00
fc36039f86
silence warnings in release build
...
llvm-svn: 30631
2006-09-27 18:29:38 +00:00
67f8cc51f4
Use abstract private/comment directives, to increase portability to ppc/linux
...
llvm-svn: 30621
2006-09-27 02:55:21 +00:00
104aa5dbc1
Various random and minor code cleanups.
...
llvm-svn: 30608
2006-09-26 03:57:53 +00:00
ad4e7eb59e
Compile:
...
int x __attribute__((used));
to:
.data
.comm _x,4 ; 'x'
.no_dead_strip _x
on both x86 and ppc darwin targets.
llvm-svn: 30605
2006-09-26 03:39:53 +00:00
66af390631
Add support for targets that want to do something with the llvm.used list,
...
because they have an aggressive linker that does dead code stripping.
llvm-svn: 30604
2006-09-26 03:38:18 +00:00
f11327daab
more notes
...
llvm-svn: 30598
2006-09-25 17:12:14 +00:00
5e2bacd6be
Fix jump tables to match gcc (and the ABI and whatnot)
...
llvm-svn: 30594
2006-09-24 19:46:56 +00:00
783a4a9d86
Add support for other relocation bases to jump tables, as well as custom asm directives
...
llvm-svn: 30593
2006-09-24 19:45:58 +00:00
68324f8f85
jump table note
...
llvm-svn: 30591
2006-09-24 13:13:10 +00:00
1da0ab2f58
Delete dead code; fix 80 col violations.
...
llvm-svn: 30583
2006-09-22 21:43:59 +00:00
72d4c070c0
add a note
...
llvm-svn: 30581
2006-09-22 11:36:17 +00:00
d31efd190f
Fold AND and ROTL more often
...
llvm-svn: 30577
2006-09-22 05:01:56 +00:00
7b700e517a
more condition codes
...
llvm-svn: 30567
2006-09-21 13:06:26 +00:00
0c71a5adc8
if a constant can't be an immediate, add it to the constant pool
...
llvm-svn: 30566
2006-09-21 11:29:52 +00:00
08a8ccaaf1
implemented
...
llvm-svn: 30559
2006-09-21 06:14:54 +00:00
1c18c0db79
Fit in 80-cols
...
llvm-svn: 30556
2006-09-21 05:46:00 +00:00
c68bbef874
Fix compile error.
...
llvm-svn: 30553
2006-09-21 02:08:31 +00:00
3c5b3df6a0
Adding codegeneration for StdCall & FastCall calling conventions
...
llvm-svn: 30549
2006-09-20 22:03:51 +00:00
ccdaecc448
Account for pseudo-ops correctly
...
llvm-svn: 30548
2006-09-20 20:08:52 +00:00
a81a75c390
The DarwinAsmPrinter need not check for isDarwin. createPPCAsmPrinterPass
...
should create the right asmprinter subclass.
llvm-svn: 30542
2006-09-20 17:12:19 +00:00
8597a2fc4e
Wrap some darwin'isms with isDarwin checks.
...
llvm-svn: 30541
2006-09-20 17:07:15 +00:00
f007f21c8a
catch constants more often
...
llvm-svn: 30534
2006-09-20 15:05:49 +00:00
97a4e99aff
clarify with test case
...
llvm-svn: 30531
2006-09-20 14:48:00 +00:00
e2d138a462
Add Note
...
llvm-svn: 30530
2006-09-20 14:40:01 +00:00
fba9e8f422
item done
...
llvm-svn: 30518
2006-09-20 06:41:56 +00:00
27d8985a71
add a note
...
llvm-svn: 30515
2006-09-20 06:32:10 +00:00
f62f090ea1
This is already done
...
llvm-svn: 30512
2006-09-20 04:59:33 +00:00
da9b1a9322
Improve PPC64 equality comparisons like PPC32 comparisons.
...
llvm-svn: 30510
2006-09-20 04:33:27 +00:00
aa3926b7ea
Two improvements:
...
1. Codegen this comparison:
if (X == 0x8000)
as:
cmplwi cr0, r3, 32768
bne cr0, LBB1_2 ;cond_next
instead of:
lis r2, 0
ori r2, r2, 32768
cmpw cr0, r3, r2
bne cr0, LBB1_2 ;cond_next
2. Codegen this comparison:
if (X == 0x12345678)
as:
xoris r2, r3, 4660
cmplwi cr0, r2, 22136
bne cr0, LBB1_2 ;cond_next
instead of:
lis r2, 4660
ori r2, r2, 22136
cmpw cr0, r3, r2
bne cr0, LBB1_2 ;cond_next
llvm-svn: 30509
2006-09-20 04:25:47 +00:00
ab33d350a7
Add a note that we should match rlwnm better
...
llvm-svn: 30508
2006-09-20 03:59:25 +00:00
601b86513d
Legalize is no longer limited to cleverness with just constant shift amounts.
...
Allow it to be clever when possible and fall back to the gross code when needed.
This allows us to compile:
long long foo1(long long X, int C) {
return X << (C|32);
}
long long foo2(long long X, int C) {
return X << (C&~32);
}
to:
_foo1:
rlwinm r2, r5, 0, 27, 31
slw r3, r4, r2
li r4, 0
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
slw r3, r3, r2
srw r5, r4, r5
or r3, r3, r5
slw r4, r4, r2
blr
instead of:
_foo1:
ori r2, r5, 32
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
.globl _foo2
.align 4
_foo2:
rlwinm r2, r5, 0, 27, 25
subfic r5, r2, 32
addi r6, r2, -32
srw r5, r4, r5
slw r3, r3, r2
slw r6, r4, r6
or r3, r3, r5
slw r4, r4, r2
or r3, r3, r6
blr
llvm-svn: 30507
2006-09-20 03:47:40 +00:00
fa7217f970
fix header
...
add comments
untabify
llvm-svn: 30486
2006-09-19 16:41:40 +00:00
f7d4a9900c
Implement a MachineFunctionPass to fix the mul instruction
...
llvm-svn: 30485
2006-09-19 15:49:25 +00:00
b94df039c0
item done
...
llvm-svn: 30483
2006-09-19 06:19:03 +00:00
3c48ea54ee
Fold the PPCISD shifts when presented with 0 inputs. This occurs for code
...
like:
long long test(long long X, int Y) {
return 1ULL << Y;
}
long long test2(long long X, int Y) {
return -1LL << Y;
}
which we used to compile to:
_test:
li r2, 1
subfic r3, r5, 32
li r4, 0
addi r6, r5, -32
srw r3, r2, r3
slw r4, r4, r5
slw r6, r2, r6
or r3, r4, r3
slw r4, r2, r5
or r3, r3, r6
blr
_test2:
li r2, -1
subfic r3, r5, 32
addi r6, r5, -32
srw r3, r2, r3
slw r4, r2, r5
slw r2, r2, r6
or r3, r4, r3
or r3, r3, r2
blr
Now we produce:
_test:
li r2, 1
addi r3, r5, -32
subfic r4, r5, 32
slw r3, r2, r3
srw r4, r2, r4
or r3, r4, r3
slw r4, r2, r5
blr
_test2:
li r2, -1
subfic r3, r5, 32
addi r6, r5, -32
srw r3, r2, r3
slw r4, r2, r5
slw r2, r2, r6
or r3, r4, r3
or r3, r3, r2
blr
llvm-svn: 30479
2006-09-19 05:22:59 +00:00
f23e3bfcb2
A pass to remove the worst of the replay trap offenders, and as a bonus, align basic blocks when it is free to do so
...
llvm-svn: 30467
2006-09-18 19:44:29 +00:00
3aa3ad780e
Jump tables on Alpha
...
llvm-svn: 30463
2006-09-18 18:01:03 +00:00
523dbc5c19
add a note. Our 64-bit shifts are ~30% slower than gcc's
...
llvm-svn: 30457
2006-09-18 05:36:54 +00:00
4a13d3b391
This is closer to what we really want.
...
llvm-svn: 30451
2006-09-18 04:54:35 +00:00
6f7072c66a
Added some eye-candy for Subtarget type checking
...
Added X86 StdCall & FastCall calling conventions. Codegen will follow.
llvm-svn: 30446
2006-09-17 20:25:45 +00:00
0ab01ff6e2
Small fixes for supporting dll* linkage types
...
llvm-svn: 30441
2006-09-17 13:06:18 +00:00
f7e3478745
add a note noticed through source inspection
...
llvm-svn: 30418
2006-09-16 23:57:51 +00:00
63b113f68c
add a note
...
llvm-svn: 30406
2006-09-16 03:30:19 +00:00
c9dc375d3e
add a nate note
...
llvm-svn: 30399
2006-09-15 20:31:36 +00:00
f8464da015
Remove a unnecessary check.
...
llvm-svn: 30382
2006-09-14 23:55:02 +00:00
2aa98e0363
add a note
...
llvm-svn: 30377
2006-09-14 20:56:30 +00:00
d61d39ec53
Adding dllimport, dllexport and external weak linkage types.
...
DLL* linkages got full (I hope) codegeneration support in C & both x86
assembler backends.
External weak linkage added for future use, we don't provide any
codegeneration, etc. support for it.
llvm-svn: 30374
2006-09-14 18:23:27 +00:00
1463377ddb
add note about switch lowering
...
llvm-svn: 30308
2006-09-13 23:37:16 +00:00
92e5113d48
Skip over first operand when determining REX prefix for two-address code.
...
llvm-svn: 30300
2006-09-13 19:07:28 +00:00
971e33930d
Turn X < 0 -> TEST X,X js
...
llvm-svn: 30294
2006-09-13 17:04:54 +00:00
0c9ae46c5f
The sense of this branch was inverted :(
...
llvm-svn: 30293
2006-09-13 16:56:12 +00:00
3130a756ef
add shifts to addressing mode 1
...
llvm-svn: 30291
2006-09-13 12:09:43 +00:00
706dd3e0d4
Fix a regression in the 32-bit port from the 64-bit port landing.
...
We now compile CodeGen/X86/lea-2.ll into:
_test:
movl 4(%esp), %eax
movl 8(%esp), %ecx
leal -5(%ecx,%eax,4), %eax
ret
instead of:
_test:
movl 4(%esp), %eax
leal (,%eax,4), %eax
addl 8(%esp), %eax
addl $4294967291, %eax
ret
llvm-svn: 30288
2006-09-13 04:45:25 +00:00
e413fea6ac
new note
...
llvm-svn: 30286
2006-09-13 04:19:50 +00:00
3496710f25
new note
...
llvm-svn: 30285
2006-09-13 03:54:54 +00:00
7a627676be
Compile X > -1 -> text X,X; js dest
...
This implements CodeGen/X86/jump_sign.ll.
llvm-svn: 30283
2006-09-13 03:22:10 +00:00
9a083a4121
Reflects MachineConstantPoolEntry changes.
...
llvm-svn: 30279
2006-09-12 21:04:05 +00:00
cfb2c32724
add a note
...
llvm-svn: 30271
2006-09-12 06:36:01 +00:00
8b4de218d9
Testcase noticed from PR906
...
llvm-svn: 30269
2006-09-11 23:00:56 +00:00
6e7286f72a
add compilable testcase
...
llvm-svn: 30268
2006-09-11 22:57:51 +00:00
c7829d62c0
implement SRL and MUL
...
llvm-svn: 30262
2006-09-11 19:24:19 +00:00
bccf9c2f1b
add the correct fallback for ARMDAGToDAGISel::SelectAddrMode1
...
llvm-svn: 30261
2006-09-11 19:23:32 +00:00
e45a79a9e2
partial implementation of the ARM Addressing Mode 1
...
llvm-svn: 30252
2006-09-11 17:25:40 +00:00
ecb0d686f8
call AsmPrinter::doInitialization in ARMAsmPrinter::doInitialization
...
llvm-svn: 30246
2006-09-11 12:49:38 +00:00
21a75acc3e
Updates.
...
llvm-svn: 30245
2006-09-11 05:35:17 +00:00
9e77d9a96b
Update README file.
...
llvm-svn: 30244
2006-09-11 05:25:15 +00:00
4259a0f654
X86ISD::CMP now produces a chain as well as a flag. Make that the chain
...
operand of a conditional branch to allow load folding into CMP / TEST
instructions.
llvm-svn: 30241
2006-09-11 02:19:56 +00:00
a0d95a8da9
Behold, more work on relocations. Things are looking pretty good now.
...
llvm-svn: 30240
2006-09-10 23:03:44 +00:00
fbee8bfe48
Removed unnecessary Mangler creation.
...
llvm-svn: 30239
2006-09-10 21:17:03 +00:00
fdb3a75942
Add cbe support for powi
...
llvm-svn: 30226
2006-09-09 06:17:12 +00:00
69df6132d7
First pass at supporting relocations. Relocations are written correctly to
...
the file now, however the relocated address is currently wrong. Fixing
that will require some deep pondering.
llvm-svn: 30207
2006-09-08 22:42:09 +00:00
de33f66286
Fixed a FuseTwoAddrInst() bug: consider GlobalAddress and JumpTableIndex
...
in addition to immediate operands.
llvm-svn: 30205
2006-09-08 21:08:13 +00:00
d11fb5d13b
implement shl and sra
...
llvm-svn: 30191
2006-09-08 17:36:23 +00:00
6c003a7c2d
Use __USER_LABEL_PREFIX__ to get the prefix added by the current host.
...
llvm-svn: 30190
2006-09-08 17:03:56 +00:00
4443c7d60a
add the eor (xor) instruction
...
llvm-svn: 30189
2006-09-08 16:59:47 +00:00
177405376c
Missing tab
...
llvm-svn: 30188
2006-09-08 13:06:56 +00:00
778769aafb
implement unconditional branches
...
fix select.ll
llvm-svn: 30186
2006-09-08 12:47:03 +00:00
7348403d42
Remove TEST64mr. It's same as TEST64rm since and is commutative.
...
llvm-svn: 30178
2006-09-08 06:56:55 +00:00
11b0a5dbd4
Committing X86-64 support.
...
llvm-svn: 30177
2006-09-08 06:48:29 +00:00
c9db83306f
We actually do support object file writing, so don't return true (error)
...
llvm-svn: 30173
2006-09-08 03:42:15 +00:00
89c5d04b9b
- Identify a vector_shuffle that can be turned into an undef, e.g.
...
shuffle V1, <undef>, <undef, undef, 4, 5>
- Fix some suspicious logic into LowerVectorShuffle that cause less than
optimal code by failing to identify MOVL (move to lowest element of a
vector).
llvm-svn: 30171
2006-09-08 01:50:06 +00:00
ae92ce8798
1. Remove condition on delete.
...
2. Protect and outline createTargetAsmInfo.
3. Misc. kruft.
llvm-svn: 30169
2006-09-07 23:39:26 +00:00
2785d55446
add a new value for the command line optn
...
llvm-svn: 30165
2006-09-07 22:32:28 +00:00
b9e0a9e82f
Fix a cross-build issue. The asmsyntax shouldn't be affected by the build
...
host, it should be affected by the target. Allow the command line option to
override in either case.
llvm-svn: 30164
2006-09-07 22:29:41 +00:00
261779bb45
Make target asm info a property of the target machine.
...
llvm-svn: 30162
2006-09-07 22:06:40 +00:00
0e83541f8b
Break out target asm info into separate files.
...
llvm-svn: 30161
2006-09-07 22:05:02 +00:00
dc4ff5311f
Eliminate X86ISD::TEST, using X86ISD::CMP instead. Match X86ISD::CMP patterns
...
using test, which provides nice simplifications like:
- movl %edi, %ecx
- andl $2, %ecx
- cmpl $0, %ecx
+ testl $2, %edi
je LBB1_11 #cond_next90
There are a couple of dagiselemitter deficiencies that this exposes, they will
be handled later.
llvm-svn: 30156
2006-09-07 20:33:45 +00:00
1b7f09cdf7
Some notes on better load folding we could do
...
llvm-svn: 30155
2006-09-07 20:32:01 +00:00
a9411c0977
Consistency.
...
llvm-svn: 30152
2006-09-07 19:03:48 +00:00
c7abe471fe
Make the x86 asm flavor part of the subtarget info.
...
llvm-svn: 30146
2006-09-07 12:23:47 +00:00
7f3f0973e6
Clean up.
...
llvm-svn: 30140
2006-09-07 01:17:57 +00:00
4c7a3fbdea
Watch out for variable_ops instructions.
...
llvm-svn: 30135
2006-09-06 20:32:45 +00:00
ac22e54131
Variable ops instructions may ignore the last few operands for code emission.
...
llvm-svn: 30134
2006-09-06 20:24:14 +00:00
ef94ebb666
Oops - forgot to update banner.
...
llvm-svn: 30131
2006-09-06 19:21:41 +00:00
681ecbb3b3
Separate target specifc asm properties from asm printers.
...
llvm-svn: 30127
2006-09-06 18:35:33 +00:00
a6211dcdad
Separate target specific asm properties from the asm printers.
...
llvm-svn: 30126
2006-09-06 18:34:40 +00:00
abd8bcbe5e
add the orr instruction
...
llvm-svn: 30125
2006-09-06 18:03:12 +00:00
2656932979
Bugfix to work with the two-addr changes that have been made in the tree recently
...
llvm-svn: 30121
2006-09-05 20:27:32 +00:00
7a150d3113
Fix a few dejagnu failures. e.g. fast-cc-merge-stack-adj.ll
...
llvm-svn: 30113
2006-09-05 08:32:49 +00:00
17c28b2e0e
JIT encoding bug.
...
llvm-svn: 30112
2006-09-05 05:59:25 +00:00
e3d2e1e41e
Update the X86 JIT to make it work with the new two-addr changes. This also
...
adds assertions that check to make sure every operand gets emitted.
llvm-svn: 30110
2006-09-05 02:52:35 +00:00
af23f9b5f6
Completely eliminate def&use operands. Now a register operand is EITHER a
...
def operand or a use operand.
llvm-svn: 30109
2006-09-05 02:31:13 +00:00
13a5dcddce
Fix a long-standing wart in the code generator: two-address instruction lowering
...
actually *removes* one of the operands, instead of just assigning both operands
the same register. This make reasoning about instructions unnecessarily complex,
because you need to know if you are before or after register allocation to match
up operand #'s with the target description file.
Changing this also gets rid of a bunch of hacky code in various places.
This patch also includes changes to fold loads into cmp/test instructions in
the X86 backend, along with a significant simplification to the X86 spill
folding code.
llvm-svn: 30108
2006-09-05 02:12:02 +00:00
3852b2ce7e
jmp_bufs are this big on alpha.
...
llvm-svn: 30107
2006-09-05 00:22:25 +00:00
8386105f3f
add support for returning 64bit values
...
llvm-svn: 30103
2006-09-04 19:05:01 +00:00
49c45d3a13
Fix some X86 JIT failures. This should really come from TargetJITInfo.
...
llvm-svn: 30102
2006-09-04 18:48:41 +00:00
cf6749e4c0
add setJumpBufSize() and setJumpBufAlignment() to target-lowering.
...
Call these from your backend to enjoy setjmp/longjmp goodness, see
lib/Target/IA64/IA64ISelLowering.cpp for an example
llvm-svn: 30095
2006-09-04 06:21:35 +00:00
12e97307a1
Completely rearchitect the interface between targets and the pass manager.
...
This pass:
1. Splits TargetMachine into TargetMachine (generic targets, can be implemented
any way, like the CBE) and LLVMTargetMachine (subclass of TM that is used by
things using libcodegen and other support).
2. Instead of having each target fully populate the passmgr for file or JIT
output, move all this to common code, and give targets hooks they can
implement.
3. Commonalize the target population stuff between file emission and JIT
emission.
4. All (native code) codegen stuff now happens in a FunctionPassManager, which
paves the way for "fast -O0" stuff in the CFE later, and now LLC could
lazily stream .bc files from disk to use less memory.
5. There are now many fewer #includes and the targets don't depend on the
scalar xforms or libanalysis anymore (but codegen does).
6. Changing common code generator pass ordering stuff no longer requires
touching all targets.
7. The JIT now has the option of "-fast" codegen or normal optimized codegen,
which is now orthogonal to the fact that JIT'ing is being done.
llvm-svn: 30081
2006-09-04 04:14:57 +00:00
e8ce162969
Add accessor
...
llvm-svn: 30080
2006-09-04 04:08:58 +00:00
2f93c0fd33
remove #include
...
llvm-svn: 30078
2006-09-04 04:06:01 +00:00
0fc4541c67
Simplify target construction.
...
llvm-svn: 30070
2006-09-03 18:44:02 +00:00
5328ba96e1
add the SETULT condition code
...
llvm-svn: 30067
2006-09-03 13:19:16 +00:00
c585b6919b
add more condition codes
...
llvm-svn: 30056
2006-09-02 20:24:25 +00:00
2c4e0f120f
Oops. Bad typo. Without the check of N1.hasOneUse() bad things can happen.
...
Suppose the TokenFactor can reach the Op:
[Load chain]
^
|
[Load]
^ ^
| |
/ \-
/ |
/ [Op]
/ ^ ^
| .. |
| / |
[TokenFactor] |
^ |
| |
\ /
\ /
[Store]
If we move the Load below the TokenFactor, we would have created a cycle in
the DAG.
llvm-svn: 30040
2006-09-01 22:52:28 +00:00
bad9d2ee49
Use a couple of multiclass patterns to factor some integer ops.
...
llvm-svn: 30039
2006-09-01 22:28:02 +00:00
38e6d1d5af
remove a bunch of comments
...
llvm-svn: 30038
2006-09-01 22:16:22 +00:00
6d464146d0
Minor asm fix.
...
llvm-svn: 29965
2006-08-29 22:14:48 +00:00
b28800f4d5
Remove dead code.
...
llvm-svn: 29962
2006-08-29 21:42:58 +00:00
dfb85155dc
Don't performance load/op/store transformation if op produces a floating point
...
or vector result. X86 does not have load/mod/store variants of those
instructions.
llvm-svn: 29957
2006-08-29 18:37:37 +00:00
358b9ed98a
- Enable x86 isel preprocessing by default unless -fast is specified.
...
- Also disable isel load folding if -fast.
llvm-svn: 29956
2006-08-29 18:28:33 +00:00
2eebe8b05e
Handle callee saved registers in dwarf frame info (lead up to exception
...
handling.)
llvm-svn: 29954
2006-08-29 16:24:26 +00:00
82dc16c0a7
Tidy up options.
...
llvm-svn: 29953
2006-08-29 15:13:10 +00:00
c07feb14b0
Avoid making unneeded load/mod/store transformation which can hurt performance.
...
llvm-svn: 29952
2006-08-29 06:44:17 +00:00
18f0329cfc
Make ppc64 jit kinda work right. About 2/3 of Olden passes with this,
...
there are clearly some encoding bugs lurking in there somewhere.
llvm-svn: 29949
2006-08-29 02:30:59 +00:00
00884b51c5
On Mac, print jump table entries after the function to work around a linker issue.
...
llvm-svn: 29946
2006-08-28 22:14:16 +00:00
64a9e28846
Add an optional pass to preprocess the DAG before x86 isel to allow selecting more load/mod/store instructions.
...
llvm-svn: 29943
2006-08-28 20:10:17 +00:00
e7141c8be6
For PR387:
...
Close out this long standing bug by removing the remaining overloaded
virtual functions in LLVM. The -Woverloaded-virtual option is now turned on.
llvm-svn: 29934
2006-08-28 01:02:49 +00:00
3d27be1333
s|llvm/Support/Visibility.h|llvm/Support/Compiler.h|
...
llvm-svn: 29911
2006-08-27 12:54:02 +00:00
c3acfc0b10
Do not use getTargetNode() and SelectNodeTo() which takes more than 3
...
SDOperand arguments. Use the variants which take an array and number instead.
llvm-svn: 29907
2006-08-27 08:14:06 +00:00
4042e871ce
Fix target matching weights, so that ppc-darwin modules are codegen with the
...
ppc target, not the itanium target, when run on an itanium machine.
This should fix the CodeGen/PowerPC regtest failures on itanium.
llvm-svn: 29903
2006-08-26 21:33:05 +00:00
34b70eea5c
SelectNodeTo now returns a SDNode*.
...
llvm-svn: 29901
2006-08-26 08:00:10 +00:00
61413a3d72
Select() no longer require Result operand by reference.
...
llvm-svn: 29898
2006-08-26 05:34:46 +00:00
ab8297f92d
Match tblgen changes.
...
llvm-svn: 29895
2006-08-26 01:07:58 +00:00
2d48722e92
Match tblgen changes; clean up.
...
llvm-svn: 29894
2006-08-26 01:05:16 +00:00
c664efe223
Give a good error message when we try to jit inline asm.
...
llvm-svn: 29891
2006-08-26 00:47:03 +00:00
1b200574ad
Add a comment.
...
llvm-svn: 29889
2006-08-25 23:29:06 +00:00
d7572fb234
Encode pc-relative conditional branch offset as pc+(num of bytes / 4). The
...
asm printer will print it as offset*4. e.g. bne cr0, $+8.
The PPC code emitter was expecting the offset to be number of instructions, not
number of bytes. This fixes a whole bunch of JIT failures.
llvm-svn: 29885
2006-08-25 21:54:44 +00:00
d51ce619c3
Fix some comments.
...
llvm-svn: 29880
2006-08-25 19:40:59 +00:00
98dc23fd1f
use @ for comments
...
store LR in an arbitrary stack slot
add support for writing varargs functions
llvm-svn: 29876
2006-08-25 17:55:16 +00:00
ac40a81253
We compile this into:
...
_swap_16:
slwi r2, r3, 24
rlwimi r2, r3, 8, 8, 15
srwi r3, r2, 16
blr
now.
llvm-svn: 29864
2006-08-24 23:06:02 +00:00
fb6bc15d5d
Owen implemented this.
...
llvm-svn: 29863
2006-08-24 23:03:33 +00:00
29e4875f57
add the "eq" condition code
...
implement a movcond instruction
llvm-svn: 29857
2006-08-24 17:19:08 +00:00
fe03fe9bf4
create a generic bcond instruction that has a conditional code argument
...
llvm-svn: 29856
2006-08-24 16:13:15 +00:00
e08b9853cc
initial support for branches
...
llvm-svn: 29854
2006-08-24 13:45:55 +00:00
3cb3921a60
Initial checkin of the Mach-O emitter. There's plenty of fixmes, but it
...
does emit linkable .o files in very simple cases.
llvm-svn: 29850
2006-08-23 21:08:52 +00:00
ea500426d6
add a README.txt
...
llvm-svn: 29814
2006-08-22 12:22:46 +00:00
d0dee77718
initial support for select
...
llvm-svn: 29802
2006-08-21 22:00:32 +00:00
9d77f9fd24
add the and instruction
...
llvm-svn: 29793
2006-08-21 13:58:59 +00:00
8a675a5d09
call computeRegisterProperties
...
llvm-svn: 29780
2006-08-20 01:49:49 +00:00
60f1eecd3a
Constify some methods. Patch provided by Anton Vayvod, thanks!
...
llvm-svn: 29756
2006-08-17 22:00:08 +00:00
162f2d5d4c
Revert this patch, the front-end has been fixed to make it unneccesary.
...
llvm-svn: 29752
2006-08-17 18:43:24 +00:00
dfb3f0591d
'g' is handled by the front-end.
...
llvm-svn: 29751
2006-08-17 18:12:28 +00:00
4a063c5ffb
Fix handling of 'g'. Closes 883
...
llvm-svn: 29750
2006-08-17 17:50:12 +00:00
c3ed77e1b9
add a "load effective address"
...
llvm-svn: 29748
2006-08-17 17:09:40 +00:00
1c3210d08d
Add the 'c' constraint as needed by the linux kernel
...
llvm-svn: 29747
2006-08-17 16:07:50 +00:00
fc60fb974c
Add support for S and D constraints, as needed to compile the linux kernel.
...
llvm-svn: 29746
2006-08-17 15:35:43 +00:00
29ab7c42a8
Doh. Incorrectly inverted condition. Also add a isOnlyUse check to match tablegen.
...
llvm-svn: 29741
2006-08-16 23:59:00 +00:00
bf8e751488
Declare the callee saved regs
...
Remove the hard coded store and load of the link register
Implement ARMFrameInfo
llvm-svn: 29727
2006-08-16 14:43:33 +00:00
63d178f473
SelectNodeTo() may return a SDOperand that is different from the input.
...
llvm-svn: 29726
2006-08-16 07:30:09 +00:00
f2a7d5768a
RET_FLAG has an optional input flag, but it does not produce a flag result.
...
llvm-svn: 29725
2006-08-16 07:28:58 +00:00
08a5f38c5c
add a note
...
llvm-svn: 29722
2006-08-16 02:47:44 +00:00
bc485fdc4c
Fix PowerPC/2006-08-15-SelectionCrash.ll and simplify selection code.
...
llvm-svn: 29715
2006-08-15 23:48:22 +00:00
157971b04a
select code like
...
ldr rx, [ry, #offset]
llvm-svn: 29664
2006-08-14 19:01:24 +00:00
984c1a4a8f
Emit .set directives for jump table entries when possible, which reduces
...
the number of relocations in object files, shrinkifying them.
llvm-svn: 29650
2006-08-12 21:29:52 +00:00
095e4ad2ea
Fix a bug in a recent refactoring that broke a bunch of stuff.
...
llvm-svn: 29649
2006-08-12 07:20:05 +00:00
20b461a97f
eliminate extraneous blank line
...
llvm-svn: 29627
2006-08-11 21:08:16 +00:00
ed728e8dc9
Eliminate use of getNode that takes a vector.
...
llvm-svn: 29614
2006-08-11 17:38:39 +00:00
c62914880f
elimiante use of getNode that takes vector of operands.
...
llvm-svn: 29612
2006-08-11 17:22:35 +00:00
56565b5cb9
eliminate use of getNode that takes vector of operands.
...
llvm-svn: 29611
2006-08-11 17:21:12 +00:00
2aa76cf371
eliminate use of getNode that takes vector<SDOperand>. Wrap a really long line.
...
llvm-svn: 29610
2006-08-11 17:19:54 +00:00
d66f14e846
Convert vectors to fixed sized arrays and smallvectors. Eliminate use of getNode that takes a vector.
...
llvm-svn: 29609
2006-08-11 17:18:05 +00:00
66f1fbaaad
Fix miscompilation of float vector returns. Compile code to this:
...
_func:
vsldoi v2, v3, v2, 12
vsldoi v2, v2, v2, 4
blr
instead of:
_func:
vsldoi v2, v3, v2, 12
vsldoi v2, v2, v2, 4
*** vor f1, v2, v2
blr
llvm-svn: 29607
2006-08-11 16:47:32 +00:00
bd1c5a8fb8
Match tablegen changes.
...
llvm-svn: 29604
2006-08-11 09:08:15 +00:00
81b645a76b
CALLSEQ_* produces chain even if that's not needed.
...
llvm-svn: 29603
2006-08-11 09:03:33 +00:00
5c68bba085
Convert more calls of getNode() that takes a vector to pass in the start of an array.
...
llvm-svn: 29601
2006-08-11 07:35:45 +00:00
1c41fc9b06
correctly set LocalAreaOffset of TargetFrameInfo
...
llvm-svn: 29589
2006-08-09 17:37:45 +00:00
f5ce475540
fix the spill code
...
llvm-svn: 29583
2006-08-09 16:41:12 +00:00
58159b36a3
fix the loading of the link register in emitepilogue
...
llvm-svn: 29580
2006-08-09 13:15:47 +00:00
8c41f99e6f
change the addressing mode of the str instruction to reg+imm
...
llvm-svn: 29571
2006-08-08 20:35:03 +00:00
39083e7836
initial support for variable number of arguments
...
llvm-svn: 29567
2006-08-08 13:02:29 +00:00
c24a1d3093
Start eliminating temporary vectors used to create DAG nodes. Instead, pass
...
in the start of an array and a count of operands where applicable. In many
cases, the number of operands is known, so this static array can be allocated
on the stack, avoiding the heap. In many other cases, a SmallVector can be
used, which has the same benefit in the common cases.
I updated a lot of code calling getNode that takes a vector, but ran out of
time. The rest of the code should be updated, and these methods should be
removed.
We should also do the same thing to eliminate the methods that take a
vector of MVT::ValueTypes.
It would be extra nice to convert the dagiselemitter to avoid creating vectors
for operands when calling getTargetNode.
llvm-svn: 29566
2006-08-08 02:23:42 +00:00
72bb66a4b8
Eliminate reachability matrix. It has to be calculated before any instruction
...
selection is done. That's rather expensive especially in situations where it
isn't really needed.
Move back to a searching the predecessors, but make use of topological order
to trim the search space.
llvm-svn: 29559
2006-08-08 00:31:00 +00:00
b9d34bd098
Match tablegen isel changes.
...
llvm-svn: 29549
2006-08-07 22:28:20 +00:00
d5e38e017c
Make XMM, FP register dwarf register numbers consistent with gcc.
...
llvm-svn: 29543
2006-08-07 21:02:39 +00:00
2bcb8c0f05
use a 'register pressure reducing' scheduler
...
make sure only one move is used in a hello world
llvm-svn: 29520
2006-08-04 12:48:42 +00:00
e19f6fde2d
Bug fix: always generate a RET_FLAG in LowerRET
...
fixes ret_null.ll and call.ll
llvm-svn: 29519
2006-08-03 22:50:11 +00:00
fef2c5f0a2
remove some more dead sparcv9 support stuff
...
llvm-svn: 29506
2006-08-03 18:55:44 +00:00
682ff0dd15
remove a dead proto
...
llvm-svn: 29505
2006-08-03 18:51:04 +00:00
f2c14591e6
Get darwin intel debugging up and running.
...
llvm-svn: 29504
2006-08-03 17:27:09 +00:00
a94b9e33af
add and use ARMISD::RET_FLAG
...
llvm-svn: 29499
2006-08-03 17:02:20 +00:00
8f585196e1
Reflect change to AssignTopologicalOrder().
...
llvm-svn: 29480
2006-08-02 22:01:32 +00:00
8101dd67d1
Use of vector<bool> causes some horrendous compile time regression (2x)!
...
Looks like libstdc++ implementation does not scale very well. Switch back
to using directly managed arrays.
llvm-svn: 29469
2006-08-02 09:18:33 +00:00
6025c92e50
Update the readme to remove duplicate information and clarify the loop
...
problem.
llvm-svn: 29468
2006-08-02 05:31:20 +00:00
d573cc7938
Disable LSR at -fast
...
llvm-svn: 29467
2006-08-02 05:29:40 +00:00
8b7bd8264b
start comments with #
...
move the constant pool to .text
correctly print loads of labels
mark R0, R1, R2 and R3 as caller save
llvm-svn: 29451
2006-08-01 18:53:10 +00:00
95035cf001
implement LowerConstantPool and LowerGlobalAddress
...
llvm-svn: 29433
2006-08-01 12:58:43 +00:00
45af287957
Factor topological order code to SelectionDAG. Clean up.
...
llvm-svn: 29430
2006-08-01 08:17:22 +00:00
524129dd64
Fix PR850 and CodeGen/X86/2006-07-31-SingleRegClass.ll.
...
The CFE refers to all single-register constraints (like "A") by their 16-bit
name, even though the 8 or 32-bit version of the register may be needed.
The X86 backend should realize what is going on and redecode the name back
to its proper form.
llvm-svn: 29420
2006-07-31 23:26:50 +00:00
7cc2d19fc1
handle GlobalValue::InternalLinkage in doFinalization
...
llvm-svn: 29417
2006-07-31 20:38:13 +00:00
ac8be4338c
Remove a duplicate pattern.
...
llvm-svn: 29414
2006-07-31 18:43:10 +00:00
2af3a67902
Remove a duplicate pattern/
...
llvm-svn: 29413
2006-07-31 18:42:49 +00:00
ebb592be39
Make functions with an "asm" name propagate that asm name into the cbe.c file.
...
This fixes link errors on programs with these on targets with prefixes.
llvm-svn: 29390
2006-07-28 20:58:47 +00:00
8298265042
Fix some ppc64 issues with vector code.
...
llvm-svn: 29384
2006-07-28 16:45:47 +00:00
e8071ecc3b
Can't spell.
...
llvm-svn: 29383
2006-07-28 06:33:41 +00:00
2e94538b8e
Some clean up.
...
llvm-svn: 29382
2006-07-28 06:05:06 +00:00
e2a3f7014d
Rename IsFoldableBy to CanBeFoldedleBy
...
llvm-svn: 29376
2006-07-28 01:03:48 +00:00
11a4d8c2f4
Node selected into address mode cannot be folded.
...
llvm-svn: 29374
2006-07-28 00:49:31 +00:00
b572401bea
Remove InFlightSet hack. No longer needed.
...
llvm-svn: 29373
2006-07-28 00:47:19 +00:00
3b5e0cafd1
Another duh. Determine topological order before any target node is added.
...
llvm-svn: 29371
2006-07-28 00:10:59 +00:00
f38707b8d4
Brain cramp..
...
llvm-svn: 29370
2006-07-27 23:35:40 +00:00
390dd7eb7d
Allocating too large an array for ReachibilityMatrix.
...
llvm-svn: 29367
2006-07-27 22:35:40 +00:00
87585760ab
Calculate the portion of reachbility matrix on demand.
...
llvm-svn: 29366
2006-07-27 22:10:00 +00:00
d6c0c2dfd9
isNonImmUse is replaced by IsFoldableBy
...
llvm-svn: 29365
2006-07-27 21:19:10 +00:00
78bf1074fc
Resolve BB references with relocation.
...
llvm-svn: 29351
2006-07-27 18:21:10 +00:00
7ec7b467df
synchronizeICache removeed from TargetJITInfo.
...
llvm-svn: 29348
2006-07-27 17:33:48 +00:00
691a63d564
Use reachbility information to determine whether a node can be folded into another during isel.
...
llvm-svn: 29346
2006-07-27 16:44:36 +00:00
89e5cbd897
emit global constants
...
llvm-svn: 29344
2006-07-27 11:38:51 +00:00
f300896420
Remove NodeDepth
...
llvm-svn: 29338
2006-07-27 06:40:15 +00:00
85ea83e821
Add some advice
...
llvm-svn: 29324
2006-07-27 04:24:14 +00:00
3b4866e194
Use the predicate.
...
llvm-svn: 29322
2006-07-27 02:05:13 +00:00
787565024a
Support jump tables when in PIC relocation model
...
llvm-svn: 29318
2006-07-27 01:13:04 +00:00
c169b8798f
Prevent creation of MachineDebugInfo for intel unless it is darwin. RC842.
...
llvm-svn: 29317
2006-07-27 01:12:23 +00:00
23a21c19d9
New entry.
...
llvm-svn: 29310
2006-07-26 21:49:52 +00:00
9e56e5c003
Rename RelocModel::PIC to PIC_, to avoid conflicts with -DPIC.
...
llvm-svn: 29307
2006-07-26 21:12:04 +00:00
f6acb34d23
- Refactor the code that resolve basic block references to a TargetJITInfo
...
method.
- Added synchronizeICache() to TargetJITInfo. It is called after each block
of code is emitted to flush the icache. This ensures correct execution
on targets that have separate dcache and icache.
- Added PPC / Mac OS X specific code to do icache flushing.
llvm-svn: 29276
2006-07-25 20:40:54 +00:00
66ed41cac1
Can't commute shufps. The high / low parts elements come from different vectors.
...
llvm-svn: 29275
2006-07-25 20:25:40 +00:00
8902fd702b
implement function calling of functions with up to 4 arguments
...
llvm-svn: 29274
2006-07-25 20:17:20 +00:00
c0577648c0
Done.
...
llvm-svn: 29262
2006-07-21 23:07:23 +00:00
976c93a110
implemented sub
...
correctly update the stack pointer in the prologue and epilogue
llvm-svn: 29244
2006-07-21 12:26:16 +00:00
74065bedf2
This opt is now handled in DAG combine.
...
llvm-svn: 29243
2006-07-21 08:26:46 +00:00
4cf0238720
A splat of a vector constant of all zero or all one is the vector constant.
...
llvm-svn: 29234
2006-07-20 23:09:47 +00:00
f98bc5288e
Missing a space.
...
llvm-svn: 29233
2006-07-20 22:52:28 +00:00
683b966485
Clean up.
...
llvm-svn: 29228
2006-07-20 21:37:39 +00:00
8a881f2309
New entry.
...
llvm-svn: 29215
2006-07-19 21:29:30 +00:00
181fb1c4d7
Do once flag never set to true.
...
llvm-svn: 29214
2006-07-19 19:33:08 +00:00
7c860afec6
Tidy up a few things.
...
llvm-svn: 29213
2006-07-19 19:32:06 +00:00
18debc21db
Reduce size of routine. Shrinks .o by 37%.
...
llvm-svn: 29210
2006-07-19 17:53:32 +00:00
4f8eb5ccaf
bswapped load/store instructions are only availble in indexed addressing form.
...
As such, use xoaddr (indexed only), not xaddr for address selection.
This fixes CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll, a crash compiling lencod.
llvm-svn: 29208
2006-07-19 17:15:36 +00:00
5ba7c23cdd
Bug#834 ICE (crash in code generator?) when building PCH .
...
Missing Darwin check in Intel ATT ASM printer.
llvm-svn: 29204
2006-07-19 11:54:50 +00:00
968a0b0309
Misc. new entry.
...
llvm-svn: 29202
2006-07-19 06:06:24 +00:00
02d8836cd5
INC / DEC instructions have shorter code size than ADD32ri8, etc.
...
llvm-svn: 29194
2006-07-19 00:27:29 +00:00
c767acd25a
Add code size to target instruction use it as the 3rd isel sorting tie-breaker.
...
llvm-svn: 29193
2006-07-19 00:24:41 +00:00
bf3a17cd32
initial prologue and epilogue implementation. Need to define add and sub before finishing it :-)
...
llvm-svn: 29175
2006-07-18 17:00:30 +00:00
b00b6c2e86
Make the implicit def instructions look like other instrs.
...
llvm-svn: 29174
2006-07-18 16:33:26 +00:00
75269be065
skeleton of a lowerCall implementation for ARM
...
llvm-svn: 29159
2006-07-16 01:02:57 +00:00
e1758d4cef
Remove what little AIX support we have. It has never been tested and isn't
...
complete.
llvm-svn: 29156
2006-07-15 01:24:23 +00:00
2e1d01541a
Add an out-of-line virtual method for X86DwarfWriter to give it a home.
...
llvm-svn: 29153
2006-07-14 23:05:05 +00:00
96aecb5d76
Add missing PPC64 extload/truncstores
...
llvm-svn: 29140
2006-07-14 04:42:02 +00:00
950dffaed6
Add a note
...
llvm-svn: 29139
2006-07-14 04:07:29 +00:00
077b86a078
Another fix in the rotate encodings, needed when the first two operands are not
...
the same.
llvm-svn: 29136
2006-07-13 21:52:41 +00:00
b42a945fd2
Print negative immediates as negative values instead of large constants
...
when using the immshifted addressing mode.
llvm-svn: 29130
2006-07-12 23:24:02 +00:00
dd57ac4871
Fix encoding of rotates, such as rldicl
...
llvm-svn: 29128
2006-07-12 22:08:13 +00:00
5b17dee741
Implement PPC64 relocations types
...
llvm-svn: 29125
2006-07-12 21:23:20 +00:00
1ec5e73b32
An overaggressive #ifdef allows a function to fall off the bottom of the
...
function instead of returning a value. This sometimes allowed the ppc32 jit
to be used in 64-bit mode.
llvm-svn: 29123
2006-07-12 20:42:10 +00:00
c8db10725b
Add information preventing several register class constraints from working.
...
This implements PR828 and CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll
llvm-svn: 29118
2006-07-12 16:59:49 +00:00
6e662083d9
The PPC64 JIT needs register numbers to encode instructions.
...
llvm-svn: 29114
2006-07-11 20:53:55 +00:00
d5a086ab12
Emit inc / dec of registers as one byte instruction.
...
llvm-svn: 29110
2006-07-11 19:49:49 +00:00
f7300b2706
It was pointed out that DEBUG() is only available with -debug.
...
llvm-svn: 29106
2006-07-11 18:25:13 +00:00
c3d341ea98
Ensure that dump calls that are associated with asserts are removed from
...
non-debug build.
llvm-svn: 29105
2006-07-11 17:58:07 +00:00
185c5c2bdf
add the memri memory operand
...
this makes it possible for ldr instructions with non-zero immediate
llvm-svn: 29103
2006-07-11 11:36:48 +00:00
298ef37e02
Implement the inline asm 'A' constraint. This implements PR825 and
...
CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll
llvm-svn: 29101
2006-07-11 02:54:03 +00:00
71227c23b1
In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones.
...
llvm-svn: 29096
2006-07-11 00:48:23 +00:00
32860f42bb
New entry.
...
llvm-svn: 29091
2006-07-10 21:42:16 +00:00
79cf9a5342
Fixed stack objects do not specify alignments, but their offsets are known.
...
Use that information when doing the transformation to merge multiple loads
into a 128-bit load.
llvm-svn: 29090
2006-07-10 21:37:44 +00:00
a7976d329e
Implement Regression/CodeGen/PowerPC/bswap-load-store.ll by folding bswaps
...
into i16/i32 load/stores.
llvm-svn: 29089
2006-07-10 20:56:58 +00:00
9aabc1e16f
Mark internal function static
...
llvm-svn: 29085
2006-07-10 19:53:12 +00:00
e40a7e2aa2
create the raddr addressing mode that matches any register and the frame index
...
use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot
llvm-svn: 29079
2006-07-10 01:41:35 +00:00
af5ae57333
Fix a typo that causes 2006-07-07-ComputeMaskedBits.ll to fail.
...
llvm-svn: 29072
2006-07-07 21:37:21 +00:00
5987cfb7b1
X86 target specific DAG combine: turn build_vector (load x), (load x+4),
...
(load x+8), (load x+12), <0, 1, 2, 3> to a single 128-bit load (aligned and
unaligned).
e.g.
__m128 test(float a, float b, float c, float d) {
return _mm_set_ps(d, c, b, a);
}
_test:
movups 4(%esp), %xmm0
ret
llvm-svn: 29042
2006-07-07 08:33:52 +00:00
59b6e8a683
Undisable ppc64 jit
...
llvm-svn: 29011
2006-07-06 17:10:42 +00:00
0441746468
Added option -code-model to set code model (only used in 64-bit) mode. Valid
...
values include small, kernel, medium, large, and default.
llvm-svn: 29009
2006-07-06 01:53:36 +00:00
0261242aa6
Reorg. No functionality change.
...
llvm-svn: 28999
2006-07-05 22:17:51 +00:00
41816100f4
Fix JIT on non MacOS X i386 systems.
...
llvm-svn: 28992
2006-07-05 07:09:13 +00:00
01078dc60b
These are already implemented
...
llvm-svn: 28990
2006-07-03 18:00:29 +00:00
042f5076ed
0 offsets for memory operands
...
llvm-svn: 28989
2006-07-03 17:57:34 +00:00
390922f979
Should just use xorps to clear XMM registers for all data types. pxor is also one byte longer.
...
llvm-svn: 28984
2006-06-29 18:04:54 +00:00
28a95491d9
Let X86CompilationCallback pass previous frame and return address to X86CompilationCallback2. Remove alloca hack.
...
llvm-svn: 28982
2006-06-29 01:48:36 +00:00
fa9e60895b
Add shift and rotate by 1 instructions / patterns.
...
llvm-svn: 28980
2006-06-29 00:36:51 +00:00
fc8cdda070
Always use xorps to clear XMM registers.
...
llvm-svn: 28979
2006-06-29 00:34:23 +00:00
56737d4fe3
Move .literal4 and .literal8 support into AsmPrinter.cpp
...
llvm-svn: 28978
2006-06-29 00:33:06 +00:00
0cc5907728
Hide x86 symbols
...
llvm-svn: 28976
2006-06-28 23:27:49 +00:00
996795b0dd
Use hidden visibility to make symbols in an anonymous namespace get
...
dropped. This shrinks libllvmgcc.dylib another 67K
llvm-svn: 28975
2006-06-28 23:17:24 +00:00
2f8c2d8ef2
shrink libllvmgcc.dylib another 25K
...
llvm-svn: 28971
2006-06-28 22:00:36 +00:00
87813744ba
Doh.
...
llvm-svn: 28963
2006-06-28 17:56:43 +00:00
0687b04455
Oops. Need to keep CP index.
...
llvm-svn: 28958
2006-06-28 07:55:24 +00:00
7f88856d95
Darwin puts float and double literal constants into literal4 and literal8 sections.
...
llvm-svn: 28957
2006-06-28 07:35:41 +00:00
a53a22e5fe
this case isn't handled
...
llvm-svn: 28948
2006-06-27 23:19:14 +00:00
f6f5aff038
handle the "mov reg1, reg2" case in isMoveInstr
...
llvm-svn: 28945
2006-06-27 21:52:45 +00:00
ca9c488528
Don't match 64-bit bitfield inserts into rlwimi's. todo add rldimi. :)
...
llvm-svn: 28944
2006-06-27 21:08:52 +00:00
f882c54505
Fix ppc64 jump tables
...
llvm-svn: 28941
2006-06-27 20:46:17 +00:00
2aed9ebded
Remove dead code.
...
llvm-svn: 28938
2006-06-27 20:34:14 +00:00
82ab3e21b1
Print stubs for external globals right.
...
llvm-svn: 28936
2006-06-27 20:20:53 +00:00
8aed3cc46b
Implement 64-bit select, bswap, etc.
...
llvm-svn: 28935
2006-06-27 20:14:52 +00:00
a2af3f47ea
Add a pattern for i64 sra. Print 8-byte units with a space between the .quad
...
and the data
llvm-svn: 28934
2006-06-27 20:07:26 +00:00
db9a95b775
Fix rewriting frame offsets with ixaddr instructions, which implicitly shift
...
the offset two bits to the left.
llvm-svn: 28933
2006-06-27 18:55:49 +00:00
a07410c95b
PPC doesn't have bit converts to/from i64
...
llvm-svn: 28932
2006-06-27 18:40:08 +00:00
3b5873456e
Add 64-bit MTCTR so that indirect calls work.
...
llvm-svn: 28931
2006-06-27 18:36:44 +00:00
e27d51e0d8
Fix an incorrect store pattern. This fixes em3d.
...
llvm-svn: 28930
2006-06-27 18:22:50 +00:00
d48ce27532
Implement 64-bit undef, sub, shl/shr, srem/urem
...
llvm-svn: 28929
2006-06-27 18:18:41 +00:00
cb5a84f446
Use i32 for shift amounts instead of i64. This gets bisort working.
...
llvm-svn: 28927
2006-06-27 17:34:57 +00:00
f7fd88356a
Add zextload from i32 -> i64, with this, perimeter works.
...
llvm-svn: 28926
2006-06-27 17:30:08 +00:00
1df0839067
Print darwin stub stuff correctly in 64-bit mode. With this, treeadd works in
...
ppc64 mode!
llvm-svn: 28923
2006-06-27 01:02:25 +00:00
9a40cca40f
Fix variable shadowing issue
...
llvm-svn: 28922
2006-06-27 00:10:13 +00:00
97b3da1519
Implement a bunch of 64-bit cleanliness work. With this, treeadd builds (but
...
doesn't work right).
llvm-svn: 28921
2006-06-27 00:04:13 +00:00
7ecbd301b1
Rearrange compares, add ADDI8, add sext from 32-to-64 bit register
...
llvm-svn: 28920
2006-06-26 23:53:10 +00:00
ec78cade34
Improve PPC64 calling convention support
...
llvm-svn: 28919
2006-06-26 22:48:35 +00:00
b6a65f4661
Remove two more definitions
...
llvm-svn: 28918
2006-06-26 22:47:37 +00:00
86e6046515
remove two unused instructions.
...
llvm-svn: 28917
2006-06-26 22:44:13 +00:00
38c5aee959
Simplify X86CompilationCallback: always align to 16-byte boundary; don't save EAX/EDX if unnecessary.
...
llvm-svn: 28910
2006-06-24 08:36:10 +00:00
a7b2bd5997
Add and sort "sections" in debug lines. This always stepping through
...
code in sections other than ".text", including weak sections like ctors and
dtors.
llvm-svn: 28909
2006-06-23 12:51:53 +00:00
0c9b90aba3
Eliminate unneeded parameter.
...
llvm-svn: 28907
2006-06-22 00:02:55 +00:00
fc1b27dad1
variable_ops instructions such as call can have any number of operands.
...
llvm-svn: 28906
2006-06-21 23:37:07 +00:00
680ac12e53
Add memory operand and int regs
...
llvm-svn: 28896
2006-06-21 15:42:36 +00:00
b0316eada6
inline asm, at least for floats
...
llvm-svn: 28895
2006-06-21 13:37:27 +00:00
336313ce3d
fix argument problem
...
llvm-svn: 28893
2006-06-21 01:00:43 +00:00
dc38e6f322
Correct returns of 64-bit values, though they seemed to work before...
...
llvm-svn: 28892
2006-06-21 00:34:03 +00:00
1f1b096142
Make these predicates correct in 64-bit mode too.
...
llvm-svn: 28890
2006-06-20 23:21:20 +00:00
52a956da52
Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit file
...
llvm-svn: 28889
2006-06-20 23:18:58 +00:00
5705d4d519
remove unused flag
...
llvm-svn: 28888
2006-06-20 23:15:07 +00:00
9d65f3507e
add some logical ops
...
llvm-svn: 28887
2006-06-20 23:11:59 +00:00
7a856a6d88
remove some unused patterns
...
llvm-svn: 28886
2006-06-20 23:11:36 +00:00
d881f8257b
Add some more immediate patterns. This allows us to compile:
...
void test6() {
Y = 0xABCD0123BCDE4567;
}
into:
_test6:
lis r2, -21555
lis r3, ha16(_Y)
ori r2, r2, 291
rldicr r2, r2, 32, 31
oris r2, r2, 48350
ori r2, r2, 17767
std r2, lo16(_Y)(r3)
blr
llvm-svn: 28885
2006-06-20 23:03:01 +00:00
9834ad2fc6
Instead of li/xoris use li/oris. Note that this doesn't work if bit 15 is
...
set, so disable the pattern in that case.
llvm-svn: 28884
2006-06-20 22:38:59 +00:00
7e742e46ac
Add some 64-bit logical ops.
...
Split imm16Shifted into a sext/zext form for 64-bit support.
Add some patterns for immediate formation. For example, we now compile this:
static unsigned long long Y;
void test3() {
Y = 0xF0F00F00;
}
into:
_test3:
li r2, 3840
lis r3, ha16(_Y)
xoris r2, r2, 61680
std r2, lo16(_Y)(r3)
blr
GCC produces:
_test3:
li r0,0
lis r2,ha16(_Y)
ori r0,r0,61680
sldi r0,r0,16
ori r0,r0,3840
std r0,lo16(_Y)(r2)
blr
llvm-svn: 28883
2006-06-20 22:34:10 +00:00
164a221b65
__i386__, __i386, etc. are not defined for x86-64. Use __x86_64__.
...
llvm-svn: 28881
2006-06-20 22:11:12 +00:00
d6e160d14d
64-bit bugfix: 0xFFFF0000 cannot be formed with a single lis.
...
llvm-svn: 28880
2006-06-20 21:39:30 +00:00
2d4e8f7e86
Add some patterns for globals, so we can now compile this:
...
static unsigned long long X, Y;
void test1() {
X = Y;
}
into:
_test1:
lis r2, ha16(_Y)
lis r3, ha16(_X)
ld r2, lo16(_Y)(r2)
std r2, lo16(_X)(r3)
blr
llvm-svn: 28879
2006-06-20 21:23:06 +00:00
868a75bec6
Remove some now-unneeded casts from instruction patterns. With the casts
...
removed, tblgen produces identical output to with them in.
llvm-svn: 28867
2006-06-20 00:39:56 +00:00
94d18df658
Add some patterns for ppc64
...
llvm-svn: 28866
2006-06-20 00:38:36 +00:00
dbec49d574
Remove some ugly now-redundant casts.
...
llvm-svn: 28864
2006-06-20 00:25:29 +00:00
55594634d7
Fix some mismatched type constraints
...
llvm-svn: 28862
2006-06-20 00:12:37 +00:00
cd58e9d8b9
Minor clean up.
...
llvm-svn: 28860
2006-06-19 19:25:30 +00:00
a88966fd5e
initial implementation of ARMRegisterInfo::eliminateFrameIndex
...
fixes test/Regression/CodeGen/ARM/ret_arg5.ll
llvm-svn: 28854
2006-06-18 00:08:07 +00:00
a54b9643aa
A new entry.
...
llvm-svn: 28848
2006-06-17 00:45:49 +00:00
49cadab385
Implement the getPointerRegClass method, which is required for the ptr_rc
...
magic to work.
llvm-svn: 28847
2006-06-17 00:01:04 +00:00
d2e9a67cd9
Later models likely to have Yonah like attributes.
...
llvm-svn: 28843
2006-06-16 21:58:49 +00:00
638ee4ee15
Upgrade some load/store instructions to use the proper addressing mode stuff.
...
llvm-svn: 28841
2006-06-16 21:29:41 +00:00
e8fe5e2bf4
In 64-bit mode, addr mode operands use G8RC instead of GPRC.
...
llvm-svn: 28840
2006-06-16 21:29:03 +00:00
a5190ae7a9
fix some assumptions that pointers can only be 32-bits. With this, we can
...
now compile:
static unsigned long X;
void test1() {
X = 0;
}
into:
_test1:
lis r2, ha16(_X)
li r3, 0
stw r3, lo16(_X)(r2)
blr
Totally amazing :)
llvm-svn: 28839
2006-06-16 21:01:35 +00:00
b429983988
Split 64-bit instructions out into a separate .td file
...
llvm-svn: 28838
2006-06-16 20:22:01 +00:00
61d703183e
Force 64-bit register availability in 64-bit mode. For real.
...
llvm-svn: 28837
2006-06-16 20:05:06 +00:00
a7d9db2fa5
Remove the -darwin and -aix llc options, inferring darwinism and aixism from
...
the target triple & subtarget info. woo.
llvm-svn: 28835
2006-06-16 18:50:48 +00:00
f3b5b92e58
Don't pass target name into TargetData anymore, it is never used or needed.
...
Remove explicit casts to std::string now that there is no overload resolution
issues in the TargetData ctors.
llvm-svn: 28830
2006-06-16 18:22:52 +00:00
7f043b52ff
Remove ctor with each piece specifyable (which causes overload ambiguities),
...
add a new init method.
llvm-svn: 28828
2006-06-16 18:11:26 +00:00
16682fff2b
Document the subtarget features better, make sure that 64-bit mode, 64-bit
...
support, and 64-bit register use are all consistent with each other.
Add a new "IsPPC" feature, to distinguish ppc32 vs ppc64 targets, use this
to configure TargetData differently. This not makes ppc64 blow up on lots
of stuff :)
llvm-svn: 28825
2006-06-16 17:50:12 +00:00
a35f306740
Rename some subtarget features. A CPU now can *have* 64-bit instructions,
...
can in 32-bit mode we can choose to optionally *use* 64-bit registers.
llvm-svn: 28824
2006-06-16 17:34:12 +00:00
0c4aa14deb
First baby step towards ppc64 support. This adds a new -march=ppc64 backend
...
that is currently just like ppc32 :)
llvm-svn: 28813
2006-06-16 01:37:27 +00:00
cb29586ce4
Add a note that Nate noticed.
...
llvm-svn: 28808
2006-06-15 21:33:31 +00:00
19f964e048
1. Support standard dwarf format (was bootstrapping in Apple format.)
...
2. Add vector support.
llvm-svn: 28807
2006-06-15 20:51:43 +00:00
66f0e09313
Vector extract / insert index operand should have ptr type.
...
llvm-svn: 28798
2006-06-15 08:19:05 +00:00
94bb93f8f7
Type of extract_element index operand should be iPTR.
...
llvm-svn: 28797
2006-06-15 08:18:06 +00:00
de7156f12c
Type of vector extract / insert index operand should be iPTR.
...
llvm-svn: 28796
2006-06-15 08:14:54 +00:00
c8734381ac
X86 call instructions can take variable number of operands. Parameters of
...
vector types are passed via XMM registers.
llvm-svn: 28789
2006-06-14 22:24:55 +00:00
37c1c44c14
add a note
...
llvm-svn: 28787
2006-06-14 21:26:18 +00:00
ca25486603
Add argument registers to the end of call operand list (partial fix).
...
llvm-svn: 28783
2006-06-14 18:17:40 +00:00
f67bec0579
Place dwarf headers at earliest possible point. Well behaved when skipping
...
functions.
llvm-svn: 28781
2006-06-14 11:35:03 +00:00
7c69df968c
I am sure I had commited this workaround before. Perhaps soon I should sort it all out
...
llvm-svn: 28772
2006-06-13 20:34:47 +00:00
f570feeae3
It really helps to be returning to the correct place
...
llvm-svn: 28769
2006-06-13 18:27:39 +00:00
c5bb8ab1d5
Port some bugfixes in shift handling from SimplifyDemandedBits over to
...
ComputeMaskedBits. DemandedMasks and KnownZero/One masks should never have
bits set out of the range of the base datatype.
llvm-svn: 28768
2006-06-13 16:52:37 +00:00
8cac9cd5f6
TargetLowering::ComputeMaskedBits was not clearing reciprocal bits on shifts.
...
llvm-svn: 28765
2006-06-13 13:08:58 +00:00
17ca732b6a
Cygwin support: use _alloca to allocate stack if > 4k. Patch by Anton Korobeynikov.
...
llvm-svn: 28764
2006-06-13 05:14:44 +00:00
ac59ab515a
Gaar! Don't use r11 for CR save/restore, use R0. R11 can be register
...
allocated, thus live across the save/reload. This fixes
llc-beta /MultiSource/Applications/spiff/spiff
llc-beta /MultiSource/Benchmarks/sim/sim:
llc-beta /MultiSource/Benchmarks/Ptrdist/bc/bc
llc-beta /MultiSource/Benchmarks/McCat/12-IOtest/iotest:
llc-beta /MultiSource/Benchmarks/FreeBench/fourinarow/fourinarow
llc-beta /MultiSource/Benchmarks/Fhourstones-3.1/fhourstones3.1
llc-beta /MultiSource/Benchmarks/mediabench/adpcm/rawdaudio/rawdaudio
llc-beta /MultiSource/Benchmarks/mediabench/adpcm/rawcaudio/rawcaudio
llc-beta /MultiSource/Benchmarks/mediabench/g721/g721encode/encode
llc-beta /MultiSource/Benchmarks/mediabench/jpeg/jpeg-6a/cjpeg
and probably others, with -regalloc=local.
llvm-svn: 28761
2006-06-12 23:59:16 +00:00
6b043a24a1
Fix spilling and reloading of CR regs to reload the right values. This fixes
...
Olden/power (and probably others) with -regalloc=local.
llvm-svn: 28760
2006-06-12 21:50:57 +00:00
80528499cf
Let the alpha breakage begin. First Formals and RET. next Calls
...
llvm-svn: 28753
2006-06-12 18:09:24 +00:00
0e57b2cb92
Start on my todo list
...
llvm-svn: 28752
2006-06-12 16:07:18 +00:00
4e76015e0b
lower more then 4 formal arguments. The offset is currently hard coded.
...
implement SelectFrameIndex
llvm-svn: 28751
2006-06-12 12:28:08 +00:00
b055c8737f
Work around a nasty tblgen bug where it doesn't add operands for varargs
...
nodes correctly.
llvm-svn: 28745
2006-06-10 01:15:02 +00:00
006b2c6ab9
Fix a problem exposed by the local allocator. CALL instructions are not marked
...
as using incoming argument registers, so the local allocator would clobber them
between their set and use. To fix this, we give the call instructions a variable
number of uses in the CALL MachineInstr itself, so live variables understands
the live ranges of these register arguments.
llvm-svn: 28744
2006-06-10 01:14:28 +00:00
beedf824e3
Comments to appease sabre.
...
llvm-svn: 28737
2006-06-09 06:25:10 +00:00
0e14a56d35
Minor compilation speed improvement.
...
llvm-svn: 28736
2006-06-09 06:24:42 +00:00
ba1ed585ee
Add support for "m" inline asm constraints.
...
llvm-svn: 28728
2006-06-08 18:03:49 +00:00
dc614c193e
Added X86FunctionInfo subclass of MachineFunction to record whether the
...
function that is being lowered is forced to use FP. Currently this is only
true for main() / Cygwin.
llvm-svn: 28703
2006-06-06 23:30:24 +00:00
16826c3503
Now that PR633 is implemented, the CBE can know to emit _setjmp/_longjmp
...
when available. This speeds up hexxagon from 18.61s to 16.61s with the CBE on
PPC Mac OS (for reference, LLC is 15.48s and GCC is 23.35s).
llvm-svn: 28697
2006-06-06 21:45:47 +00:00
c8587d4b81
Add PowerPC intrinsics to support dcbz[l]
...
llvm-svn: 28696
2006-06-06 21:29:23 +00:00
6306becc49
add R0 to liveout
...
expand "ret null" (implements test/Regression/CodeGen/ARM/ret_void.ll)
note that a Flag link is missing between the copy and the branch
llvm-svn: 28691
2006-06-05 22:26:14 +00:00
0f29df98a1
A few new entries.
...
llvm-svn: 28683
2006-06-04 09:08:00 +00:00
0de66677e7
Be consistent with gcc.
...
llvm-svn: 28682
2006-06-04 07:24:07 +00:00
b47461350c
ignore ordered/unordered for now
...
llvm-svn: 28679
2006-06-04 00:25:51 +00:00
e8a42360c5
Cygwin support. Patch by Anton Korobeynikov!
...
llvm-svn: 28672
2006-06-02 22:38:37 +00:00
a2efb9f3ec
Use xor to clear a register.
...
llvm-svn: 28667
2006-06-02 21:20:34 +00:00
7ae8632cb4
Incorrect AT&T opcode.
...
llvm-svn: 28666
2006-06-02 21:09:10 +00:00
8fd1036612
Add mingw support, patch contributed by Anton
...
llvm-svn: 28661
2006-06-02 18:54:01 +00:00
4442a70b3a
Silence -pedantic warning
...
llvm-svn: 28633
2006-06-01 17:17:06 +00:00
b47b8a9fad
Silence -pedantic warning.
...
llvm-svn: 28630
2006-06-01 17:13:10 +00:00
2b2c1be49c
Typos
...
llvm-svn: 28617
2006-06-01 05:53:27 +00:00
75f29be136
For PR786:
...
Don't warn about -pedantic errors. Add a note to the PR instead.
llvm-svn: 28616
2006-06-01 05:49:51 +00:00
a62f097c96
For PR786:
...
Turn -pedantic and -Wno-long-long compile flags on by default. In a few
places, avoid the warnings by removing these options in the local makefile.
One notable exception: lib/Target/CBackend/Writer.cpp. These warnings are
left on as a reminder to developers to clean them up.
llvm-svn: 28614
2006-06-01 01:55:21 +00:00
a647c7ff42
Use archive libraries instead of object files for VMCore, BCReader,
...
BCWriter, and bzip2 libraries. Adjust the various makefiles to accommodate
these changes. This was done to speed up link times.
llvm-svn: 28610
2006-06-01 01:30:27 +00:00
2489ccdd90
Remove a warning
...
llvm-svn: 28607
2006-06-01 00:30:39 +00:00
cfaffdd335
Rename ASM modifier trunc8, trunc16 to subreg8, subreg16.
...
llvm-svn: 28606
2006-05-31 22:34:26 +00:00
ff82596981
Fix casting so there's no warning on Alpha.
...
llvm-svn: 28605
2006-05-31 22:26:11 +00:00
cf70c7f42d
Sign extender
...
llvm-svn: 28603
2006-05-31 22:05:11 +00:00
25e44e008d
Rename instructions for consistency sake.
...
llvm-svn: 28594
2006-05-31 19:00:07 +00:00
8abf45e22d
Select vector_shuffle v1, undef <2, 3, ?, ?> to MOVHLPS.
...
llvm-svn: 28582
2006-05-31 00:51:37 +00:00
550cb663e8
Remove dead code.
...
llvm-svn: 28581
2006-05-31 00:50:42 +00:00
ddced95d8f
A new entry
...
llvm-svn: 28579
2006-05-30 23:56:31 +00:00
57399704b3
MAXP{D|S} and MINP{D|S} are commutable.
...
llvm-svn: 28578
2006-05-30 23:47:30 +00:00
c0f90bef47
Commute shufps / shufpd.
...
llvm-svn: 28577
2006-05-30 23:34:30 +00:00
f21045a5cd
Somehow I lost a condition when I was shuffling some code around. Anyway,
...
only transform a shufps to pshufd when the first two operands are the same.
llvm-svn: 28575
2006-05-30 22:13:36 +00:00
c8c172eaae
Fix a build breaker.
...
llvm-svn: 28574
2006-05-30 21:45:53 +00:00
a4fc5b8699
Oops. PSHUFD is only available with SSE2.
...
llvm-svn: 28573
2006-05-30 21:30:59 +00:00
a5d4587296
Add a note
...
llvm-svn: 28572
2006-05-30 21:29:15 +00:00
b9342afa56
Always reserve space for 8 spilled GPRs. GCC apparently assumes that this
...
space will be available, even if the callee isn't varargs.
llvm-svn: 28571
2006-05-30 21:21:04 +00:00
66f849bd7b
Allow shufps x, x, mask to be converted to pshufd x, mask to save a move.
...
llvm-svn: 28565
2006-05-30 20:26:50 +00:00
b33e54ead7
Remove bogus comment.
...
llvm-svn: 28564
2006-05-30 20:24:48 +00:00
5bc60da112
Expand ret into "CopyToReg;BRIND"
...
llvm-svn: 28559
2006-05-30 17:33:19 +00:00
02420144ab
Add a note about integer multiplication by constants.
...
llvm-svn: 28551
2006-05-30 07:37:37 +00:00
734e1e241b
A addressing mode folding enhancement:
...
Fold c2 in (x << c1) | c2 where (c2 < c1)
e.g.
int test(int x) {
return (x << 3) + 7;
}
This can be codegen'd as:
leal 7(,%eax,8), %eax
llvm-svn: 28550
2006-05-30 06:59:36 +00:00
749138582e
Some new entries about truncate / anyext
...
llvm-svn: 28548
2006-05-30 06:23:50 +00:00
64d8692dee
Ignore generated files
...
llvm-svn: 28520
2006-05-27 01:23:30 +00:00
a3add0fea8
Change RET node to include signness information of the return values. i.e.
...
RET chain, value1, sign1, value2, sign2, ...
llvm-svn: 28510
2006-05-26 23:10:12 +00:00
b92f418408
Vector argument must be passed in memory location aligned on 16-byte boundary.
...
llvm-svn: 28505
2006-05-26 20:37:47 +00:00
bfb5ea6875
Mac OS X ABI document lied. The first four XMM registers are used to pass
...
vector arguments, not three.
llvm-svn: 28504
2006-05-26 19:22:06 +00:00
a01e799927
Minor update to make the code more clear
...
llvm-svn: 28499
2006-05-26 18:39:59 +00:00
cbfb3d07e0
Update more comments.
...
llvm-svn: 28498
2006-05-26 18:37:16 +00:00
763f9b00f0
Fix some comments.
...
llvm-svn: 28497
2006-05-26 18:25:43 +00:00
83dc51d7ff
No need to handle illegal types.
...
llvm-svn: 28496
2006-05-26 18:22:49 +00:00
87bc1a9b0b
On ARM, alignment is in bits
...
Add lr as a hard coded operand of bx
llvm-svn: 28494
2006-05-26 10:56:17 +00:00
70145f2d5e
Remove a couple of bogus casts.
...
llvm-svn: 28493
2006-05-26 08:04:31 +00:00
29296b844f
Minor bug caught by Ashwin Chandra
...
llvm-svn: 28491
2006-05-26 06:22:34 +00:00
8aca43e8da
Consistency
...
llvm-svn: 28488
2006-05-25 23:31:23 +00:00
0421aca87a
Some clean up.
...
llvm-svn: 28483
2006-05-25 22:38:31 +00:00
dc1614d93e
Add support for the missing FP condition codes
...
llvm-svn: 28482
2006-05-25 22:26:02 +00:00
29f805ec65
Remove some dead code.
...
llvm-svn: 28481
2006-05-25 22:25:52 +00:00
2554e3d9ba
X86 / Cygwin asm / alignment fixes.
...
Patch contributed by Anton Korobeynikov!
llvm-svn: 28480
2006-05-25 21:59:08 +00:00
5ee96893ae
Build breakage.
...
llvm-svn: 28475
2006-05-25 18:56:34 +00:00
1fbb0d38c7
Fix build failure of povray
...
llvm-svn: 28473
2006-05-25 18:06:16 +00:00
630bbcef8d
Fix Benchmarks/MallocBench/cfrac
...
llvm-svn: 28471
2006-05-25 16:54:16 +00:00
91df1ef41f
implement initial version of ARMAsmPrinter::printOperand
...
llvm-svn: 28470
2006-05-25 12:57:06 +00:00
4781610886
port the ARM backend to use ISD::CALL instead of LowerCallTo
...
llvm-svn: 28469
2006-05-25 11:00:18 +00:00
2a33094284
Switch X86 over to a call-selection model where the lowering code creates
...
the copyto/fromregs instead of making the X86ISD::CALL selection code create
them.
llvm-svn: 28463
2006-05-25 00:59:30 +00:00
c2cd473d9b
CALL node change (arg / sign pairs instead of just arguments).
...
llvm-svn: 28462
2006-05-25 00:57:32 +00:00
4af59dac0b
Assert if InflightSet is not cleared after instruction selecting a BB.
...
llvm-svn: 28459
2006-05-25 00:24:28 +00:00
1a8e74d113
Clear HandleMap and ReplaceMap after instruction selection. Or it may cause
...
non-deterministic behavior.
llvm-svn: 28454
2006-05-24 20:46:25 +00:00
6e64180f03
For PR786:
...
Minor tweaks in public headers and a few .cpp files so that LLVM can build
successfully with -pedantic and projects using LLVM with -pedantic don't
get warnings from LLVM. There's still more -pedantic warnings to fix.
llvm-svn: 28453
2006-05-24 19:21:13 +00:00
94531bf367
For PR786:
...
Remove a spurious ;
llvm-svn: 28452
2006-05-24 19:05:21 +00:00
aa2372562e
Patches to make the LLVM sources more -pedantic clean. Patch provided
...
by Anton Korobeynikov! This is a step towards closing PR786.
llvm-svn: 28447
2006-05-24 17:04:05 +00:00
33165c246c
Fix CodeGen/Generic/vector.ll:test_div with altivec.
...
llvm-svn: 28445
2006-05-24 00:15:25 +00:00
b56d22c2f6
Handle SETO* like we handle SET*, restoring behavior after Evan's setcc
...
change. This fixes PowerPC/fnegsel.ll.
llvm-svn: 28443
2006-05-24 00:06:44 +00:00
de177e016e
Print struct return functions and calls as actually returning the hidden
...
argument struct pointer, enabling ABI compatibility for the CBE with
platforms with strange struct-return ABIs. This fixes 252.eon and
CoyoteBench/fftbench on Darwin/X86 among other things.
llvm-svn: 28442
2006-05-23 23:39:48 +00:00
a58f559848
Fix file header comment
...
llvm-svn: 28441
2006-05-23 23:20:42 +00:00
7068a93cae
Better way to check for vararg.
...
llvm-svn: 28440
2006-05-23 21:08:24 +00:00
17e734f0a6
Remove PreprocessCCCArguments and PreprocessFastCCArguments now that
...
FORMAL_ARGUMENTS nodes include a token operand.
llvm-svn: 28439
2006-05-23 21:06:34 +00:00
8be5be817c
Implement an annoying part of the Darwin/X86 abi: the callee of a struct
...
return argument pops the hidden struct pointer if present, not the caller.
For example, in this testcase:
struct X { int D, E, F, G; };
struct X bar() {
struct X a;
a.D = 0;
a.E = 1;
a.F = 2;
a.G = 3;
return a;
}
void foo(struct X *P) {
*P = bar();
}
We used to emit:
_foo:
subl $28, %esp
movl 32(%esp), %eax
movl %eax, (%esp)
call _bar
addl $28, %esp
ret
_bar:
movl 4(%esp), %eax
movl $0, (%eax)
movl $1, 4(%eax)
movl $2, 8(%eax)
movl $3, 12(%eax)
ret
This is correct on Linux/X86 but not Darwin/X86. With this patch, we now
emit:
_foo:
subl $28, %esp
movl 32(%esp), %eax
movl %eax, (%esp)
call _bar
*** addl $24, %esp
ret
_bar:
movl 4(%esp), %eax
movl $0, (%eax)
movl $1, 4(%eax)
movl $2, 8(%eax)
movl $3, 12(%eax)
*** ret $4
For the record, GCC emits (which is functionally equivalent to our new code):
_bar:
movl 4(%esp), %eax
movl $3, 12(%eax)
movl $2, 8(%eax)
movl $1, 4(%eax)
movl $0, (%eax)
ret $4
_foo:
pushl %esi
subl $40, %esp
movl 48(%esp), %esi
leal 16(%esp), %eax
movl %eax, (%esp)
call _bar
subl $4, %esp
movl 16(%esp), %eax
movl %eax, (%esi)
movl 20(%esp), %eax
movl %eax, 4(%esi)
movl 24(%esp), %eax
movl %eax, 8(%esi)
movl 28(%esp), %eax
movl %eax, 12(%esi)
addl $40, %esp
popl %esi
ret
This fixes SingleSource/Benchmarks/CoyoteBench/fftbench with LLC and the
JIT, and fixes the X86-backend portion of PR729. The CBE still needs to
be updated.
llvm-svn: 28438
2006-05-23 18:50:38 +00:00
ac4f66ff24
-enable-unsafe-fp-math implies -enable-finite-only-fp-math
...
llvm-svn: 28437
2006-05-23 18:18:46 +00:00
ea1450742e
Added option -enable-finite-only-fp-math. When on, the codegen can assume that
...
FP arithmetic arguments and results are never NaNs or +=Infs. This includes
ignoring parity flag (PF) when checking for FP equality.
llvm-svn: 28432
2006-05-23 06:39:12 +00:00
27f8bdc7e5
implement minimal versions of
...
ARMAsmPrinter::runOnMachineFunction
LowerFORMAL_ARGUMENTS
ARMInstrInfo::isMoveInstr
llvm-svn: 28431
2006-05-23 02:48:20 +00:00
26ba25f910
A isel deficiency.
...
llvm-svn: 28427
2006-05-22 05:54:49 +00:00
85b6232b53
Back out indirect branch load folding hack. It broke some tests.
...
llvm-svn: 28425
2006-05-21 06:28:50 +00:00
80b0a70911
Add a note
...
llvm-svn: 28424
2006-05-21 03:57:07 +00:00
80b1b4d41e
Make TargetData strings less redundant.
...
llvm-svn: 28423
2006-05-20 23:28:54 +00:00
482fb65144
Fix a parsing bug that caused 7 llvm-test regressions on PPC last night.
...
I'm suprised it didn't cause more!
llvm-svn: 28421
2006-05-20 21:16:59 +00:00
401049ce33
- Use of load's chain result should be redirected to load's chain operand.
...
If it reads the chain result of the call, then the use, callseq_start,
and call would form a cycle!
- Don't forget handle node replacement!
- There could also be a TokenFactor between the load and the callseq_start.
llvm-svn: 28420
2006-05-20 09:21:39 +00:00
0643f902be
A new entry
...
llvm-svn: 28419
2006-05-20 07:44:53 +00:00
a26c451fa2
Missing break statements.
...
llvm-svn: 28418
2006-05-20 07:44:28 +00:00
b9ac06bb33
Remove unused patterns.
...
llvm-svn: 28417
2006-05-20 01:40:16 +00:00
f838cfcfbe
Handle indirect call which folds a load manually. This never matches by
...
the TableGen generated code since the load's chain result is read by
the callseq_start node.
llvm-svn: 28416
2006-05-20 01:36:52 +00:00
f7db631b7d
Sparc is big-endian.
...
llvm-svn: 28415
2006-05-20 00:49:30 +00:00
88812b5c0a
Make all of the TargetMachine subclasses use the new string TargetData methods.
...
This is part of the on-going work on PR 761.
llvm-svn: 28414
2006-05-20 00:24:56 +00:00
01dd6df5f3
CSRet allows varargs
...
llvm-svn: 28409
2006-05-19 21:34:04 +00:00
29d7bded45
Add a note
...
llvm-svn: 28402
2006-05-19 21:01:38 +00:00
b22eb6304f
Add a note
...
llvm-svn: 28401
2006-05-19 20:55:31 +00:00
17f1f1a56c
Split the SSE readme items out into their own README.
...
llvm-svn: 28400
2006-05-19 20:51:43 +00:00
427ea6f0a7
Split FP-stack notes out of the main readme. Next up: splitting out SSE.
...
llvm-svn: 28399
2006-05-19 20:45:52 +00:00
240f846495
Move a target-independent note out of the X86 readme.
...
llvm-svn: 28398
2006-05-19 20:45:08 +00:00
d6a25a08d1
Particularly ugly code.
...
llvm-svn: 28397
2006-05-19 19:41:33 +00:00
feca91a516
These can be transformed into lea as well. Not that we use this feature
...
currently...
llvm-svn: 28393
2006-05-19 18:43:41 +00:00
7b8feb27c8
- Use exact-width integer types, e.g. int32_t, to avoid confusion.
...
- Fix a couple of minor bugs in i16immSExt8 and i16immZExt8.
- Added loadiPTR fragment used for indirect jumps and calls.
llvm-svn: 28392
2006-05-19 18:40:54 +00:00
1c8ef9832f
Explicitly specify MOV32mi can only be used store 32-bit GV, etc.
...
llvm-svn: 28390
2006-05-19 07:30:36 +00:00
b15597b59a
implement movri
...
add a stub LowerFORMAL_ARGUMENTS
llvm-svn: 28388
2006-05-18 21:45:49 +00:00
f3cbd7ef31
Added a Flags field to TargetOperandInfo. Currently the only flag is
...
M_LOOK_UP_PTR_REG_CLASS which allows the register class of the operand to be
resolved via a callback at runtime.
llvm-svn: 28387
2006-05-18 20:44:26 +00:00
4cda95b32f
add a note
...
llvm-svn: 28384
2006-05-18 18:26:13 +00:00
f66e89721d
add a note
...
llvm-svn: 28383
2006-05-18 17:38:16 +00:00
b90055ef24
Fix a bogus gcc warning
...
llvm-svn: 28382
2006-05-18 17:29:34 +00:00
03524c63ff
ImmMask should be 3 for a two-bit field; Compact X86II
...
llvm-svn: 28381
2006-05-18 06:27:15 +00:00
305c49579c
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
...
llvm-svn: 28378
2006-05-18 00:12:58 +00:00
297e1cb10a
Remove CalleeSavedRegisters from class Target.
...
llvm-svn: 28377
2006-05-18 00:09:53 +00:00
fc08d5a2a8
Fix a stupid bug when parsing TargetData strings.
...
llvm-svn: 28373
2006-05-17 21:56:02 +00:00
e59042d004
Use generic iPTR instead i32 to represent pointer type.
...
llvm-svn: 28371
2006-05-17 21:21:41 +00:00
7fa58c38c0
Another entry
...
llvm-svn: 28370
2006-05-17 21:20:51 +00:00
dcec882286
Remove PointerType from class Target
...
llvm-svn: 28368
2006-05-17 21:20:27 +00:00
0f524f2050
Fix call_adj.ll
...
llvm-svn: 28360
2006-05-17 19:24:49 +00:00
446dbcb5e4
Added sanity check for obviously bogus immediates
...
llvm-svn: 28359
2006-05-17 19:24:31 +00:00
8c6b234ce8
Should pass by reference.
...
llvm-svn: 28357
2006-05-17 19:07:40 +00:00
00bce3f2f4
Another entry
...
llvm-svn: 28356
2006-05-17 19:05:31 +00:00
6353807fdc
Add a note about a note
...
llvm-svn: 28355
2006-05-17 19:02:25 +00:00
eb755fc1b3
Make PPC call lowering more aggressive, making the isel matching code simple
...
enough to be autogenerated.
llvm-svn: 28354
2006-05-17 19:00:46 +00:00
19aaaca293
Another typo. Pointed out by Nate Begeman.
...
llvm-svn: 28353
2006-05-17 18:22:14 +00:00
6dcec44fec
Fix an obvious bug in getPackedTypeBreakdown. Return 1 if type is legal.
...
llvm-svn: 28351
2006-05-17 18:10:06 +00:00
b1e9e37c58
Switch PPC over to a call-selection model where the lowering code creates
...
the copyto/fromregs instead of making the PPCISD::CALL selection code create
them. This vastly simplifies the selection code, and moves the ABI handling
parts into one place.
llvm-svn: 28346
2006-05-17 06:01:33 +00:00
b7552a88d6
3 changes, 2 of which are cleanup one of which changes codegen:
...
1. Rearrange code a bit so that the special case doesn't require indenting lots
of code.
2. Add comments describing PPC calling convention.
3. Only round up to 56-bytes of stack space for an outgoing call if the callee
is varargs. This saves a bit of stack space.
llvm-svn: 28342
2006-05-17 00:15:40 +00:00
f058f5aef1
implement passing/returning vector regs to calls, at least non-varargs calls.
...
llvm-svn: 28341
2006-05-16 23:54:25 +00:00
aa40ec1b32
Instead of implementing LowerCallTo directly, let the default impl produce an
...
ISD::CALL node, then custom lower that. This means that we only have to handle
LEGAL call operands/results, not every possible type. This allows us to
simplify the call code, shrinking it by about 1/3.
llvm-svn: 28339
2006-05-16 22:56:08 +00:00
26e2fcd8b1
Simplify the argument counting logic by only incrementing the index.
...
llvm-svn: 28335
2006-05-16 18:58:15 +00:00
76c47b50e7
Simplify the dead argument handling code.
...
llvm-svn: 28334
2006-05-16 18:54:32 +00:00
318f0d2122
Vector args passed in registers don't reserve stack space.
...
llvm-svn: 28333
2006-05-16 18:51:52 +00:00
4302e8fb67
Switch the PPC backend over to using FORMAL_ARGUMENTS for formal argument
...
handling. This makes the lower argument code significantly simpler (we
only need to handle legal argument types).
Incidentally, this also implements support for vector argument registers,
so long as they are not on the stack.
llvm-svn: 28331
2006-05-16 18:18:50 +00:00
20eb2ce871
this should be 128 I think
...
llvm-svn: 28330
2006-05-16 17:45:23 +00:00
1dc9ec5874
Move this code to a common place
...
llvm-svn: 28329
2006-05-16 17:42:15 +00:00
c7df70db57
Implement the custom lowering hook right, returning values for all of the
...
arguments at once.
llvm-svn: 28327
2006-05-16 17:14:26 +00:00
7b8b8bbbf9
Fix a bug I introduced yesterday, which broke functions with *no* arguments.
...
llvm-svn: 28326
2006-05-16 17:08:35 +00:00
9fee442e63
X86 integer register classes naming changes. Make them consistent with FP, vector classes.
...
llvm-svn: 28324
2006-05-16 07:21:53 +00:00
3d82699605
Add a chain to FORMAL_ARGUMENTS. This is a minimal port of the X86 backend,
...
it doesn't currently use/maintain the chain properly. Also, make the
X86ISelLowering.cpp file 80-col clean.
llvm-svn: 28320
2006-05-16 06:45:34 +00:00
788db2c812
Replace "../whatever.td" with "whatever.td", so that out-of-tree backends
...
can just add lib/Target to TableGen includes.
llvm-svn: 28318
2006-05-16 06:39:36 +00:00
d2ca9abf57
Fit in 80 cols
...
llvm-svn: 28311
2006-05-16 04:20:24 +00:00
4abf33f56e
add an abort after every assert(0)
...
llvm-svn: 28310
2006-05-15 22:34:39 +00:00
fce45ffcd6
Improve comment, patch provided by Vladimir Prus!
...
llvm-svn: 28307
2006-05-15 18:35:02 +00:00
04a9e38369
Remove some dead code, identified by coverity.
...
llvm-svn: 28303
2006-05-15 05:48:32 +00:00
ffdc24b847
added a skeleton of the ARM backend
...
llvm-svn: 28301
2006-05-14 22:18:28 +00:00
215280d8b9
Update comment.
...
llvm-svn: 28283
2006-05-14 02:05:19 +00:00
768bc20b74
Fix build breakage :(
...
llvm-svn: 28267
2006-05-12 23:26:11 +00:00
b19ce6c810
More coverity fixes
...
llvm-svn: 28266
2006-05-12 21:14:20 +00:00
22f95b74ba
Dead variable
...
llvm-svn: 28265
2006-05-12 21:12:22 +00:00
ae48a894b1
Remove dead var, fix bad override.
...
llvm-svn: 28264
2006-05-12 21:09:57 +00:00
db30388d48
Remove dead code
...
llvm-svn: 28261
2006-05-12 19:03:56 +00:00
d63ec521c5
Actually override the right method. :)
...
Bug identified by coverity.
llvm-svn: 28259
2006-05-12 18:19:25 +00:00
132322b96e
remove dead variable.
...
llvm-svn: 28258
2006-05-12 18:17:25 +00:00
f76c42776d
remove dead variable.
...
llvm-svn: 28248
2006-05-12 17:33:59 +00:00
9cd2ef34e6
Remove dead variable.
...
llvm-svn: 28247
2006-05-12 17:31:21 +00:00
a296339c87
Fix PowerPC/2006-05-12-rlwimi-crash.ll
...
Nate, please verify that if InsertMask is 0, rlwimi shouldn't be used.
This fixes the crash and causes no PPC testsuite regressions.
llvm-svn: 28243
2006-05-12 16:29:37 +00:00
5fea9f0a93
Add a method to generate a string representation from a TargetData.
...
This continues the work on PR 761.
llvm-svn: 28239
2006-05-12 07:01:44 +00:00
8c2c1e90c4
Refactor a bunch of includes so that TargetMachine.h doesn't have to include
...
TargetData.h. This should make recompiles a bit faster with my current
TargetData tinkering.
llvm-svn: 28238
2006-05-12 06:33:49 +00:00
d7c77b8c56
Fix some tabbing issues.
...
llvm-svn: 28237
2006-05-12 06:06:55 +00:00
8d7774cb1d
Add a new constructor to TargetData that builds a TargetData from its
...
string representation.
This is part of PR 761.
llvm-svn: 28234
2006-05-12 05:49:47 +00:00
c30a5558f2
Typo! How did we commute nodes before?!
...
llvm-svn: 28229
2006-05-12 01:46:26 +00:00
dd7230c9e0
Add MOV16_rm / MOV32_rm and MOV16_mr / MOV32_mr to isLoadFromStackSlot and isStoreToStackSlot
...
llvm-svn: 28223
2006-05-11 07:33:49 +00:00
b25cb79604
Fix the PowerPC JIT-only failure on UnitTests/Vector/sumarray-dbl, which is
...
really a bad codegen bug that LLC happens to get lucky with. I must chat with
Nate for the proper fix.
llvm-svn: 28213
2006-05-10 06:38:32 +00:00
2814134a5d
Indent .data/.text in the .s file
...
llvm-svn: 28204
2006-05-09 16:15:00 +00:00
fc532fe1b7
Remove a completed entry.
...
llvm-svn: 28199
2006-05-09 06:54:05 +00:00
4ebc6a2311
Implement MASM sections correctly, without a "has masm sections flag" and a bunch of special case code.
...
llvm-svn: 28194
2006-05-09 05:33:48 +00:00
0b7acaf027
MASM doesn't have one of these.
...
llvm-svn: 28190
2006-05-09 05:21:47 +00:00
e0006c6794
Preserve prior behavior
...
llvm-svn: 28187
2006-05-09 05:15:24 +00:00
d0201946ad
Fix the MASM asmprinter's lies. It does not want to emit code to .text/.data
...
it wants it emitted to _text/_data.
llvm-svn: 28185
2006-05-09 05:12:53 +00:00
8488ba2e41
Split SwitchSection into SwitchTo{Text|Data}Section methods.
...
llvm-svn: 28184
2006-05-09 04:59:56 +00:00
8587f8885d
Some notes and thoughts to myself
...
llvm-svn: 28182
2006-05-09 04:58:46 +00:00
aa193d80a9
Another bad case I noticed
...
llvm-svn: 28177
2006-05-08 21:39:45 +00:00
5bcea612f4
add a note
...
llvm-svn: 28176
2006-05-08 21:24:21 +00:00
ce6646c366
Yet more readme updating
...
llvm-svn: 28172
2006-05-08 20:54:02 +00:00
68a45419cc
New note about something bad happening in target independent optimizers
...
llvm-svn: 28170
2006-05-08 20:08:28 +00:00
0eb8f2e496
Proving once again that I am not as smart as the compiler
...
llvm-svn: 28169
2006-05-08 19:09:24 +00:00
9b6d4c2968
Fold more shifts into inserts, and update the README
...
llvm-svn: 28168
2006-05-08 17:38:32 +00:00
10c653744e
When tracking demanded bits, if any bits from the sext of an SRA are demanded,
...
then so is the input sign bit. This fixes mediabench/g721 on X86.
llvm-svn: 28166
2006-05-08 17:22:53 +00:00
9733bde74c
Fixing truncate. Previously we were emitting truncate from r16 to r8 as
...
movw. That is we promote the destination operand to r16. So
%CH = TRUNC_R16_R8 %BP
is emitted as
movw %bp, %cx.
This is incorrect. If %cl is live, it would be clobbered.
Ideally we want to do the opposite, that is emitted it as
movb ??, %ch
But this is not possible since %bp does not have a r8 sub-register.
We are now defining a new register class R16_ which is a subclass of R16
containing only those 16-bit registers that have r8 sub-registers (i.e.
AX - DX). We isel the truncate to two instructions, a MOV16to16_ to copy the
value to the R16_ class, followed by a TRUNC_R16_R8.
Due to bug 770, the register colaescer is not going to coalesce between R16 and
R16_. That will be fixed later so we can eliminate the MOV16to16_. Right now, it
can only be eliminated if we are lucky that source and destination registers are
the same.
llvm-svn: 28164
2006-05-08 08:01:26 +00:00
dc996b3f6c
Update some stuff now that the new rlwimi code has gone in
...
llvm-svn: 28162
2006-05-08 02:52:38 +00:00
6732dcd5b3
Typo's
...
llvm-svn: 28158
2006-05-07 10:10:20 +00:00
1333cead5b
New rlwimi implementation, which is superior to the old one. There are
...
still a couple missed optimizations, but we now generate all the possible
rlwimis for multiple inserts into the same bitfield. More regression tests
to come.
llvm-svn: 28156
2006-05-07 00:23:38 +00:00
cd4a643728
Use ComputeMaskedBits to determine # sign bits as a fallback. This allows us
...
to handle all kinds of stuff, including silly things like:
sextinreg(setcc,i16) -> setcc.
llvm-svn: 28155
2006-05-06 23:48:13 +00:00
4f3de3e33c
Add some more sign propagation cases
...
llvm-svn: 28154
2006-05-06 23:40:29 +00:00
f86075731d
Add some more simple sign bit propagation cases.
...
llvm-svn: 28149
2006-05-06 22:39:59 +00:00
ce9b9fe6eb
Fix some loose ends in MASM support.
...
llvm-svn: 28148
2006-05-06 21:27:14 +00:00
7206d74f0c
Add some really really simple code for computing sign-bit propagation.
...
This will certainly be enhanced in the future.
llvm-svn: 28145
2006-05-06 09:27:13 +00:00
6d4a2dc4ad
Teach the X86 backend about non-i32 inline asm register classes.
...
llvm-svn: 28139
2006-05-06 00:29:37 +00:00
86a1467fc0
Fold (trunc (srl x, c)) -> (srl (trunc x), c)
...
llvm-svn: 28138
2006-05-06 00:11:52 +00:00
0f64932a5c
Implement ComputeMaskedBits/SimplifyDemandedBits for ISD::TRUNCATE
...
llvm-svn: 28135
2006-05-05 22:32:12 +00:00
8b9e11c110
Print a grouping around inline asm blocks so that we can tell when we are
...
using them.
llvm-svn: 28134
2006-05-05 21:50:04 +00:00
c22d4bede5
Print *some* grouping around inline asm blocks so we know where they are.
...
llvm-svn: 28133
2006-05-05 21:48:50 +00:00
44a73e9fa5
Teach the code generator to use cvtss2sd as extload f32 -> f64
...
llvm-svn: 28131
2006-05-05 21:35:18 +00:00
52c22512b9
Need extload patterns after Chris' DAG combiner changes
...
llvm-svn: 28127
2006-05-05 08:23:07 +00:00
ddb6cc1d8e
Better implementation of truncate. ISel matches it to a pseudo instruction
...
that gets emitted as movl (for r32 to i16, i8) or a movw (for r16 to i8). And
if the destination gets allocated a subregister of the source operand, then
the instruction will not be emitted at all.
llvm-svn: 28119
2006-05-05 05:40:20 +00:00
304bbf3b1d
New note, Nate, please check to see if I'm full of it :)
...
llvm-svn: 28118
2006-05-05 05:36:15 +00:00
469647bf38
Remove and simplify some more machineinstr/machineoperand stuff.
...
llvm-svn: 28105
2006-05-04 18:16:01 +00:00
10b71c0d08
Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling.
...
llvm-svn: 28104
2006-05-04 18:05:43 +00:00
10d6341618
Move some methods out of MachineInstr into MachineOperand
...
llvm-svn: 28102
2006-05-04 17:52:23 +00:00
fef7a2d0f5
There shalt be only one "immediate" operand type!
...
llvm-svn: 28099
2006-05-04 17:21:20 +00:00
13d5f3eb05
Revert Nate's CR patch from last night, which caused many regressions (e.g. fhourstones).
...
Loading and storing off R0 isn't what we wanted. Also, taking some CR's out of
CRRC seems to cause failures as well. Further investigation is required.
llvm-svn: 28097
2006-05-04 16:56:45 +00:00
06041abeb6
Make external globals public; other minor cleanup.
...
llvm-svn: 28096
2006-05-04 16:20:22 +00:00
f812a4fa75
Make Intel syntax the default when LLVM is built with VC++.
...
llvm-svn: 28095
2006-05-04 16:19:27 +00:00
ee64b6b40f
Remove a bunch more dead V9 specific stuff
...
llvm-svn: 28094
2006-05-04 01:26:39 +00:00
940cc978ef
Remove a bunch more SparcV9 specific stuff
...
llvm-svn: 28093
2006-05-04 01:15:02 +00:00
6e663f1c1e
Remove some more V9-specific stuff.
...
llvm-svn: 28092
2006-05-04 00:49:59 +00:00
9f6639b64d
Remove some more unused stuff from MachineInstr that was leftover from V9.
...
llvm-svn: 28091
2006-05-04 00:44:25 +00:00
2aef59f123
Simplify handling of relocations
...
llvm-svn: 28090
2006-05-04 00:42:08 +00:00
8b1cde2bbe
Use movsd to shuffle in the lowest two elements of a v4f32 / v4i32 vector when
...
movlps cannot be used (e.g. when load from m64 has multiple uses).
llvm-svn: 28089
2006-05-03 20:32:03 +00:00
e3a9c70ba0
Change from using MachineRelocation ctors to using static methods
...
in MachineRelocation to create Relocations.
llvm-svn: 28088
2006-05-03 20:30:20 +00:00
9e68942d78
inline a simple method
...
llvm-svn: 28083
2006-05-03 17:21:32 +00:00
1d8ee1fc80
Suck block address tracking out of targets into the JIT Emitter. This
...
simplifies the MachineCodeEmitter interface just a little bit and makes
BasicBlocks work like constant pools and jump tables.
llvm-svn: 28082
2006-05-03 17:10:41 +00:00
9954bc9c19
Fix a bug in Owen's checkin that broke the CBE on all non sparc v9 platforms.
...
llvm-svn: 28081
2006-05-03 05:48:41 +00:00
43b1ed7e3d
Teach the x86 jit how to handle jump tables not directly used by a jump
...
instruction.
llvm-svn: 28080
2006-05-03 04:52:47 +00:00
20a631fde7
Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.
...
This fixes PR 759.
llvm-svn: 28074
2006-05-03 01:29:57 +00:00
d8b192ba3b
Change the BasicBlockAddrs map to be a vector, indexed by MBB number.
...
llvm-svn: 28069
2006-05-03 00:32:55 +00:00
0267807ddc
Keep the alpha JIT similar to the PPC/X86 jits
...
llvm-svn: 28068
2006-05-03 00:31:21 +00:00
b8065a9a3a
Several related changes:
...
1. Change several methods in the MachineCodeEmitter class to be pure virtual.
2. Suck emitConstantPool/initJumpTableInfo into startFunction, removing them
from the MachineCodeEmitter interface, and reducing the amount of target-
specific code.
3. Change the JITEmitter so that it allocates constantpools and jump tables
*right* next to the functions that they belong to, instead of in a separate
pool of memory. This makes all memory for a function be contiguous, and
means the JITEmitter only tracks one block of memory now.
llvm-svn: 28065
2006-05-02 23:22:24 +00:00
233391f5f5
Remove some stuff from the README
...
llvm-svn: 28063
2006-05-02 22:43:31 +00:00
e1c96369e2
Fix a purely hypothetical problem (for now): emitWord emits in the host
...
byte format. This doesn't work when using the code emitter in a cross target
environment. Since the code emitter is only really used by the JIT, this
isn't a current problem, but if we ever start emitting .o files, it would be.
llvm-svn: 28060
2006-05-02 19:14:47 +00:00
c9aa3715e8
Refactor the machine code emitter interface to pull the pointers for the current
...
code emission location into the base class, instead of being in the derived classes.
This change means that low-level methods like emitByte/emitWord now are no longer
virtual (yaay for speed), and we now have a framework to support growable code
segments. This implements feature request #1 of PR469.
llvm-svn: 28059
2006-05-02 18:27:26 +00:00
bbcbf48aab
Since we don't handle callee-save CRs right yet, don't allocate them. Also
...
don't step on R11 in the middle of a function when saving and restoring CRs
llvm-svn: 28058
2006-05-02 17:37:31 +00:00
287dc5be0d
Hooray, everyone now uses the same printBasicBlockLabel implementation
...
llvm-svn: 28056
2006-05-02 17:34:51 +00:00
5bc9c583e3
There is no reason to use a virtual method to store this word.
...
llvm-svn: 28053
2006-05-02 17:16:20 +00:00
b9d4f8324d
Extend printBasicBlockLabel a bit so that it can be used to print all
...
basic block labels, consolidating the code to do so in one place for each
target.
llvm-svn: 28050
2006-05-02 05:37:32 +00:00
01364fbba8
Update the PPC compilation callback code to not need weird abi-violating
...
prologs and epilogs, keep all the asm in one place, and remove use of
compiler builtin functions.
llvm-svn: 28049
2006-05-02 04:50:05 +00:00
470f431f44
De-virtualize SwitchSection.
...
llvm-svn: 28047
2006-05-02 03:58:45 +00:00
f34ddb1e0d
De-virtualize EmitZeroes.
...
llvm-svn: 28046
2006-05-02 03:46:13 +00:00
bfe9ffb449
Finish support for Microsoft ML/MASM. May still be a few rough edges.
...
llvm-svn: 28045
2006-05-02 03:11:50 +00:00
24a62a9bc1
Make Intel syntax mode friendlier to Microsoft ML assembler (still needs more work).
...
llvm-svn: 28044
2006-05-02 01:16:28 +00:00
85e9909755
Put PHI/INLINEASM into the correct namespace.
...
llvm-svn: 28037
2006-05-01 17:00:49 +00:00
563f0417d2
Remove %'s from register names when in intel mode.
...
llvm-svn: 28027
2006-05-01 05:53:50 +00:00
71c2e0f262
Mingw32 patches supplied by Anton Korobeynikov.
...
llvm-svn: 28023
2006-04-29 18:41:44 +00:00
d369603df9
I can't spell: Register, not Regsiter.
...
llvm-svn: 28021
2006-04-28 23:19:39 +00:00
b244b80172
Implemented x86 inline asm b, h, w, k modifiers.
...
llvm-svn: 28020
2006-04-28 23:11:40 +00:00
84b49d51be
Fix CodeGen/Generic/2006-04-28-Sign-extend-bool.ll
...
llvm-svn: 28017
2006-04-28 21:56:10 +00:00
88decded82
Initial caller side support (for CCC only, not FastCC) of 128-bit vector
...
passing by value.
llvm-svn: 28015
2006-04-28 21:29:37 +00:00
68a44dc445
Bare-bone X86 inline asm printer support.
...
llvm-svn: 28014
2006-04-28 21:19:05 +00:00
3cd4362ade
Implement four-wide shuffle with 2 shufps if no more than two elements come
...
from each vector. e.g.
shuffle(G1, G2, 7, 1, 5, 2)
==>
movaps _G2, %xmm0
shufps $151, _G1, %xmm0
shufps $216, %xmm0, %xmm0
llvm-svn: 28011
2006-04-28 07:03:38 +00:00
d43c5c6046
TargetLowering::LowerArguments should return a VBIT_CONVERT of
...
FORMAL_ARGUMENTS SDOperand in the return result vector.
llvm-svn: 28009
2006-04-28 05:25:15 +00:00
f0157cb0bc
Use movaps instead of movapd for spill / restore.
...
llvm-svn: 28005
2006-04-28 02:23:35 +00:00
a4c2c4a276
Add a note
...
llvm-svn: 27999
2006-04-28 00:04:05 +00:00
b209131b56
Add a note
...
llvm-svn: 27998
2006-04-27 21:40:57 +00:00
f4f3f0d25f
Make x86 isel lowering produce tailcall nodes. They are match to normal calls
...
for now.
Patch contributed by Alexander Friedman.
llvm-svn: 27994
2006-04-27 08:40:39 +00:00
ec04a37edd
A couple of new entries.
...
llvm-svn: 27993
2006-04-27 08:31:33 +00:00
89001ad729
Support for passing 128-bit vector arguments via XMM registers.
...
llvm-svn: 27992
2006-04-27 08:31:10 +00:00
a0374e1bed
Oops
...
llvm-svn: 27989
2006-04-27 05:44:50 +00:00
24eb3f4765
Bug fix: not updating NumIntRegs.
...
llvm-svn: 27988
2006-04-27 05:35:28 +00:00
48940d16b2
- Clean up formal argument lowering code. Prepare for vector pass by value work.
...
- Fixed vararg support.
llvm-svn: 27985
2006-04-27 01:32:22 +00:00
1c39903297
Fix fastcc failures.
...
llvm-svn: 27980
2006-04-26 18:21:31 +00:00
e0bcfbe811
Switching over FORMAL_ARGUMENTS mechanism to lower call arguments.
...
llvm-svn: 27975
2006-04-26 01:20:17 +00:00
4530327c04
Keep the stack from on darwin 16-byte aligned. This fixes many JIT
...
failres.
llvm-svn: 27973
2006-04-25 20:54:26 +00:00
a9467aab0a
Separate LowerOperation() into multiple functions, one per opcode.
...
llvm-svn: 27972
2006-04-25 20:13:52 +00:00
4cc3e0b05f
Fix a typo.
...
llvm-svn: 27968
2006-04-25 17:48:41 +00:00
318bb96f9e
No functionality changes, but cleaner code with correct comments.
...
llvm-svn: 27966
2006-04-25 04:45:59 +00:00
fb46b2bf5d
Explicitly specify result type for def : Pat<> patterns (if it produces a vector
...
result). Otherwise tblgen will pick the default (v16i8 for 128-bit vector).
llvm-svn: 27965
2006-04-25 00:50:01 +00:00
25b09295f8
Added X86 SSE2 intrinsics which can be represented as vector_shuffles. This is
...
a temporary workaround for the 2-wide vector_shuffle problem (i.e. its mask
would have type v2i32 which is not legal).
llvm-svn: 27964
2006-04-24 23:34:56 +00:00
d03631ee76
Add a new entry.
...
llvm-svn: 27963
2006-04-24 23:30:10 +00:00
5c2bfb069e
Special case handling two wide build_vector(0, x).
...
llvm-svn: 27961
2006-04-24 22:58:52 +00:00
63bd4d3730
Some missing movlps, movhps, movlpd, and movhpd patterns.
...
llvm-svn: 27960
2006-04-24 21:58:20 +00:00
b0461080e4
A little bit more build_vector enhancement for v8i16 cases.
...
llvm-svn: 27959
2006-04-24 18:01:45 +00:00
2f9b0bcbd5
Remove a completed entry.
...
llvm-svn: 27958
2006-04-24 17:38:16 +00:00
ab0ee6340c
MakeMIInst() should handle jump table index operands.
...
llvm-svn: 27955
2006-04-24 05:37:35 +00:00
f110527a29
Add a note
...
llvm-svn: 27954
2006-04-23 19:47:09 +00:00
b4f31dd1a8
MOVL shuffle (i.e. movd or movss / movsd from memory) of undef, V2 == V2
...
llvm-svn: 27953
2006-04-23 06:35:19 +00:00
9f0b13c885
Optimized stores to the constant pool, while cool, are unnecessary.
...
llvm-svn: 27948
2006-04-22 22:31:45 +00:00
4ca2ea5b43
JumpTable support! What this represents is working asm and jit support for
...
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.
llvm-svn: 27947
2006-04-22 18:53:45 +00:00
e728efdfce
Don't do all the lowering stuff for 2-wide build_vector's. Also, minor optimization for shuffle of undef.
...
llvm-svn: 27946
2006-04-22 08:34:05 +00:00
16ef94f4e8
Fix a performance regression. Use {p}shuf* when there are only two distinct elements in a build_vector.
...
llvm-svn: 27945
2006-04-22 06:21:46 +00:00
c8afdfec52
Teach the JIT how to relocate LI, this fixes the JIT on Prolangs-C/TimberWolfMC
...
llvm-svn: 27943
2006-04-22 06:17:56 +00:00
14215c36b6
Revamp build_vector lowering to take advantage of movss and movd instructions.
...
movd always clear the top 96 bits and movss does so when it's loading the
value from memory.
The net result is codegen for 4-wide shuffles is much improved. It is near
optimal if one or more elements is a zero. e.g.
__m128i test(int a, int b) {
return _mm_set_epi32(0, 0, b, a);
}
compiles to
_test:
movd 8(%esp), %xmm1
movd 4(%esp), %xmm0
punpckldq %xmm1, %xmm0
ret
compare to gcc:
_test:
subl $12, %esp
movd 20(%esp), %xmm0
movd 16(%esp), %xmm1
punpckldq %xmm0, %xmm1
movq %xmm1, %xmm0
movhps LC0, %xmm0
addl $12, %esp
ret
or icc:
_test:
movd 4(%esp), %xmm0 #5.10
movd 8(%esp), %xmm3 #5.10
xorl %eax, %eax #5.10
movd %eax, %xmm1 #5.10
punpckldq %xmm1, %xmm0 #5.10
movd %eax, %xmm2 #5.10
punpckldq %xmm2, %xmm3 #5.10
punpckldq %xmm3, %xmm0 #5.10
ret #5.10
There are still room for improvement, for example the FP variant of the above example:
__m128 test(float a, float b) {
return _mm_set_ps(0.0, 0.0, b, a);
}
_test:
movss 8(%esp), %xmm1
movss 4(%esp), %xmm0
unpcklps %xmm1, %xmm0
xorps %xmm1, %xmm1
movlhps %xmm1, %xmm0
ret
The xorps and movlhps are unnecessary. This will require post legalizer optimization to handle.
llvm-svn: 27939
2006-04-21 23:03:30 +00:00
57a32f0bc1
Fix the comment
...
llvm-svn: 27938
2006-04-21 22:11:27 +00:00
516b393992
Change the PPC JIT to use a Static relocation model
...
llvm-svn: 27937
2006-04-21 22:04:15 +00:00
3e62d4b289
fix thinko
...
llvm-svn: 27935
2006-04-21 21:05:22 +00:00
e1f9ab7d53
add some low-prio notes
...
llvm-svn: 27934
2006-04-21 21:03:21 +00:00
e8b5180044
Now generating perfect (I think) code for "vector set" with a single non-zero
...
scalar value.
e.g.
_mm_set_epi32(0, a, 0, 0);
==>
movd 4(%esp), %xmm0
pshufd $69, %xmm0, %xmm0
_mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
movzbw 4(%esp), %ax
movzwl %ax, %eax
pxor %xmm0, %xmm0
pinsrw $5, %eax, %xmm0
llvm-svn: 27923
2006-04-21 01:05:10 +00:00
99d3da9d2c
Fix the CodeGen/PowerPC/buildvec_canonicalize.ll regression last night.
...
llvm-svn: 27908
2006-04-20 19:01:30 +00:00
d1c3a067ee
add a note
...
llvm-svn: 27907
2006-04-20 18:49:28 +00:00
3e5521799c
remove some v9 specific code
...
llvm-svn: 27900
2006-04-20 18:33:11 +00:00
2a875285f7
Remove this obsolete file
...
llvm-svn: 27895
2006-04-20 18:16:45 +00:00
ac61195539
This target is no longer built. The ,v files now live in the reoptimizer.
...
llvm-svn: 27885
2006-04-20 17:15:44 +00:00
60f0b8998e
- Added support to turn "vector clear elements", e.g. pand V, <-1, -1, 0, -1>
...
to a vector shuffle.
- VECTOR_SHUFFLE lowering change in preparation for more efficient codegen
of vector shuffle with zero (or any splat) vector.
llvm-svn: 27875
2006-04-20 08:58:49 +00:00
0cd0065c58
Make sure that the new instructions selected have the right type. This fixes
...
CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll
llvm-svn: 27868
2006-04-20 05:58:10 +00:00
15c264b753
Handle v2i64 BUILD_VECTOR custom lowering correctly. v2i64 is a legal type,
...
but i64 is not. If possible, change a i64 op to a f64 (e.g. load, constant)
and then cast it back.
llvm-svn: 27849
2006-04-20 00:11:39 +00:00
4a1b0d3292
isSplatMask() bug: first element can be an undef.
...
llvm-svn: 27847
2006-04-19 23:28:59 +00:00
a3caaee503
- Added support to do aribitrary 4 wide shuffle with no more than three
...
instructions.
- Fixed a commute vector_shuff bug.
llvm-svn: 27845
2006-04-19 22:48:17 +00:00
6d5297dac3
Prefer {p}unpack* and mov*dup over {p}shuf* as well.
...
llvm-svn: 27844
2006-04-19 21:15:24 +00:00
52df74000a
Renamed AddedCost to AddedComplexity.
...
llvm-svn: 27843
2006-04-19 20:38:28 +00:00
b416a25174
- Renamed AddedCost to AddedComplexity.
...
- Added more movhlps and movlhps patterns.
llvm-svn: 27842
2006-04-19 20:37:34 +00:00
7855e4d032
Commute vector_shuffle to match more movlhps, movlp{s|d} cases.
...
llvm-svn: 27840
2006-04-19 20:35:22 +00:00
cc7abc6c38
More mov{h|l}p{d|s} patterns.
...
llvm-svn: 27836
2006-04-19 18:20:17 +00:00
aeb09ccdd3
- More mov{h|l}ps patterns.
...
- Increase cost (complexity) of patterns which match mov{h|l}ps ops. These
are preferred over shufps in most cases.
llvm-svn: 27835
2006-04-19 18:11:52 +00:00
aa3325e925
Allow "let AddedCost = n in" to increase pattern complexity.
...
llvm-svn: 27834
2006-04-19 18:07:24 +00:00
05bbec5020
add a note
...
llvm-svn: 27832
2006-04-19 16:22:38 +00:00
a922a516b0
add a note
...
llvm-svn: 27828
2006-04-19 05:55:06 +00:00
bfab82817a
Add a note.
...
llvm-svn: 27827
2006-04-19 05:53:27 +00:00
3823aa1d0f
- PEXTRW cannot take a memory location as its first source operand.
...
- PINSRWrmi encoding bug.
llvm-svn: 27818
2006-04-18 21:59:43 +00:00
43f4ef4ffb
SHUFP{S|D}, PSHUF* encoding bugs. Left out the mask immediate operand.
...
llvm-svn: 27817
2006-04-18 21:56:36 +00:00
a179ea631d
Name change for clarity sake
...
llvm-svn: 27816
2006-04-18 21:55:35 +00:00
09e36ef710
Encoding bug: CMPPSrmi, CMPPDrmi dropped operand 2 (condtion immediate).
...
llvm-svn: 27815
2006-04-18 21:31:08 +00:00
d799d680f4
Name change for clarity sake
...
llvm-svn: 27814
2006-04-18 21:29:50 +00:00
0ee281f37c
Left a pattern out
...
llvm-svn: 27813
2006-04-18 21:29:08 +00:00
34c901b50e
These are correctly encoded by the JIT. I checked :)
...
llvm-svn: 27810
2006-04-18 19:03:38 +00:00
197d762232
add a note
...
llvm-svn: 27809
2006-04-18 18:30:19 +00:00
518834c67e
Fix a crash on:
...
void foo2(vector float *A, vector float *B) {
vector float C = (vector float)vec_cmpeq(*A, *B);
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
*A = C;
}
llvm-svn: 27808
2006-04-18 18:28:22 +00:00
e2d25a1a50
Fixed an encoding bug: movd from XMM to R32.
...
llvm-svn: 27807
2006-04-18 18:19:00 +00:00
1e174c87c3
pretty print node name
...
llvm-svn: 27806
2006-04-18 18:05:58 +00:00
9754d142a4
Implement an important entry from README_ALTIVEC:
...
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
llvm-svn: 27804
2006-04-18 17:59:36 +00:00
68c16a201e
move some stuff around, clean things up
...
llvm-svn: 27802
2006-04-18 17:52:36 +00:00
bfc2c68386
Teach the codegen about instructions used for SSE spill code, allowing it
...
to optimize cases where it has to spill a lot
llvm-svn: 27801
2006-04-18 16:44:51 +00:00
96d50487c9
Use vmladduhm to do v8i16 multiplies which is faster and simpler than doing
...
even/odd halves. Thanks to Nate telling me what's what.
llvm-svn: 27793
2006-04-18 04:28:57 +00:00
d6d82aa889
Implement v16i8 multiply with this code:
...
vmuloub v5, v3, v2
vmuleub v2, v3, v2
vperm v2, v2, v5, v4
This implements CodeGen/PowerPC/vec_mul.ll. With this, v16i8 multiplies are
6.79x faster than before.
Overall, UnitTests/Vector/multiplies.c is now 2.45x faster with LLVM than with
GCC.
Remove the 'integer multiplies' todo from the README file.
llvm-svn: 27792
2006-04-18 03:57:35 +00:00
4d36a36900
Correct comments
...
llvm-svn: 27790
2006-04-18 03:45:01 +00:00
7e439874cb
Lower v8i16 multiply into this code:
...
li r5, lo16(LCPI1_0)
lis r6, ha16(LCPI1_0)
lvx v4, r6, r5
vmulouh v5, v3, v2
vmuleuh v2, v3, v2
vperm v2, v2, v5, v4
where v4 is:
LCPI1_0: ; <16 x ubyte>
.byte 2
.byte 3
.byte 18
.byte 19
.byte 6
.byte 7
.byte 22
.byte 23
.byte 10
.byte 11
.byte 26
.byte 27
.byte 14
.byte 15
.byte 30
.byte 31
This is 5.07x faster on the G5 (measured) than lowering to scalar code +
loads/stores.
llvm-svn: 27789
2006-04-18 03:43:48 +00:00
a2cae1bb10
Custom lower v4i32 multiplies into a cute sequence, instead of having legalize
...
scalarize the sequence into 4 mullw's and a bunch of load/store traffic.
This speeds up v4i32 multiplies 4.1x (measured) on a G5. This implements
PowerPC/vec_mul.ll
llvm-svn: 27788
2006-04-18 03:24:30 +00:00
0ef233509b
Another entry
...
llvm-svn: 27786
2006-04-18 01:22:57 +00:00
e008bd3d27
Another entry.
...
llvm-svn: 27784
2006-04-18 00:21:01 +00:00
5421206c4b
Use movss to insert_vector_elt(v, s, 0).
...
llvm-svn: 27782
2006-04-17 22:45:49 +00:00
6e5e205841
Use two pinsrw to insert an element into v4i32 / v4f32 vector.
...
llvm-svn: 27779
2006-04-17 22:04:06 +00:00
63a5cdc423
remove done item
...
llvm-svn: 27778
2006-04-17 21:52:03 +00:00
6bd68ae81e
Don't diddle VRSAVE if no registers need to be added/removed from it. This
...
allows us to codegen functions as:
_test_rol:
vspltisw v2, -12
vrlw v2, v2, v2
blr
instead of:
_test_rol:
mfvrsave r2, 256
mr r3, r2
mtvrsave r3
vspltisw v2, -12
vrlw v2, v2, v2
mtvrsave r2
blr
Testcase here: CodeGen/PowerPC/vec_vrsave.ll
llvm-svn: 27777
2006-04-17 21:48:13 +00:00
22c06f054b
Encoding bug
...
llvm-svn: 27773
2006-04-17 21:33:57 +00:00
72d7c27069
Vectors that are known live-in and live-out are clearly already marked in
...
the vrsave register for the caller. This allows us to codegen a function as:
_test_rol:
mfspr r2, 256
mr r3, r2
mtspr 256, r3
vspltisw v2, -12
vrlw v2, v2, v2
mtspr 256, r2
blr
instead of:
_test_rol:
mfspr r2, 256
oris r3, r2, 40960
mtspr 256, r3
vspltisw v0, -12
vrlw v2, v0, v0
mtspr 256, r2
blr
llvm-svn: 27772
2006-04-17 21:22:06 +00:00
14c4972b6d
Prefer to allocate V2-V5 before V0,V1. This lets us generate code like this:
...
vspltisw v2, -12
vrlw v2, v2, v2
instead of:
vspltisw v0, -12
vrlw v2, v0, v0
when a function is returning a value.
llvm-svn: 27771
2006-04-17 21:19:12 +00:00
6df094b4ab
Move some knowledge about registers out of the code emitter into the register info.
...
llvm-svn: 27770
2006-04-17 21:07:20 +00:00
0f28d48da2
Use a small table instead of macros to do this conversion.
...
llvm-svn: 27769
2006-04-17 20:59:25 +00:00
5022b3426e
Implement v8i16, v16i8 splat using unpckl + pshufd.
...
llvm-svn: 27768
2006-04-17 20:43:08 +00:00
c070c621ac
implement returns of a vector, testcase here: CodeGen/X86/vec_return.ll
...
llvm-svn: 27767
2006-04-17 20:32:50 +00:00
e54133cfba
Make sure to check splats of every constant we can, handle splat(31) by
...
being a bit more clever, add support for odd splats from -31 to -17.
llvm-svn: 27764
2006-04-17 18:09:22 +00:00
bf0d13c54f
Incorrect foldMemoryOperand entries
...
llvm-svn: 27763
2006-04-17 18:06:12 +00:00
5112b5c544
Errors in patterns preventing load folding
...
llvm-svn: 27762
2006-04-17 18:05:01 +00:00
e3955a05e4
Add checks for __OpenBSD__.
...
llvm-svn: 27761
2006-04-17 17:55:41 +00:00
264c908e3a
Teach the ppc backend to use rol and vsldoi to generate splatted constants.
...
This implements vec_constants.ll:test_vsldoi and test_rol
llvm-svn: 27760
2006-04-17 17:55:10 +00:00
26fb8d9393
add a note
...
llvm-svn: 27758
2006-04-17 17:29:41 +00:00
b3b41c4f3d
FP SETOLT, SETOLT, SETUGE, SETUGT conditions were implemented incorrectly
...
llvm-svn: 27755
2006-04-17 07:24:10 +00:00
1b3806ace5
Make some code more general, adding support for constant formation of several
...
new patterns.
llvm-svn: 27754
2006-04-17 06:58:41 +00:00
f8dd76df5b
Learn how to make odd splatted constants in range [17,29]. This implements
...
PowerPC/vec_constants.ll:test_29.
llvm-svn: 27752
2006-04-17 06:07:44 +00:00
2a099c04c1
Pull some code out into a helper function.
...
Effeciently codegen even splats in the range [-32,30].
This allows us to codegen <30,30,30,30> as:
vspltisw v0, 15
vadduwm v2, v0, v0
instead of as a cp load.
llvm-svn: 27750
2006-04-17 06:00:21 +00:00
071ad01ceb
Implement a TODO: for any shuffle that can be viewed as a v4[if]32 shuffle,
...
if it can be implemented in 3 or fewer discrete altivec instructions, codegen
it as such. This implements Regression/CodeGen/PowerPC/vec_perf_shuffle.ll
llvm-svn: 27748
2006-04-17 05:28:54 +00:00
85bfa3c2bc
Regenerate with adjusted costs
...
llvm-svn: 27746
2006-04-17 05:26:20 +00:00
aac2a200cd
Regenerate with correct offset
...
llvm-svn: 27744
2006-04-17 05:08:46 +00:00
311b1a6e23
Increase the opcodes by one each to disambiguate COPY from VMRGHW.
...
llvm-svn: 27742
2006-04-17 00:47:48 +00:00
07a3d01a91
Check in a table, generated by llvm-PerfectShuffle, of optimal shuffles
...
of various 4-element vectors.
llvm-svn: 27739
2006-04-17 00:37:02 +00:00
20712deecb
movduprm, movshduprm bugs
...
llvm-svn: 27734
2006-04-16 18:11:28 +00:00
3064f9aaa6
Encoding bugs
...
llvm-svn: 27733
2006-04-16 07:02:22 +00:00
685ddd8152
Can't fold loads into alias vector SSE ops used for scalar operation. The load
...
address has to be 16-byte aligned but the values aren't spilled to 128-bit
locations.
llvm-svn: 27732
2006-04-16 06:58:19 +00:00
06a21ba96b
Implement a TODO: have the legalizer canonicalize a bunch of operations to
...
one type (v4i32) so that we don't have to write patterns for each type, and
so that more CSE opportunities are exposed.
llvm-svn: 27731
2006-04-16 01:37:57 +00:00
fa5aa396c2
Make the BUILD_VECTOR lowering code much more aggressive w.r.t constant vectors.
...
Remove some done items from the todo list.
llvm-svn: 27729
2006-04-16 01:01:29 +00:00
24acbe46c0
Fix a crash when faced with a shuffle vector that has an undef in its mask.
...
llvm-svn: 27726
2006-04-15 23:48:05 +00:00
873202fabd
Add patterns for matching vnots with bit converted inputs. Most of these will
...
go away when I start using evan's binop type canonicalizer
llvm-svn: 27725
2006-04-15 23:45:24 +00:00
41df12ff4c
Add a new vnot_conv predicate for matching vnot's where the allones vector is
...
bitconverted from some other type.
llvm-svn: 27724
2006-04-15 23:39:14 +00:00
8f1d801389
More encoding bugs
...
llvm-svn: 27722
2006-04-15 06:10:09 +00:00
91944e8699
pslldrm, psrawrm, etc. encoding bug
...
llvm-svn: 27721
2006-04-15 05:59:08 +00:00
1220b31a31
hsubp{s|d} encoding bug
...
llvm-svn: 27720
2006-04-15 05:52:42 +00:00
6222cf2a36
Silly bug
...
llvm-svn: 27719
2006-04-15 05:37:34 +00:00
65bb720a8b
Do not use movs{h|l}dup for a shuffle with a single non-undef node.
...
llvm-svn: 27718
2006-04-15 03:13:24 +00:00
0ba896c75b
Added SSE (and other) entries to foldMemoryOperand().
...
llvm-svn: 27716
2006-04-14 23:33:27 +00:00
00a5b3d9d3
Some clean up
...
llvm-svn: 27715
2006-04-14 23:32:40 +00:00
559c8ba466
Allow undef in a shuffle mask
...
llvm-svn: 27714
2006-04-14 23:19:08 +00:00
5d247f81c1
Last few SSE3 intrinsics.
...
llvm-svn: 27711
2006-04-14 21:59:03 +00:00
3bd605397b
Misc. SSE2 intrinsics: clflush, lfench, mfence
...
llvm-svn: 27699
2006-04-14 07:43:12 +00:00
e349d01acf
We were not adjusting the frame size to ensure proper alignment when alloca /
...
vla are present in the function. This causes a crash when a leaf function
allocates space on the stack used to store / load with 128-bit SSE
instructions.
llvm-svn: 27698
2006-04-14 07:26:43 +00:00
8d76f3922b
New entry
...
llvm-svn: 27697
2006-04-14 07:24:04 +00:00
4211ca9108
Move the rest of the PPCTargetLowering::LowerOperation cases out into
...
separate functions, for simplicity and code clarity.
llvm-svn: 27693
2006-04-14 06:01:58 +00:00
19e9055eb5
Pull the VECTOR_SHUFFLE and BUILD_VECTOR lowering code out into separate
...
functions, which makes the code much cleaner :)
llvm-svn: 27692
2006-04-14 05:19:18 +00:00
eb0063a34f
pcmpeq* and pcmpgt* intrinsics.
...
llvm-svn: 27685
2006-04-14 01:39:53 +00:00
16287444ff
psll*, psrl*, and psra* intrinsics.
...
llvm-svn: 27684
2006-04-14 00:14:05 +00:00
64f6c11c59
Remove the .cvsignore file so this directory can be pruned.
...
llvm-svn: 27683
2006-04-13 22:00:10 +00:00
497ecf6840
Remove .cvsignore so that this directory can be pruned.
...
llvm-svn: 27682
2006-04-13 21:59:03 +00:00
a84319719c
Doh. PANDrm, etc. are not commutable.
...
llvm-svn: 27668
2006-04-13 18:11:28 +00:00
883fb053bd
Force non-darwin targets to use a static relo model. This fixes PR734,
...
tested by CodeGen/Generic/vector.ll
llvm-svn: 27657
2006-04-13 17:10:48 +00:00
5879efe0c8
add a note, move an altivec todo to the altivec list.
...
llvm-svn: 27654
2006-04-13 16:48:00 +00:00
9857229aba
Add the README files to the distribution.
...
llvm-svn: 27651
2006-04-13 06:39:24 +00:00
ed3996743f
psad, pmax, pmin intrinsics.
...
llvm-svn: 27647
2006-04-13 06:11:45 +00:00
58dad55959
Various SSE2 packed integer intrinsics: pmulhuw, pavgw, etc.
...
llvm-svn: 27645
2006-04-13 05:24:54 +00:00
e4f97ccf7f
X86 SSE2 supports v8i16 multiplication
...
llvm-svn: 27644
2006-04-13 05:10:25 +00:00
d2eb662415
Update
...
llvm-svn: 27643
2006-04-13 05:09:45 +00:00
b3fe00bdc6
padds{b|w}, paddus{b|w}, psubs{b|w}, psubus{b|w} intrinsics.
...
llvm-svn: 27639
2006-04-13 00:43:35 +00:00
0aab735a1a
Naming inconsistency.
...
llvm-svn: 27638
2006-04-13 00:00:23 +00:00
c88afc36a9
SSE / SSE2 conversion intrinsics.
...
llvm-svn: 27637
2006-04-12 23:42:44 +00:00
92232307d0
All "integer" logical ops (pand, por, pxor) are now promoted to v2i64.
...
Clean up and fix various logical ops issues.
llvm-svn: 27633
2006-04-12 21:21:57 +00:00
147e50e1c5
Add a new way to match vector constants, which make it easier to bang bits of
...
different types.
Codegen spltw(0x7FFFFFFF) and spltw(0x80000000) without a constant pool load,
implementing PowerPC/vec_constants.ll:test1. This compiles:
typedef float vf __attribute__ ((vector_size (16)));
typedef int vi __attribute__ ((vector_size (16)));
void test(vi *P1, vi *P2, vf *P3) {
*P1 &= (vi){0x80000000,0x80000000,0x80000000,0x80000000};
*P2 &= (vi){0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF};
*P3 = vec_abs((vector float)*P3);
}
to:
_test:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
vspltisw v0, -1
vslw v0, v0, v0
lvx v1, 0, r3
vand v1, v1, v0
stvx v1, 0, r3
lvx v1, 0, r4
vandc v1, v1, v0
stvx v1, 0, r4
lvx v1, 0, r5
vandc v0, v1, v0
stvx v0, 0, r5
mtspr 256, r2
blr
instead of (with two constant pool entries):
_test:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
li r6, lo16(LCPI1_0)
lis r7, ha16(LCPI1_0)
li r8, lo16(LCPI1_1)
lis r9, ha16(LCPI1_1)
lvx v0, r7, r6
lvx v1, 0, r3
vand v0, v1, v0
stvx v0, 0, r3
lvx v0, r9, r8
lvx v1, 0, r4
vand v1, v1, v0
stvx v1, 0, r4
lvx v1, 0, r5
vand v0, v1, v0
stvx v0, 0, r5
mtspr 256, r2
blr
GCC produces (with 2 cp entries):
_test:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc00c
mtspr 256,r0
lis r2,ha16(LC0)
lis r9,ha16(LC1)
la r2,lo16(LC0)(r2)
lvx v0,0,r3
lvx v1,0,r5
la r9,lo16(LC1)(r9)
lwz r12,-4(r1)
lvx v12,0,r2
lvx v13,0,r9
vand v0,v0,v12
stvx v0,0,r3
vspltisw v0,-1
vslw v12,v0,v0
vandc v1,v1,v12
stvx v1,0,r5
lvx v0,0,r4
vand v0,v0,v13
stvx v0,0,r4
mtspr 256,r12
blr
llvm-svn: 27624
2006-04-12 19:07:14 +00:00
74cf9ff761
Rename get_VSPLI_elt -> get_VSPLTI_elt
...
Canonicalize BUILD_VECTOR's that match VSPLTI's into a single type for each
form, eliminating a bunch of Pat patterns in the .td file and allowing us to
CSE stuff more aggressively. This implements
PowerPC/buildvec_canonicalize.ll:VSPLTI
llvm-svn: 27614
2006-04-12 17:37:20 +00:00
e2157c6e41
Promote v4i32, v8i16, v16i8 load to v2i64 load.
...
llvm-svn: 27612
2006-04-12 17:12:36 +00:00
e318a7574e
Ensure that zero vectors are always v4i32, which forces them to CSE with
...
each other. This implements CodeGen/PowerPC/vxor-canonicalize.ll
llvm-svn: 27609
2006-04-12 16:53:28 +00:00
29be057d92
Various SSE2 conversion intrinsics
...
llvm-svn: 27603
2006-04-12 05:20:24 +00:00
70c74a3ced
Added __builtin_ia32_storelv4si, __builtin_ia32_movqv4si,
...
__builtin_ia32_loadlv4si, __builtin_ia32_loaddqu, __builtin_ia32_storedqu.
llvm-svn: 27599
2006-04-11 22:28:25 +00:00
f19bcd5177
Fix SingleSource/UnitTests/Vector/sumarray-dbl
...
llvm-svn: 27594
2006-04-11 19:44:43 +00:00
1bb132099f
Fix PR727, correctly handling large stack aligments on ppc
...
llvm-svn: 27593
2006-04-11 19:29:21 +00:00
aaa04230bd
we have a shuffle instr, add an example.
...
llvm-svn: 27592
2006-04-11 18:47:03 +00:00
6b60357f4a
gcc lower SSE prefetch into generic prefetch intrinsic. Need to add support
...
later.
llvm-svn: 27591
2006-04-11 18:04:57 +00:00
6ea715af28
Misc. intrinsics.
...
llvm-svn: 27590
2006-04-11 17:35:57 +00:00
02b3b72bfc
Suppress debug label when not debug.
...
llvm-svn: 27588
2006-04-11 08:11:53 +00:00
09a956271a
movnt* and maskmovdqu intrinsics
...
llvm-svn: 27587
2006-04-11 06:57:30 +00:00
e4db08a2f1
Vector function results go into V2 according to GCC. The darwin ABI doc
...
doesn't say where they go :-/
llvm-svn: 27579
2006-04-11 01:38:39 +00:00
92533cfb4a
Move some return-handling code from lowerarguments to the ISD::RET handling stuff.
...
No functionality change.
llvm-svn: 27577
2006-04-11 01:21:43 +00:00
12ba3e23d0
Added support for _mm_move_ss and _mm_move_sd.
...
llvm-svn: 27575
2006-04-11 00:19:04 +00:00
dca2655daa
Use existing information.
...
llvm-svn: 27574
2006-04-10 23:09:19 +00:00
f8ac02283c
Remove some bogus patterns; clean up.
...
llvm-svn: 27569
2006-04-10 22:35:16 +00:00
d99f57c1e1
add a note
...
llvm-svn: 27567
2006-04-10 21:51:03 +00:00
051de9a82b
Remove an entry that is now done.
...
llvm-svn: 27565
2006-04-10 21:42:57 +00:00
76112c3cb8
Added some missing shuffle patterns.
...
llvm-svn: 27564
2006-04-10 21:42:19 +00:00
664fcba5fa
Correct an entry
...
llvm-svn: 27563
2006-04-10 21:41:39 +00:00
395fa3d2a6
movups / movupd
...
llvm-svn: 27562
2006-04-10 21:11:06 +00:00
617a6a812e
Conditional move of vector types.
...
llvm-svn: 27556
2006-04-10 07:23:14 +00:00
014849e121
New entries
...
llvm-svn: 27555
2006-04-10 07:22:03 +00:00
c9ed8e4c1a
Use movaps to do VR128 reg-to-reg copies for now. It's shorter and available for SSE1.
...
llvm-svn: 27554
2006-04-10 07:21:31 +00:00
3a68f3c3ca
properly mark vector selects as expanded to select_cc
...
llvm-svn: 27544
2006-04-08 22:59:15 +00:00
0a3d1bbca4
Add VRRC select support
...
llvm-svn: 27543
2006-04-08 22:45:08 +00:00
3f9c17906f
Disable switch lowering for targets based on the selection dag isel,
...
letting the code generator handle them directly.
llvm-svn: 27539
2006-04-08 19:46:55 +00:00
d9e80f4516
Implement PowerPC/CodeGen/vec_splat.ll:spltish to use vsplish instead of a
...
constant pool load.
llvm-svn: 27538
2006-04-08 07:14:26 +00:00
d71a1f946d
Change the interface to the predicate that determines if vsplti* can be used.
...
No functionality changes.
llvm-svn: 27536
2006-04-08 06:46:53 +00:00
cf905223c5
Initialize SDOperand values because the gcc 4.0.2 compiler complains about
...
them.
llvm-svn: 27534
2006-04-08 05:38:03 +00:00
0df9c9f57d
ldmxcsr and stmxcsr.
...
llvm-svn: 27506
2006-04-08 00:47:44 +00:00
ac847268c5
Code clean up.
...
llvm-svn: 27501
2006-04-07 21:53:05 +00:00
aa18a52545
Added patterns for MOVHPSmr and MOVLPSmr.
...
llvm-svn: 27497
2006-04-07 21:20:58 +00:00
748e573ce5
Keep track of an Mac OS X / x86 ABI bug.
...
llvm-svn: 27496
2006-04-07 21:19:53 +00:00
c0d6518f27
Make sure that debug labels are defined within the same section and after the
...
entry point of a function.
llvm-svn: 27494
2006-04-07 20:44:42 +00:00
2d7298c362
Foundation for call frame information.
...
llvm-svn: 27491
2006-04-07 16:34:46 +00:00
d8e1a01be6
A MOVPS2SSmr, i.e. _mm_store_ss, encoding bug.
...
Also MOVPDI2DIrr.
llvm-svn: 27476
2006-04-06 23:53:29 +00:00
c995b45f67
- movlp{s|d} and movhp{s|d} support.
...
- Normalize shuffle nodes so result vector lower half elements come from the
first vector, the rest come from the second vector. (Except for the
exceptions :-).
- Other minor fixes.
llvm-svn: 27474
2006-04-06 23:23:56 +00:00
acf8b3c828
New entries.
...
llvm-svn: 27473
2006-04-06 23:21:24 +00:00
1596a1b276
This may be overconservative, but it lets the new cfe compile
...
llvm-svn: 27471
2006-04-06 23:18:45 +00:00
e61cfad815
Add an item
...
llvm-svn: 27470
2006-04-06 23:16:19 +00:00
466841ddc7
Make sure to return the result in the right type.
...
llvm-svn: 27469
2006-04-06 23:12:19 +00:00
a4bbfaed5c
Match vpku[hw]um(x,x).
...
Convert vsldoi(x,x) to work the same way other (x,x) cases work.
llvm-svn: 27467
2006-04-06 22:28:36 +00:00
f38e033270
Add support for matching vmrg(x,x) patterns
...
llvm-svn: 27463
2006-04-06 22:02:42 +00:00
cee782d514
fix some linking problems with the new gcc
...
llvm-svn: 27460
2006-04-06 21:26:32 +00:00
d1dcb52093
Pattern match vmrg* instructions, which are now lowered by the CFE into shuffles.
...
llvm-svn: 27457
2006-04-06 21:11:54 +00:00
a4c727f1cc
remove two done items
...
llvm-svn: 27453
2006-04-06 19:19:38 +00:00
1d33819194
Support pattern matching vsldoi(x,y) and vsldoi(x,x), which allows the f.e. to
...
lower it and LLVM to have one fewer intrinsic. This implements
CodeGen/PowerPC/vec_shuffle.ll
llvm-svn: 27450
2006-04-06 18:26:28 +00:00
e8b83b4206
Compile the vpkuhum/vpkuwum intrinsics into vpkuhum/vpkuwum instead of into
...
vperm with a perm mask lvx'd from the constant pool.
llvm-svn: 27448
2006-04-06 17:23:16 +00:00
695e45c252
POR encoded as PAND, yikes.
...
llvm-svn: 27446
2006-04-06 01:49:20 +00:00
dddb688a40
An entry about comi / ucomi intrinsics.
...
llvm-svn: 27445
2006-04-05 23:46:04 +00:00
780382946e
Support for comi / ucomi intrinsics.
...
llvm-svn: 27444
2006-04-05 23:38:46 +00:00
c94d932447
Add all of the data stream intrinsics and instructions. woo
...
llvm-svn: 27442
2006-04-05 22:27:14 +00:00
39dc64c955
Fix a typo
...
llvm-svn: 27440
2006-04-05 20:15:25 +00:00
39cc717c65
Fix CodeGen/PowerPC/2006-04-05-splat-ish.ll
...
llvm-svn: 27439
2006-04-05 17:39:25 +00:00
f3b52c84ea
Handle canonical form of e.g.
...
vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>
This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.
It would match a {p}unpckl on x86.
llvm-svn: 27437
2006-04-05 07:20:06 +00:00
6d196db40d
Bogus assert
...
llvm-svn: 27434
2006-04-05 06:11:20 +00:00
2cf4232ced
Fallthrough to expand if a VECTOR_SHUFFLE cannot be custom lowered.
...
llvm-svn: 27433
2006-04-05 06:09:26 +00:00
59a6355e82
Handle v8i16 shuffle that must be broken into a pair of pshufhw / pshuflw.
...
llvm-svn: 27427
2006-04-05 01:47:37 +00:00
2f8e2b2895
add vsl
...
llvm-svn: 27425
2006-04-05 01:16:22 +00:00
575352ac20
add vmladduhm
...
llvm-svn: 27423
2006-04-05 00:49:48 +00:00
5a528e565b
Add m[tf]vscr instructions.
...
llvm-svn: 27421
2006-04-05 00:03:57 +00:00
0c82447c66
add a note
...
llvm-svn: 27419
2006-04-04 23:45:11 +00:00
281bb5da1d
Add missing byte merges.
...
llvm-svn: 27418
2006-04-04 23:43:56 +00:00
fc50ae521c
Add FP -> Int Conversions
...
llvm-svn: 27417
2006-04-04 23:25:02 +00:00
96338b6a21
add average intrinsics
...
llvm-svn: 27416
2006-04-04 23:14:00 +00:00
4464383a17
add a note
...
llvm-svn: 27414
2006-04-04 22:43:55 +00:00
4a744e5c9d
Fix some broken logic that would cause us to codegen {2147483647,2147483647,2147483647,2147483647} as 'vspltisb v0, -1'.
...
llvm-svn: 27413
2006-04-04 22:28:35 +00:00
011c23d9d3
Added pslldq and psrldq.
...
llvm-svn: 27412
2006-04-04 21:49:39 +00:00
8f3b6b8d8a
Minor fixes + naming changes.
...
llvm-svn: 27410
2006-04-04 19:12:30 +00:00
802b35c339
PSHUF* encoding bugs.
...
llvm-svn: 27405
2006-04-04 18:40:36 +00:00
95c7adc7cb
Ask legalize to promote all vector shuffles to be v16i8 instead of having to
...
handle all 4 PPC vector types. This simplifies the matching code and allows
us to eliminate a bunch of patterns. This also adds cases we were missing,
such as CodeGen/PowerPC/vec_splat.ll:splat_h.
llvm-svn: 27400
2006-04-04 17:25:31 +00:00
e91e3bd874
cmpps / cmppd encoding bug
...
llvm-svn: 27393
2006-04-04 03:04:07 +00:00
dd2eb27d6d
Compact some intrinsic definitions.
...
llvm-svn: 27388
2006-04-04 00:10:53 +00:00
b1e6d84544
Plug in the byte and short splats
...
llvm-svn: 27387
2006-04-04 00:05:13 +00:00
447a7968af
Revert accidentally committed hunks.
...
llvm-svn: 27386
2006-04-03 23:58:04 +00:00
533aed9a35
Make sure to mark unsupported SCALAR_TO_VECTOR operations as expand.
...
llvm-svn: 27385
2006-04-03 23:55:43 +00:00
0ef83c83e1
Some SSE1 intrinsics: min, max, sqrt, etc.
...
llvm-svn: 27384
2006-04-03 23:49:17 +00:00
bf0016f2d4
revert previous patch
...
llvm-svn: 27383
2006-04-03 23:14:49 +00:00
b64827e662
Use movlpd to: store lower f64 extracted from v2f64.
...
Use movhpd to: store upper f64 extracted from v2f64.
llvm-svn: 27382
2006-04-03 22:30:54 +00:00
5400727595
Force use of a frame-pointer if there is anything on the stack that is aligned
...
more than the OS keeps the stack aligned.
llvm-svn: 27381
2006-04-03 22:03:29 +00:00
ebf1006d16
- More efficient extract_vector_elt with shuffle and movss, movsd, movd, etc.
...
- Some bug fixes and naming inconsistency fixes.
llvm-svn: 27377
2006-04-03 20:53:28 +00:00
78c788b450
Align vectors to the size in bytes, not bits.
...
llvm-svn: 27376
2006-04-03 19:28:50 +00:00
9ccd61c893
Add the full set of min/max instructions
...
llvm-svn: 27372
2006-04-03 15:58:28 +00:00
df7abf8b74
support x * (c1 + c2) where c1 and c2 are pow2s. special case for c2 == 4
...
llvm-svn: 27370
2006-04-03 04:19:17 +00:00
4e2c073a33
mul by const conversion sequences. more coming soon
...
llvm-svn: 27368
2006-04-03 03:18:59 +00:00
444bdb069a
This makes McCat/12-IOtest go 8x faster or so
...
llvm-svn: 27363
2006-04-02 21:08:39 +00:00
01bd5523a3
This will be needed soon
...
llvm-svn: 27362
2006-04-02 20:13:57 +00:00
acf1fc8a28
add a note
...
llvm-svn: 27360
2006-04-02 07:20:00 +00:00
c5287c0ece
Inform the dag combiner that the predicate compares only return a low bit.
...
llvm-svn: 27359
2006-04-02 06:26:07 +00:00
6c1321ca3f
relax assertion
...
llvm-svn: 27358
2006-04-02 06:19:46 +00:00
e6025525fb
Allow targets to compute masked bits for intrinsics.
...
llvm-svn: 27357
2006-04-02 06:15:09 +00:00
80fdc1eb6b
Remove done item
...
llvm-svn: 27351
2006-04-02 05:28:54 +00:00
b80f114707
add a note
...
llvm-svn: 27348
2006-04-02 03:59:11 +00:00
7a29cf3c7f
New note
...
llvm-svn: 27337
2006-04-02 01:47:20 +00:00
9b2d6e7886
Custom lower all BUILD_VECTOR's so that we can compile vec_splat_u8(8) into
...
"vspltisb v0, 8" instead of a constant pool load.
llvm-svn: 27335
2006-04-02 00:43:36 +00:00
dc72c17798
Implement vnot using VNOR instead of using 'vspltisb v0, -1' and vxor
...
llvm-svn: 27331
2006-04-01 22:41:47 +00:00
0baebb11bf
ADd a note
...
llvm-svn: 27324
2006-04-01 04:08:29 +00:00
ff77dc0a08
Shrinkify some more intrinsic definitions.
...
llvm-svn: 27322
2006-03-31 22:41:56 +00:00
dc1161cf53
An entry about packed type alignments.
...
llvm-svn: 27321
2006-03-31 22:35:14 +00:00
20d3f3726f
Pull operand asm string into base class, shrinkifying intrinsic definitions.
...
No functionality change.
llvm-svn: 27320
2006-03-31 22:34:05 +00:00
a11d834b8c
TargetData.cpp::getTypeInfo() was returning alignment of element type as the
...
alignment of a packed type. This is obviously wrong. Added a workaround that
returns the size of the packed type as its alignment. The correct fix would
be to return a target dependent alignment value provided via TargetLowering
(or some other interface).
llvm-svn: 27319
2006-03-31 22:33:42 +00:00
110fc74b97
Fix 80 column violations :)
...
llvm-svn: 27315
2006-03-31 21:57:36 +00:00
5fd7c69473
Use a X86 target specific node X86ISD::PINSRW instead of a mal-formed
...
INSERT_VECTOR_ELT to insert a 16-bit value in a 128-bit vector.
llvm-svn: 27314
2006-03-31 21:55:24 +00:00
747e29ef0b
Added support for SSE3 horizontal ops: haddp{s|d} and hsub{s|d}.
...
llvm-svn: 27310
2006-03-31 21:29:33 +00:00
a4150f751d
fix a pasto
...
llvm-svn: 27308
2006-03-31 21:19:06 +00:00
e7fd4b0274
Add vperm support for all datatypes
...
llvm-svn: 27307
2006-03-31 20:00:35 +00:00
baa73e0d91
Rearrange code a bit
...
llvm-svn: 27306
2006-03-31 19:52:36 +00:00
754b41c84b
Add, sub and shuffle are legal for all vector types
...
llvm-svn: 27305
2006-03-31 19:48:58 +00:00
cbffa4656b
Add support to use pextrw and pinsrw to extract and insert a word element
...
from a 128-bit vector.
llvm-svn: 27304
2006-03-31 19:22:53 +00:00
3296f297d5
Add vector_extract and vector_insert nodes.
...
llvm-svn: 27303
2006-03-31 19:21:16 +00:00
40ff17dc22
add a note
...
llvm-svn: 27302
2006-03-31 19:00:22 +00:00
829a061abf
note to self: *save* file, then check it in
...
llvm-svn: 27291
2006-03-31 06:04:53 +00:00
d4058a59d4
Implement an item from the readme, folding vcmp/vcmp. instructions with
...
identical instructions into a single instruction. For example, for:
void test(vector float *x, vector float *y, int *P) {
int v = vec_any_out(*x, *y);
*x = (vector float)vec_cmpb(*x, *y);
*P = v;
}
we now generate:
_test:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r4
lvx v1, 0, r3
vcmpbfp. v0, v1, v0
mfcr r4, 2
stvx v0, 0, r3
rlwinm r3, r4, 27, 31, 31
xori r3, r3, 1
stw r3, 0(r5)
mtspr 256, r2
blr
instead of:
_test:
mfspr r2, 256
oris r6, r2, 57344
mtspr 256, r6
lvx v0, 0, r4
lvx v1, 0, r3
vcmpbfp. v2, v1, v0
mfcr r4, 2
*** vcmpbfp v0, v1, v0
rlwinm r4, r4, 27, 31, 31
stvx v0, 0, r3
xori r3, r4, 1
stw r3, 0(r5)
mtspr 256, r2
blr
Testcase here: CodeGen/PowerPC/vcmp-fold.ll
llvm-svn: 27290
2006-03-31 06:02:07 +00:00
070181c927
compactify some more instruction definitions
...
llvm-svn: 27288
2006-03-31 05:38:32 +00:00
45c709388a
Compactify comparisons.
...
llvm-svn: 27287
2006-03-31 05:32:57 +00:00
d7495ae7e9
Lower vector compares to VCMP nodes, just like we lower vector comparison
...
predicates to VCMPo nodes.
llvm-svn: 27285
2006-03-31 05:13:27 +00:00
e5a6c4f8b7
These are done
...
llvm-svn: 27284
2006-03-31 04:53:21 +00:00
051f7861b8
Was returning the wrong type.
...
llvm-svn: 27277
2006-03-31 01:50:09 +00:00
bca5fbe914
Mark INSERT_VECTOR_ELT as expand
...
llvm-svn: 27276
2006-03-31 01:48:55 +00:00
1b0d294de0
Expand all INSERT_VECTOR_ELT (obviously bad) for now.
...
llvm-svn: 27275
2006-03-31 01:30:39 +00:00
f144dac7b7
Modify the TargetLowering::getPackedTypeBreakdown method to also return the
...
unpromoted element type.
llvm-svn: 27273
2006-03-31 00:46:36 +00:00
d9d0bbb5ac
Typo
...
llvm-svn: 27272
2006-03-31 00:33:57 +00:00
99d7205fba
Ok for vector_shuffle mask to contain undef elements.
...
llvm-svn: 27271
2006-03-31 00:30:29 +00:00
549fb167eb
Implement TargetLowering::getPackedTypeBreakdown
...
llvm-svn: 27270
2006-03-31 00:28:56 +00:00
c4e3eadf21
Add the rest of the vmul instructions and the vmulsum* instructions.
...
llvm-svn: 27268
2006-03-30 23:39:06 +00:00
a23158f1ca
Use a new tblgen feature to significantly shrinkify instruction definitions that
...
directly correspond to intrinsics.
llvm-svn: 27266
2006-03-30 23:21:27 +00:00
551d3a11d3
Add a bunch of new instructions for intrinsics.
...
llvm-svn: 27265
2006-03-30 23:07:36 +00:00
7e2ff11a42
Make sure all possible shuffles are matched.
...
Use pshufd, pshuhw, and pshulw to shuffle v4f32 if shufps doesn't match.
Use shufps to shuffle v4f32 if pshufd, pshuhw, and pshulw don't match.
llvm-svn: 27259
2006-03-30 19:54:57 +00:00
dd487d865b
More logical ops patterns
...
llvm-svn: 27257
2006-03-30 07:33:32 +00:00
c58ef7deeb
Add support for _mm_cmp{cc}_ss and _mm_cmp{cc}_ps intrinsics
...
llvm-svn: 27256
2006-03-30 06:21:22 +00:00
593310016d
Add 128-bit pmovmskb intrinsic support.
...
llvm-svn: 27255
2006-03-30 00:33:26 +00:00
c5cf9bba05
Change SSE pack operation definitions to fit what the intrinsics expected.
...
For example, packsswb actually creates a v16i8 from a pair of v8i16. But since
the intrinsic specification forces the output type to match the operands.
llvm-svn: 27254
2006-03-29 23:53:14 +00:00
b7fedffc78
- Added some SSE2 128-bit packed integer ops.
...
- Added SSE2 128-bit integer pack with signed saturation ops.
- Added pshufhw and pshuflw ops.
llvm-svn: 27252
2006-03-29 23:07:14 +00:00
acc336475e
Need to special case splat after all. Make the second operand of splat
...
vector_shuffle undef.
llvm-svn: 27250
2006-03-29 19:02:40 +00:00
3cf95747c7
Floating point logical operation patterns should match bit_convert. Or else
...
integer vector logical operations would match andp{s|d} instead of pand.
llvm-svn: 27248
2006-03-29 18:47:40 +00:00
500ec16578
- More shuffle related bug fixes.
...
- Whenever possible use ops of the right packed types for vector shuffles /
splats.
llvm-svn: 27246
2006-03-29 03:04:49 +00:00
3a1c4e75de
Another entry about shuffles.
...
llvm-svn: 27245
2006-03-29 03:03:46 +00:00
da59b0d2a8
- Only use pshufd for v4i32 vector shuffles.
...
- Other shuffle related fixes.
llvm-svn: 27244
2006-03-29 01:30:51 +00:00
7d6f4f14b4
add a note
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llvm-svn: 27243
2006-03-29 00:24:13 +00:00
38b34296d0
Added aliases to scalar SSE instructions, e.g. addss, to match x86 intrinsics.
...
The source operands type are v4sf with upper bits passes through.
Added matching code for these.
llvm-svn: 27240
2006-03-28 23:51:43 +00:00
8160fd3d42
Fixing buggy code.
...
llvm-svn: 27239
2006-03-28 23:41:33 +00:00
66e1410858
add a note
...
llvm-svn: 27227
2006-03-28 18:56:23 +00:00
d1aa1638c6
Expose base register for DwarfWriter. Refactor code accordingly.
...
llvm-svn: 27225
2006-03-28 13:48:33 +00:00
457e54efc1
Added missing paren on behalf of Ramana Radhakrishnan.
...
llvm-svn: 27223
2006-03-28 10:17:11 +00:00
21e5476deb
Missed X86::isUNPCKHMask
...
llvm-svn: 27222
2006-03-28 08:27:15 +00:00
be2d9a0e99
movlps and movlpd should be modeled as two address code.
...
llvm-svn: 27221
2006-03-28 07:01:28 +00:00
dc57ae0711
Update
...
llvm-svn: 27220
2006-03-28 06:55:45 +00:00
4e7374ff8a
Typo
...
llvm-svn: 27219
2006-03-28 06:53:49 +00:00
1a194a5264
* Prefer using operation of matching types. e.g unpcklpd rather than movlhps.
...
* Bug fixes.
llvm-svn: 27218
2006-03-28 06:50:32 +00:00
af8c373e77
Fix a couple typos
...
llvm-svn: 27216
2006-03-28 04:18:18 +00:00
1b3928765d
Add a few more altivec intrinsics
...
llvm-svn: 27215
2006-03-28 04:15:58 +00:00
08b473c619
Added a couple of entries about movhps and movlhps.
...
llvm-svn: 27212
2006-03-28 02:49:12 +00:00
3765fadef6
All unpack cases are now being handled.
...
llvm-svn: 27211
2006-03-28 02:44:05 +00:00
2bc3280659
- Clean up / consoladate various shuffle masks.
...
- Some misc. bug fixes.
- Use MOVHPDrm to load from m64 to upper half of a XMM register.
llvm-svn: 27210
2006-03-28 02:43:26 +00:00
3710fca2b8
implement a bunch more intrinsics.
...
llvm-svn: 27209
2006-03-28 02:29:37 +00:00
cb5ec07cc3
Use normal lvx for scalar_to_vector instead of lve*x. They do the exact
...
same thing and we have a dag node for the former.
llvm-svn: 27205
2006-03-28 01:43:22 +00:00
e55d171ccd
Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value. Split them into separate enums.
...
llvm-svn: 27201
2006-03-28 00:40:33 +00:00
5df75889db
Model unpack lower and interleave as vector_shuffle so we can lower the
...
intrinsics as such.
llvm-svn: 27200
2006-03-28 00:39:58 +00:00
fa53b276d0
Translate llvm target registers to dwarf register numbers properly.
...
llvm-svn: 27180
2006-03-27 20:18:45 +00:00
018e17c8de
unbreak the build
...
llvm-svn: 27174
2006-03-27 16:52:45 +00:00
939c9ab88f
Add a bunch of notes from my journey thus far.
...
llvm-svn: 27170
2006-03-27 07:41:00 +00:00
22ec3e7b7e
Split out altivec notes into their own README
...
llvm-svn: 27168
2006-03-27 07:04:16 +00:00
9b9cc4fb39
Use pcmpeq to generate vector of all ones.
...
llvm-svn: 27167
2006-03-27 07:00:16 +00:00
a74792fa9d
Changed isBuildVectorAllOnesInteger to isBuildVectorAllOnes.
...
llvm-svn: 27166
2006-03-27 06:59:32 +00:00
1738c293b5
Fix the JIT encoding of VSEL
...
llvm-svn: 27160
2006-03-27 03:34:17 +00:00
df59d5314c
Fix the JIT encoding of VSPLTI*
...
llvm-svn: 27159
2006-03-27 03:28:57 +00:00
ed728c1291
SelectionDAGISel can now natively handle Switch instructions, in the same
...
manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks. The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.
This functionality is currently only enabled on x86, but should be safe for
every target. In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.
llvm-svn: 27156
2006-03-27 01:32:24 +00:00
65473e20d8
add vsel
...
llvm-svn: 27153
2006-03-26 22:38:43 +00:00
68cc9d4540
Readme note
...
llvm-svn: 27152
2006-03-26 19:19:27 +00:00
6961fc76bb
Codegen vector predicate compares.
...
llvm-svn: 27151
2006-03-26 10:06:40 +00:00
ed6184aef2
Remove X86:isZeroVector, use ISD::isBuildVectorAllZeros instead; some fixes / cleanups
...
llvm-svn: 27150
2006-03-26 09:53:12 +00:00
Andrew Lenharth