60d6f96da3
Change the peep for EXTRACT_VECTOR_ELT of BUILD_PAIR to look for
...
the new CONCAT_VECTORS node type instead, as that's what legalize
uses now. And add a peep for EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT.
llvm-svn: 38503
2007-07-10 18:20:44 +00:00
4bd45b3d53
Add a regression test for folding spill code into scalar min and max.
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llvm-svn: 38492
2007-07-10 15:34:29 +00:00
f8f531bf69
Change getCopyToParts and getCopyFromParts to always use target-endian
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register ordering, for both physical and virtual registers. Update the PPC
target lowering for calls to expect registers for the call result to
already be in target order.
llvm-svn: 38471
2007-07-09 20:59:04 +00:00
318ff8dd94
force a cpu without SSE
...
llvm-svn: 38466
2007-07-09 17:35:18 +00:00
0937478073
allow this to work on ppc-darwin
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llvm-svn: 38465
2007-07-09 17:32:28 +00:00
0e623de40d
remove this bogus t-t
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llvm-svn: 38464
2007-07-09 17:31:07 +00:00
6fec9a91b7
add target triple to fix PR1546
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llvm-svn: 38462
2007-07-09 17:14:58 +00:00
5740239998
Add explicit triples to these tests so that llc behaves as expected on
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non-Apple hosts.
llvm-svn: 38455
2007-07-09 13:42:32 +00:00
bab5355ff4
Add an explicit triple to the big-endian tests so that the assembly
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output format is always consistent with what the greps are looking for.
llvm-svn: 37943
2007-07-06 13:15:51 +00:00
6ddf75174a
Test that byte offsets are used to index into the list
...
of filter ids, and not simply the id index. Testing
this requires at least 128 type infos!
llvm-svn: 37941
2007-07-06 12:38:27 +00:00
da784693c3
Fix test.
...
llvm-svn: 37928
2007-07-05 23:00:50 +00:00
feba62c719
avoid ambiguity in target selection
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llvm-svn: 37927
2007-07-05 22:16:19 +00:00
d258e80583
Add a parameter to getCopyToParts and getCopyFromParts to specify whether
...
endian swapping should be done, and update the code to use it. This fixes
some register ordering issues on big-endian systems, such as PowerPC,
introduced by the recent illegal by-val arguments changes.
llvm-svn: 37921
2007-07-05 20:12:34 +00:00
3053244b27
Allow a GR64 to be moved into an MMX register via the "movd" instruction.
...
Still need to have JIT generate this code.
llvm-svn: 37863
2007-07-04 00:19:54 +00:00
a8bf39ee31
New testcases for rev 37847 (PR's 1489 and 1505).
...
llvm-svn: 37848
2007-07-03 00:58:37 +00:00
9ff9908413
Add a basic test-case for passing and returning <4 x double> and
...
<8 x float> values on X86.
llvm-svn: 37845
2007-07-02 16:23:47 +00:00
11a4008a59
New test case. DAGCombiner should be able to fold -sin(-x)
...
in -enable-unsafe-fp-math mode.
llvm-svn: 37841
2007-07-02 15:43:20 +00:00
d21e3ab873
New test.
...
llvm-svn: 37823
2007-06-29 23:17:15 +00:00
62acd01275
New test.
...
llvm-svn: 37815
2007-06-29 21:40:30 +00:00
2660cef6d7
Convert .cvsignore files
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llvm-svn: 37801
2007-06-29 16:35:07 +00:00
d880f90c2b
New test.
...
llvm-svn: 37791
2007-06-29 01:36:33 +00:00
b99f152f29
New tests.
...
llvm-svn: 37787
2007-06-29 00:27:18 +00:00
0de7694de6
Fix an assertion failure in legalizing bitcast operators on targets where
...
vectors are split down to single elements as part of legalization.
llvm-svn: 37785
2007-06-29 00:09:08 +00:00
e15ea75168
Fix tests.
...
llvm-svn: 37693
2007-06-21 18:22:42 +00:00
5fcb5a5c74
New tests.
...
llvm-svn: 37686
2007-06-21 07:40:00 +00:00
85010166a6
Added some if-conversion tests.
...
llvm-svn: 37672
2007-06-20 18:26:15 +00:00
6ba3e8b27d
New test case: identity operation of RHS / LHS of a VECTOR_SHUFFLE.
...
llvm-svn: 37637
2007-06-19 00:06:08 +00:00
5f232faf8c
ensure we don't regress on these tests. We generate aweful code in x86-32 for
...
these though.
llvm-svn: 37619
2007-06-17 23:29:57 +00:00
ec6be07c22
XFAILing until I can fix properly.
...
llvm-svn: 37618
2007-06-16 23:57:51 +00:00
c8f293b4f9
Testcase for MMX int to MMX register failure.
...
llvm-svn: 37612
2007-06-16 06:31:47 +00:00
2d7f447a7a
make this test harder, include a tied register.
...
llvm-svn: 37600
2007-06-15 19:09:53 +00:00
92bf2c628c
Workaround for PR1508.
...
llvm-svn: 37597
2007-06-15 19:04:19 +00:00
616627b002
Do not treat FP_REG_KILL as terminator in branch analysis (X86).
...
llvm-svn: 37578
2007-06-14 22:03:45 +00:00
fe940d8d74
"Simplified" testcase for PR1422.
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llvm-svn: 37462
2007-06-06 09:59:53 +00:00
af56be7f2c
new testcase for PR1495
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llvm-svn: 37452
2007-06-06 01:21:46 +00:00
59754300a8
New test.
...
llvm-svn: 37431
2007-06-05 01:45:08 +00:00
0558dda319
Tail merging wasn't working for predecessors of landing pads. PR 1496.
...
llvm-svn: 37427
2007-06-04 23:52:54 +00:00
3c0a13762d
Implement smarter algorithm for choosing which blocks to tail-merge.
...
See test/CodeGen/X86/test-pic-jtbl.ll for a case where it works well;
shaves another 10K off our favorite benchmark. I was hesitant about
this because of compile speed, but seems to do OK on a bootstrap.
llvm-svn: 37392
2007-06-01 23:02:45 +00:00
5a3e6fe365
Add a test for PR1424.
...
llvm-svn: 37372
2007-05-31 18:36:07 +00:00
4217aa376a
new testcase for PR1473
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llvm-svn: 37361
2007-05-30 16:29:20 +00:00
b58bf97603
Add a new test case.
...
llvm-svn: 37317
2007-05-24 02:31:15 +00:00
d750b46f8b
tail merging shrinks this code a bit. Could do more in future.
...
llvm-svn: 37316
2007-05-23 21:09:26 +00:00
a7120dde08
new testcases for -enable-tail-merge default handling
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llvm-svn: 37287
2007-05-22 17:19:23 +00:00
80fae16a06
Test assumes tail merging is off; this must now be explicit.
...
llvm-svn: 37286
2007-05-22 17:18:05 +00:00
204af78b96
Add test for PR1259.
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llvm-svn: 37273
2007-05-21 23:30:33 +00:00
0306944992
add source
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llvm-svn: 37253
2007-05-19 01:22:52 +00:00
afa90dc355
new testcase
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llvm-svn: 37251
2007-05-19 01:21:39 +00:00
bde968823a
new testcase
...
llvm-svn: 37245
2007-05-19 00:41:40 +00:00
0465aca5d2
New test case.
...
llvm-svn: 37174
2007-05-17 18:49:50 +00:00
7bee9ad4f7
add testcase for 128-bit add/sub
...
llvm-svn: 37170
2007-05-17 18:22:37 +00:00
Dan Gohman