c0434466e4
[Hexagon] Adding encoding information for absolute-reg mode stores. Xfailing a test until constant extenders are correctly put in the same packet.
...
llvm-svn: 228158
2015-02-04 17:52:06 +00:00
7d971056ed
[Hexagon] Adding encoding information for absolute-set stores.
...
llvm-svn: 228154
2015-02-04 17:24:04 +00:00
0eb9727d42
[Hexagon] Adding encoding bits for indirect long load instructions.
...
llvm-svn: 228152
2015-02-04 16:56:46 +00:00
585316cb41
[Hexagon] Revert change to isCodeGenOnly = 1 in r228080
...
llvm-svn: 228082
2015-02-04 00:09:23 +00:00
510ba0c661
[Hexagon] Changing some isCodeGenOnly to isAsmParserOnly since we want them to asm parse but not cause decode conflicts.
...
llvm-svn: 228080
2015-02-04 00:07:26 +00:00
e4101e2c9e
[Hexagon] Marking a bunch of non-encoded instructions with isCodeGenOnly = 1.
...
llvm-svn: 228050
2015-02-03 22:09:51 +00:00
cd9cb023d7
[Hexagon] Converting XTYPE/SHIFT intrinsics. Cleaning out old intrinsic patterns and updating tests.
...
llvm-svn: 228026
2015-02-03 20:40:52 +00:00
cf7248bcaf
[Hexagon] Updating XTYPE/PRED intrinsics.
...
llvm-svn: 228019
2015-02-03 19:43:59 +00:00
e5daf3abfe
[Hexagon] Updating XTYPE/PERM intrinsics.
...
llvm-svn: 228015
2015-02-03 19:36:59 +00:00
99cc7c1070
[Hexagon] Adding missing vector multiply instruction encodings. Converting multiply intrinsics and updating tests.
...
llvm-svn: 228010
2015-02-03 19:15:11 +00:00
a6632452be
[Hexagon] Converting complex number intrinsics and adding tests.
...
llvm-svn: 227995
2015-02-03 18:16:28 +00:00
cdba4e1bcc
[Hexagon] Adding vector intrinsics for alu32/alu and xtype/alu.
...
llvm-svn: 227993
2015-02-03 18:01:45 +00:00
36fe028a2a
Only access TLOF via the TargetMachine, not TargetLowering.
...
llvm-svn: 227949
2015-02-03 07:22:52 +00:00
8f276db622
Define a runOnMachineFunction for the Hexagon AsmPrinter and
...
use it to initialize the subtarget.
llvm-svn: 227948
2015-02-03 06:40:22 +00:00
d5c235dab8
Use the cached subtarget on the MachineFunction.
...
llvm-svn: 227885
2015-02-02 22:40:56 +00:00
6905059e80
Remove dead header.
...
llvm-svn: 227884
2015-02-02 22:40:54 +00:00
57931fca07
Remove dead code in the HexagonMCInst classes. This also fixes
...
a layering violation in the port and removes calls to getSubtargetImpl.
llvm-svn: 227883
2015-02-02 22:40:53 +00:00
d21486dfe0
80-col fixup.
...
llvm-svn: 227882
2015-02-02 22:40:51 +00:00
2b7707c07e
Remove dead code in the HexagonMCInst classes. This also fixes
...
a layering violation in the port and removes calls to getSubtargetImpl.
llvm-svn: 227880
2015-02-02 22:28:48 +00:00
97a2a39695
80-col fixup.
...
llvm-svn: 227879
2015-02-02 22:28:46 +00:00
6098f150a1
Remove unused class variables and update all callers/uses from
...
the HexagonSplitTFRCondSet pass. Use the subtarget off the machine
function at the same time.
llvm-svn: 227878
2015-02-02 22:28:44 +00:00
01f875e859
Migrate the HexagonSplitConst32AndConst64 pass from TargetMachine
...
based getSubtarget to the one cached on the MachineFunction.
Remove unused class variables and update all callers/uses.
llvm-svn: 227874
2015-02-02 22:11:43 +00:00
0fef34e3fc
Remove #if'd code and update comment.
...
llvm-svn: 227873
2015-02-02 22:11:42 +00:00
f8b8e4a3fb
Move HexagonMachineScheduler to use the subtarget off of the
...
MachineFunction and update all uses accordingly including
VLIWResourceModel.
llvm-svn: 227872
2015-02-02 22:11:40 +00:00
d737b76b63
Cache and use the subtarget that owns the target lowering.
...
llvm-svn: 227871
2015-02-02 22:11:36 +00:00
202f22bbda
Migrate HexagonISelDAGToDAG to setting a subtarget pointer during
...
runOnMachineFunction. Update all uses of the Subtarget accordingly.
llvm-svn: 227840
2015-02-02 19:22:03 +00:00
90295c9c63
Use the getSubtarget call off of the MachineFunction rather than
...
the TargetMachine.
llvm-svn: 227839
2015-02-02 19:22:01 +00:00
2c44f43ebe
Remove unused class variables and update calls to get the subtarget
...
off of the machine function.
llvm-svn: 227837
2015-02-02 19:05:28 +00:00
d55c7c6670
Sink queries into asserts since the variable is unused otherwise.
...
llvm-svn: 227836
2015-02-02 18:58:24 +00:00
241a9e8db2
Update CMake build for removed files.
...
llvm-svn: 227834
2015-02-02 18:52:49 +00:00
6ff7ed6446
Get TargetRegisterInfo and TargetInstrInfo off of the MachineFunction
...
and remove unnecessary class variables.
llvm-svn: 227832
2015-02-02 18:46:31 +00:00
12a5c0db57
Use the function template getSubtarget to remove an explicit cast.
...
llvm-svn: 227831
2015-02-02 18:46:29 +00:00
5c3376aa62
Grab TargetInstrInfo off of the MachineFunction and remove
...
unnecessary class variables.
llvm-svn: 227830
2015-02-02 18:46:27 +00:00
da67cc97a7
Remove unused files.
...
llvm-svn: 227829
2015-02-02 18:46:23 +00:00
cefca69d72
[Hexagon] Adding vector shift instructions and tests.
...
llvm-svn: 227619
2015-01-30 21:58:46 +00:00
cc4329b836
[Hexagon] Adding vector predicate instructions.
...
llvm-svn: 227613
2015-01-30 21:24:06 +00:00
26a537c743
[Hexagon] Adding vector permutation instructions and tests.
...
llvm-svn: 227612
2015-01-30 21:14:00 +00:00
16f5e56703
[Hexagon] Adding vector multiplies. Cleaning up tests.
...
llvm-svn: 227609
2015-01-30 20:56:54 +00:00
b84ec02296
[Hexagon] Adding XTYPE/COMPLEX instructions and cleaning up tests.
...
llvm-svn: 227607
2015-01-30 20:08:37 +00:00
21fbc94777
[Hexagon] Adding XTYPE/ALU vector instructions. Organizing test files.
...
llvm-svn: 227598
2015-01-30 19:13:26 +00:00
709c0a16bb
[Hexagon] Adding a number of vector load variants and organizing tests.
...
llvm-svn: 227588
2015-01-30 18:09:44 +00:00
3c740a3614
[Hexagon] Organizing tests and adding a few missing jump instruction encodings.
...
llvm-svn: 227498
2015-01-29 21:47:15 +00:00
bc63f42e0d
[Hexagon] Adding missing instruction encodings and tests.
...
llvm-svn: 227495
2015-01-29 21:30:22 +00:00
bd4770f915
[Hexagon] Adding alu vector instructions
...
llvm-svn: 227493
2015-01-29 21:09:30 +00:00
ba31e27f0a
Compute the ELF SectionKind from the flags.
...
Any code creating an MCSectionELF knows ELF and already provides the flags.
SectionKind is an abstraction used by common code that uses a plain
MCSection.
Use the flags to compute the SectionKind. This removes a lot of
guessing and boilerplate from the MCSectionELF construction.
llvm-svn: 227476
2015-01-29 17:33:21 +00:00
1610730faf
[Hexagon] Deleting old variants of intrinsics and adding missing tests.
...
llvm-svn: 227474
2015-01-29 17:26:56 +00:00
860210bc49
[Hexagon] Adding CR intrinsic tests.
...
llvm-svn: 227463
2015-01-29 16:55:37 +00:00
e75aa4983c
[Hexagon] Deleting unused classes.
...
llvm-svn: 227460
2015-01-29 16:35:38 +00:00
a749b3ee6a
[Hexagon] Adding XTYPE/PRED intrinsic tests. Converting predicate types to i32 instead of i1.
...
llvm-svn: 227457
2015-01-29 16:08:43 +00:00
4379d10273
[Hexagon] Updating several V5 intrinsics and adding FP tests.
...
llvm-svn: 227379
2015-01-28 22:08:16 +00:00
1de7e0d923
[Hexagon] Updating many V4 intrinsic patterns. Adding missing instruction and deleting unused classes.
...
llvm-svn: 227353
2015-01-28 19:39:09 +00:00
94c33218e3
[Hexagon] Adding XTYPE/MPY intrinsic tests and some missing multiply instructions.
...
llvm-svn: 227347
2015-01-28 19:16:17 +00:00
19ed07c75a
[Hexagon] Deleting a lot of old variants of intrinsics and updating references.
...
llvm-svn: 227338
2015-01-28 18:29:11 +00:00
39b846ce0f
[Hexagon] Converting XTYPE/BIT intrinsic patterns and adding tests.
...
llvm-svn: 227335
2015-01-28 18:06:23 +00:00
fe03c9a678
[Hexagon] Replacing XTYPE/SHIFT intrinsic patternss. Adding tests and missing instructions with tests.
...
llvm-svn: 227330
2015-01-28 17:37:59 +00:00
fdbc5adbb6
[Hexagon] Replacing intrinsics for halfword adds and max/min word/dword.
...
llvm-svn: 227322
2015-01-28 17:06:40 +00:00
b81dfa6378
[LPM] Stop using the string based preservation API. It is an
...
abomination.
For starters, this API is incredibly slow. In order to lookup the name
of a pass it must take a memory fence to acquire a pointer to the
managed static pass registry, and then potentially acquire locks while
it consults this registry for information about what passes exist by
that name. This stops the world of LLVMs in your process no matter
how little they cared about the result.
To make this more joyful, you'll note that we are preserving many passes
which *do not exist* any more, or are not even analyses which one might
wish to have be preserved. This means we do all the work only to say
"nope" with no error to the user.
String-based APIs are a *bad idea*. String-based APIs that cannot
produce any meaningful error are an even worse idea. =/
I have a patch that simply removes this API completely, but I'm hesitant
to commit it as I don't really want to perniciously break out-of-tree
users of the old pass manager. I'd rather they just have to migrate to
the new one at some point. If others disagree and would like me to kill
it with fire, just say the word. =]
llvm-svn: 227294
2015-01-28 04:57:56 +00:00
8b7706517c
Move DataLayout back to the TargetMachine from TargetSubtargetInfo
...
derived classes.
Since global data alignment, layout, and mangling is often based on the
DataLayout, move it to the TargetMachine. This ensures that global
data is going to be layed out and mangled consistently if the subtarget
changes on a per function basis. Prior to this all targets(*) have
had subtarget dependent code moved out and onto the TargetMachine.
*One target hasn't been migrated as part of this change: R600. The
R600 port has, as a subtarget feature, the size of pointers and
this affects global data layout. I've currently hacked in a FIXME
to enable progress, but the port needs to be updated to either pass
the 64-bitness to the TargetMachine, or fix the DataLayout to
avoid subtarget dependent features.
llvm-svn: 227113
2015-01-26 19:03:15 +00:00
94269db8ba
[Hexagon] Converting multiply and accumulate with immediate intrinsics to patterns.
...
llvm-svn: 226681
2015-01-21 18:13:15 +00:00
988c68f2a7
[Hexagon] Adding intrinsics for doubleword ALU operations.
...
llvm-svn: 226606
2015-01-20 20:45:05 +00:00
0ee02fc9fe
[Hexagon] Updating muxir/ri/ii intrinsics. Setting predicate registers as compatible with i32 rather than doing custom type conversion.
...
llvm-svn: 226500
2015-01-19 20:31:18 +00:00
fcd4569af6
[Hexagon] Converting intrinsics combine imm/imm, simple shifts and extends.
...
llvm-svn: 226483
2015-01-19 18:56:19 +00:00
9327bdad2f
[Hexagon] Converting remaining ALU32/ALU intrinsics.
...
llvm-svn: 226480
2015-01-19 18:33:58 +00:00
663419b008
[Hexagon] Converting ALU32/ALU intrinsics to new patterns.
...
llvm-svn: 226478
2015-01-19 18:22:19 +00:00
310bad8b7e
[Hexagon] Converting halfword to double accumulating multiply intrinsics.
...
llvm-svn: 226472
2015-01-19 17:36:32 +00:00
9459832ebd
std::unique_ptrify the MCStreamer argument to createAsmPrinter
...
llvm-svn: 226414
2015-01-18 20:29:04 +00:00
823415b881
[Hexagon] Converting halfword to doubleword multiply intrinsics.
...
llvm-svn: 226326
2015-01-16 21:41:57 +00:00
cd9b276966
[Hexagon] Converting accumulating halfword multiply intrinsics to patterns.
...
llvm-svn: 226324
2015-01-16 21:36:34 +00:00
3b047e0ee5
[Hexagon] Beginning converting intrinsics to patterns instead of duplicated definitions. Converting halfword multiply intrinsics.
...
llvm-svn: 226318
2015-01-16 20:38:54 +00:00
54adb6a5d5
[Hexagon] Fix 226309, replacement atomic store patterns didn't actually exist, added new versions.
...
llvm-svn: 226315
2015-01-16 20:16:14 +00:00
bb6718b30e
[Hexagon] Removing old duplicate atomic load/store patterns.
...
llvm-svn: 226309
2015-01-16 19:53:35 +00:00
7d1f632380
[Hexagon] Converting old patterns to new versions using classes.
...
llvm-svn: 226304
2015-01-16 19:29:59 +00:00
2e3a26de0c
[Hexagon] Updating call/jump instruction patterns.
...
llvm-svn: 226288
2015-01-16 17:05:27 +00:00
cd9c4e3e07
[Hexagon] Adding new-value store and bit reverse instructions.
...
llvm-svn: 226224
2015-01-15 23:10:29 +00:00
c59328e627
[Hexagon] Fix 226206 by uncommenting required pattern and changing patterns for simple load-extends.
...
llvm-svn: 226210
2015-01-15 21:35:49 +00:00
f87697f05e
[Hexagon] Updating indexed load-extend patterns and changing test to new expected output.
...
llvm-svn: 226206
2015-01-15 21:07:52 +00:00
538b85810c
[Hexagon] Removing old versions of vsplice, valign, cl0, ct0 and updating references to new versions.
...
llvm-svn: 226194
2015-01-15 19:28:32 +00:00
504157f1ae
[Hexagon] Adding vmux instruction. Removing old transfer instructions and updating references.
...
llvm-svn: 226184
2015-01-15 18:16:00 +00:00
2d1c14563e
[Hexagon] Deleting old float comparison instruction and updating references to new ones.
...
llvm-svn: 226179
2015-01-15 17:28:14 +00:00
7959cac725
[Hexagon] Replacing old fadd/fsub instructions and updating references.
...
llvm-svn: 226176
2015-01-15 16:30:07 +00:00
8ffce23cda
[Hexagon] Replacing old versions of stores and loads.
...
llvm-svn: 226065
2015-01-15 00:15:30 +00:00
c7522f31f1
[Hexagon] Replacing old version of convert and load f64.
...
llvm-svn: 226057
2015-01-14 23:07:36 +00:00
11a34b385d
[Hexagon] Removing old, unused !tstbit instructions.
...
llvm-svn: 226036
2015-01-14 20:26:15 +00:00
c91fabc233
[Hexagon] Removing old versions of cmph and updating references.
...
llvm-svn: 226013
2015-01-14 18:26:14 +00:00
ffacc6eac6
[Hexagon] Removing old versions of cmpb and updating references.
...
llvm-svn: 226006
2015-01-14 18:05:44 +00:00
fa947906bf
[Hexagon] Deleting versions of compare-not that don't have encoding information. Updating references.
...
llvm-svn: 226003
2015-01-14 16:49:12 +00:00
d9903888d9
[cleanup] Re-sort all the #include lines in LLVM using
...
utils/sort_includes.py.
I clearly haven't done this in a while, so more changed than usual. This
even uncovered a missing include from the InstrProf library that I've
added. No functionality changed here, just mechanical cleanup of the
include order.
llvm-svn: 225974
2015-01-14 11:23:27 +00:00
2b6917b020
[SelectionDAG] Allow targets to specify legality of extloads' result
...
type (in addition to the memory type).
The *LoadExt* legalization handling used to only have one type, the
memory type. This forced users to assume that as long as the extload
for the memory type was declared legal, and the result type was legal,
the whole extload was legal.
However, this isn't always the case. For instance, on X86, with AVX,
this is legal:
v4i32 load, zext from v4i8
but this isn't:
v4i64 load, zext from v4i8
Whereas v4i64 is (arguably) legal, even without AVX2.
Note that the same thing was done a while ago for truncstores (r46140),
but I assume no one needed it yet for extloads, so here we go.
Calls to getLoadExtAction were changed to add the value type, found
manually in the surrounding code.
Calls to setLoadExtAction were mechanically changed, by wrapping the
call in a loop, to match previous behavior. The loop iterates over
the MVT subrange corresponding to the memory type (FP vectors, etc...).
I also pulled neighboring setTruncStoreActions into some of the loops;
those shouldn't make a difference, as the additional types are illegal.
(e.g., i128->i1 truncstores on PPC.)
No functional change intended.
Differential Revision: http://reviews.llvm.org/D6532
llvm-svn: 225421
2015-01-08 00:51:32 +00:00
92b49c3e39
[Hexagon] Fix 225372 USR register is not fully complete. Removing Uses = [USR] maintains existing functionality to old instructions without encodings.
...
llvm-svn: 225377
2015-01-07 20:43:38 +00:00
627df427eb
[Hexagon] Adding floating point classification and creation.
...
llvm-svn: 225374
2015-01-07 20:28:57 +00:00
290ece7d4c
[Hexagon] Adding encodings for v5 floating point instructions.
...
llvm-svn: 225372
2015-01-07 20:24:09 +00:00
777abcb1d7
[Hexagon] Adding encoding for popcount, fastcorner, dword asr with rounding.
...
llvm-svn: 225371
2015-01-07 20:07:28 +00:00
507dd32703
[Hexagon] Adding compound jump encodings.
...
llvm-svn: 225291
2015-01-06 20:03:31 +00:00
68b2e050f0
[Hexagon] Adding encoding for misc v4 instructions: boundscheck, tlbmatch, dcfetch.
...
llvm-svn: 225283
2015-01-06 19:03:20 +00:00
d9c605ddae
[Hexagon] Adding encoding information for absolute address loads.
...
llvm-svn: 225279
2015-01-06 18:38:26 +00:00
243a5481d9
[Hexagon] Fix 225267. GP register is not yet fully implemented. Removing Uses [GP] maintains existing behavior.
...
llvm-svn: 225270
2015-01-06 16:52:38 +00:00
1445553474
[Hexagon] Adding dealloc_return encoding and absolute address stores.
...
llvm-svn: 225267
2015-01-06 16:15:15 +00:00
dacf057bdc
[Hexagon] Adding add/sub with carry, logical shift left by immediate and memop instructions. Removing old defs without bits and updating references.
...
llvm-svn: 225210
2015-01-05 21:36:38 +00:00
28bb02a8c7
[Hexagon] Adding rounding reg/reg variants, accumulating multiplies, and accumulating shifts.
...
llvm-svn: 225201
2015-01-05 20:56:41 +00:00
abdf2b37d8
[Hexagon] Adding V4 bit manipulating instructions, removing ALU defs without encoding bits.
...
llvm-svn: 225199
2015-01-05 20:35:54 +00:00
3acfddd6b5
[Hexagon] Adding V4 logic-logic instructions and tests.
...
llvm-svn: 225198
2015-01-05 20:14:58 +00:00
ff10c8c95c
[Hexagon] Adding orand, bitsplit reg/reg, and modwrap instructions.
...
llvm-svn: 225197
2015-01-05 20:04:40 +00:00
5e079577e1
[Hexagon] Adding round reg/imm and bitsplit instructions.
...
llvm-svn: 225188
2015-01-05 18:08:21 +00:00
d3c02f177a
Replace several 'assert(false' with 'llvm_unreachable' or fold a condition into the assert.
...
llvm-svn: 225160
2015-01-05 10:15:49 +00:00
5691eb5ee7
Reverting 225045 and 225043 and XFAIL multiline.ll on hexagon
...
llvm-svn: 225047
2014-12-31 17:14:35 +00:00
79e8ebada2
[Hexagon] Removing assertion to appease buildbot until I can reproduce the problem
...
llvm-svn: 225045
2014-12-31 16:20:00 +00:00
94272611ac
[Hexagon] Changing an llvm_unreachable to an assertion and returning 0. Relocations aren't implemented yet but we don't need to abort for this in release builds.
...
llvm-svn: 225043
2014-12-31 15:57:38 +00:00
bc405294f0
[Hexagon] Adding accumulating add/sub, doubleword logic-not variants, doubleword bitfield extract, word parity, accumulating multiplies with saturation.
...
llvm-svn: 225024
2014-12-31 00:08:34 +00:00
8971e055ae
[Hexagon] Adding double-logic on predicate instructions.
...
llvm-svn: 225018
2014-12-30 23:22:39 +00:00
65f3e12ed1
[Hexagon] Adding newvalue compare and jumps.
...
llvm-svn: 225015
2014-12-30 23:04:21 +00:00
0cba5f1b43
[Hexagon] Adding postincrement register newvalue stores.
...
llvm-svn: 225010
2014-12-30 22:34:08 +00:00
9014890819
[Hexagon] Removing old newvalue store variants. Adding postincrement immediate newvalue stores.
...
llvm-svn: 225009
2014-12-30 22:28:31 +00:00
820d5cb608
[Hexagon] Adding indexed store new-value variants.
...
llvm-svn: 225007
2014-12-30 22:00:26 +00:00
2bad4a7177
[Hexagon] Adding indexed store of immediates.
...
llvm-svn: 225006
2014-12-30 21:01:38 +00:00
94a498bf0e
[Hexagon] Adding indexed stores.
...
llvm-svn: 225005
2014-12-30 20:42:23 +00:00
9161d47476
[Hexagon] Adding reg-reg indexed load forms.
...
llvm-svn: 224997
2014-12-30 18:58:47 +00:00
82fb8cba16
[Hexagon] Dropping old combine instructions without encodings.
...
llvm-svn: 224992
2014-12-30 17:53:54 +00:00
377ac65340
[Hexagon] Adding compare byte/halfword reg-reg/reg-imm forms. Adding compare to general register reg-imm form.
...
llvm-svn: 224991
2014-12-30 17:39:24 +00:00
d7a56fd9ff
[Hexagon] Updating constant extender def, adding alu-not instructions, compare to general register, and inverted compares.
...
llvm-svn: 224989
2014-12-30 15:44:17 +00:00
651b72095b
[Hexagon] Adding allocframe, post-increment circular immediate stores, post-increment circular register stores, and bit reversed post-increment stores.
...
llvm-svn: 224957
2014-12-29 21:33:45 +00:00
488b6f7bbc
[Hexagon] Fixing 224952 where an addressing mode update was missed.
...
llvm-svn: 224955
2014-12-29 21:18:02 +00:00
bda31b42a0
[Hexagon] Adding post-increment register form stores and register-immediate form stores with tests.
...
llvm-svn: 224952
2014-12-29 20:44:51 +00:00
9a3cd3f58c
[Hexagon] Replacing the remaining postincrement stores with versions that have encoding bits.
...
llvm-svn: 224951
2014-12-29 20:00:43 +00:00
3d34afb32d
[Hexagon] Renaming old multiclass for removal. Adding post-increment store classes and instruction defs.
...
llvm-svn: 224949
2014-12-29 19:42:14 +00:00
8233fb002d
[Hexagon] Adding auto-incrementing loads with and without byte reversal.
...
llvm-svn: 224871
2014-12-26 21:09:25 +00:00
0a721cd4e1
[Hexagon] Adding locked loads.
...
llvm-svn: 224870
2014-12-26 20:42:27 +00:00
ff370ed90e
[Hexagon] Adding deallocframe and circular addressing loads.
...
llvm-svn: 224869
2014-12-26 20:30:58 +00:00
c83cbbf6a1
[Hexagon] Adding remaining post-increment instruction variants. Removing unused classes.
...
llvm-svn: 224868
2014-12-26 19:31:46 +00:00
fe9612e09d
[Hexagon] Adding post-increment unsigned byte loads.
...
llvm-svn: 224867
2014-12-26 19:12:11 +00:00
96976a10a3
[Hexagon] Adding post-increment signed byte loads with tests.
...
llvm-svn: 224866
2014-12-26 18:57:13 +00:00
e193e1c48b
[Hexagon] Removing old classes.
...
llvm-svn: 224795
2014-12-24 00:43:00 +00:00
947cd70413
[Hexagon] Adding doubleword load.
...
llvm-svn: 224787
2014-12-23 20:44:59 +00:00
026e88d317
[Hexagon] Reapplying 224775 load words.
...
llvm-svn: 224786
2014-12-23 20:02:16 +00:00
20be15718b
Reverting 224775 until mayLoad flag is addressed.
...
llvm-svn: 224783
2014-12-23 19:22:59 +00:00
122aeaafea
[Hexagon] Adding word loads.
...
llvm-svn: 224775
2014-12-23 18:06:56 +00:00
8e39cad934
[Hexagon] Adding signed halfword loads.
...
llvm-svn: 224774
2014-12-23 17:25:57 +00:00
a9386d28a5
[Hexagon] Adding unsigned halfword load.
...
llvm-svn: 224772
2014-12-23 16:42:57 +00:00
4b1eac4dda
[Hexagon] Adding memb instruction. Fixing whitespace in test from 224730.
...
llvm-svn: 224735
2014-12-22 21:40:43 +00:00
af1e5de141
[Hexagon] Adding classes and load unsigned byte instruction, updating usages.
...
llvm-svn: 224730
2014-12-22 21:20:03 +00:00
0f850bde0e
[Hexagon] Removing old variants of instructions and updating references.
...
llvm-svn: 224612
2014-12-19 20:29:29 +00:00
38ce8cd2e2
[Hexagon] Adding bit extraction and table indexing instructions.
...
llvm-svn: 224610
2014-12-19 20:01:08 +00:00
3c7f664d5a
[Hexagon] Adding bit insertion instructions.
...
llvm-svn: 224609
2014-12-19 19:54:38 +00:00
d63ef93b4b
[Hexagon] Adding more xtype shift instructions.
...
llvm-svn: 224608
2014-12-19 19:51:35 +00:00
cc09d1ccc5
[Hexagon] Adding xtype shift instructions.
...
llvm-svn: 224604
2014-12-19 19:34:50 +00:00
f3db884efb
[Hexagon] Adding transfers to and from control registers.
...
llvm-svn: 224599
2014-12-19 19:06:32 +00:00
402f772b82
[Hexagon] Adding doubleregs for control registers. Renaming control register class.
...
llvm-svn: 224598
2014-12-19 18:56:10 +00:00
5ccbb1298b
[Hexagon] Adding loop0/1 sp0/1/2loop0 instructions.
...
llvm-svn: 224556
2014-12-19 00:06:53 +00:00
174476ed96
Reverting 224550, was not ready for commit.
...
llvm-svn: 224552
2014-12-18 23:36:15 +00:00
9000481cda
[Hexagon] Adding loop0/1 sp0/1/2loop0 instructions.
...
llvm-svn: 224550
2014-12-18 23:27:51 +00:00
2055538edb
[Hexagon] Reconfiguring register alternate names.
...
llvm-svn: 224455
2014-12-17 20:35:11 +00:00
aa1bade7b4
[Hexagon] Updating doubleword shift usages to new versions.
...
llvm-svn: 224391
2014-12-16 23:36:15 +00:00
7fc90fc7e9
[Hexagon] Removing old XTYPE/BIT instructions and replacing usages.
...
llvm-svn: 224381
2014-12-16 22:17:09 +00:00
f5acc8c625
[Hexagon] Adding tstbit/bitclr/bitset instructions.
...
llvm-svn: 224374
2014-12-16 21:28:58 +00:00
615757f2f1
[Hexagon] Adding bit count and twiddling instructions.
...
llvm-svn: 224367
2014-12-16 20:57:56 +00:00
6fce46baf6
[Hexagon] Adding asr/lsr/asl reg/imm, asl with saturation, asr with rounding. Doubleword abs/neg/not. Interleave and deinterleave instructions.
...
llvm-svn: 224365
2014-12-16 20:40:23 +00:00
1944a8cd04
[Hexagon] Adding absolute value, and negate with saturation
...
llvm-svn: 224346
2014-12-16 17:44:49 +00:00
455f24aa77
[Hexagon] Adding saturate and swizzle instructions.
...
llvm-svn: 224343
2014-12-16 16:27:17 +00:00
d9b23509bf
[Hexagon] Removing old multiply defs and updating references to new versions.
...
llvm-svn: 224340
2014-12-16 16:10:01 +00:00
d9a00a9c38
[Hexagon] Adding doubleword multiplies with and without accumulation.
...
llvm-svn: 224293
2014-12-16 00:07:24 +00:00
18c927620a
[Hexagon] Adding halfword to doubleword multiplies.
...
llvm-svn: 224289
2014-12-15 23:29:37 +00:00
64ffd52943
[Hexagon] Adding logical-logical accumulation instructions and tests.
...
llvm-svn: 224288
2014-12-15 23:19:07 +00:00
71e11a1d0d
[Hexagon] Adding a number of additional multiply forms with tests.
...
llvm-svn: 224282
2014-12-15 22:10:37 +00:00
4a46429305
[Hexagon] Adding misc multiply encodings and tests.
...
llvm-svn: 224273
2014-12-15 21:17:03 +00:00
26f884aedf
[Hexagon] Adding doubleworld accumulating multiplies of halfwords.
...
llvm-svn: 224267
2014-12-15 20:17:46 +00:00
572c53e258
[Hexagon] Adding accumulating half word multiplies.
...
llvm-svn: 224266
2014-12-15 20:10:28 +00:00
d1704cdc07
[Hexagon] Adding multiply with rnd/sat/rndsat
...
llvm-svn: 224265
2014-12-15 20:01:59 +00:00
fe4012a969
[Hexagon] Adding encoding bits for halfword multiplies.
...
llvm-svn: 224261
2014-12-15 19:22:07 +00:00
90482a77b1
[Hexagon] Adding double word add/min/minu/max/maxu instructions and tests.
...
llvm-svn: 224153
2014-12-12 21:29:25 +00:00
984ef17d66
[Hexagon] Adding J class call instructions.
...
llvm-svn: 224150
2014-12-12 21:12:27 +00:00
7e37a5f523
[CodeGen] Add print and verify pass after each MachineFunctionPass by default
...
Previously print+verify passes were added in a very unsystematic way, which is
annoying when debugging as you miss intermediate steps and allows bugs to stay
unnotice when no verification is performed.
To make this change practical I added the possibility to explicitely disable
verification. I used this option on all places where no verification was
performed previously (because alot of places actually don't pass the
MachineVerifier).
In the long term these problems should be fixed properly and verification
enabled after each pass. I'll enable some more verification in subsequent
commits.
This is the 2nd attempt at this after realizing that PassManager::add() may
actually delete the pass.
llvm-svn: 224059
2014-12-11 21:26:47 +00:00
01c73610d0
This reverts commit r224043 and r224042.
...
check-llvm was failing.
llvm-svn: 224045
2014-12-11 20:03:57 +00:00
a7c82a9f1d
[CodeGen] Add print and verify pass after each MachineFunctionPass by default
...
Previously print+verify passes were added in a very unsystematic way, which is
annoying when debugging as you miss intermediate steps and allows bugs to stay
unnotice when no verification is performed.
To make this change practical I added the possibility to explicitely disable
verification. I used this option on all places where no verification was
performed previously (because alot of places actually don't pass the
MachineVerifier).
In the long term these problems should be fixed properly and verification
enabled after each pass. I'll enable some more verification in subsequent
commits.
llvm-svn: 224042
2014-12-11 19:42:05 +00:00
150b6b3a73
[Hexagon] Renaming classes in preparation for replacement.
...
llvm-svn: 224036
2014-12-11 19:01:28 +00:00
adab80720d
[Hexagon] Ading i64 <- i32, i32 sextw pattern.
...
llvm-svn: 224027
2014-12-11 17:08:21 +00:00
eb52f69f59
[Hexagon] Adding encoding information for sign extend word instruction.
...
llvm-svn: 224026
2014-12-11 16:43:06 +00:00
220adb6370
[Hexagon] Adding combine ri/ir instructions.
...
llvm-svn: 223971
2014-12-10 22:23:07 +00:00
db0b13cef0
[Hexagon] Adding encodings for JR class instructions. Updating complier usages.
...
llvm-svn: 223967
2014-12-10 21:24:10 +00:00
8872d20788
[Hexagon] Adding JR class predicated call reg instructions.
...
llvm-svn: 223933
2014-12-10 18:24:16 +00:00
b32bf14c2a
[Hexagon] [NFC] Cleaning up unused classes.
...
llvm-svn: 223845
2014-12-09 22:33:26 +00:00
b030c254c0
[Hexagon] Fixing broken tests.
...
llvm-svn: 223823
2014-12-09 20:36:53 +00:00
4af437fee5
[Hexagon] Updating rr/ri 32/64 transfer encodings and adding tests.
...
llvm-svn: 223821
2014-12-09 20:23:30 +00:00
b580d7d8c8
[Hexagon] Adding word combine dot-new form and replacing old combine opcode.
...
llvm-svn: 223815
2014-12-09 19:23:45 +00:00
30dcb232b0
[Hexagon] Updating predicate register transfers and adding tstbit to allow select selection. Updating ll tests with predicate transfers that previously had nop encodings.
...
llvm-svn: 223800
2014-12-09 18:16:49 +00:00
5cf5632696
[Hexagon] Removing old def versions and replacing usages with versions that have encodings.
...
llvm-svn: 223720
2014-12-08 23:55:43 +00:00
f5b4d655d2
[Hexagon] Adding any8, all8, and/or/xor/andn/orn/not predicate register forms, mask, and vitpack instructions and patterns.
...
llvm-svn: 223710
2014-12-08 23:07:59 +00:00
b6c4dd96f9
[Hexagon] Adding xtype doubleword add, sub, and, or, xor and patterns.
...
llvm-svn: 223702
2014-12-08 22:19:14 +00:00
9bfe5473da
[Hexagon] Adding xtype doubleword comparisons. Removing unused multiclass.
...
llvm-svn: 223701
2014-12-08 21:56:47 +00:00
025f860638
[Hexagon] Adding xtype parity, min, minu, max, maxu instructions.
...
llvm-svn: 223693
2014-12-08 21:19:18 +00:00
8d1376c60e
[Hexagon] Adding xtype halfword add/sub ll/hl/lh/hh/sat/<<16 instructions.
...
llvm-svn: 223692
2014-12-08 20:33:01 +00:00
cc46cd8eec
[Hexagon] Adding add/sub with saturation. Removing unused def. Cleaning up shift patterns.
...
llvm-svn: 223680
2014-12-08 18:33:49 +00:00
b56e6cd9b9
[Hexagon] Adding combine reg, reg with predicated forms.
...
llvm-svn: 223667
2014-12-08 17:33:06 +00:00
a55070dbdd
[Hexagon] Adding packhl instruction.
...
llvm-svn: 223664
2014-12-08 17:01:18 +00:00
d8b766072b
[Hexagon] Relocating logical instructions and templates later in the td file.
...
llvm-svn: 223523
2014-12-05 21:51:12 +00:00
2c77a35e6e
[Hexagon] Adding sub/and/or reg, imm forms
...
llvm-svn: 223522
2014-12-05 21:38:29 +00:00
9665f98c10
[Hexagon] Updating mux_ir/ri/ii/rr with encoding bits
...
llvm-svn: 223515
2014-12-05 21:09:27 +00:00
19985e9a8d
[Hexagon] Adding tfrih/l instructions.
...
llvm-svn: 223506
2014-12-05 20:07:19 +00:00
a4ab58101a
[Hexagon] Adding add reg, imm form with encoding bits and test.
...
llvm-svn: 223504
2014-12-05 19:51:23 +00:00
383c36e3a8
[Hexagon] Adding DoubleRegs decoder. Moving C2_mux and A2_nop. Adding combine imm-imm form.
...
llvm-svn: 223494
2014-12-05 18:24:06 +00:00
63035ebee1
[Hexagon] [NFC] Rearranging patterns and mux instruction.
...
llvm-svn: 223488
2014-12-05 17:58:06 +00:00
7358593e34
[Hexagon] [NFC] Rearranging def order.
...
llvm-svn: 223487
2014-12-05 17:55:51 +00:00
7f0a430c7d
[Hexagon] Adding combine reg-reg forms.
...
llvm-svn: 223485
2014-12-05 17:38:36 +00:00
01785bb063
[Hexagon] Marking several instructions as isCodeGenOnly=0 and adding direct disassembly tests for many instructions.
...
llvm-svn: 223482
2014-12-05 17:27:39 +00:00
5d6f03bd5a
[Hexagon] Marking some instructions as CodeGenOnly=0 and adding disassembly tests.
...
llvm-svn: 223334
2014-12-04 03:41:21 +00:00
597fbb5230
HexagonMCInst.h: Qualify constants explicitly to appease msc17.
...
llvm-svn: 223325
2014-12-04 00:26:39 +00:00
654f2d2037
[Hexagon] Converting member InstrDesc to static variable.
...
llvm-svn: 223268
2014-12-03 21:40:25 +00:00
7e9908ea10
[Hexagon] Converting subclass members to an implicit operand.
...
llvm-svn: 223264
2014-12-03 20:23:22 +00:00
089791db48
[NFC] Fixing pendantic warning extra semicolons.
...
llvm-svn: 223246
2014-12-03 17:36:39 +00:00
1d04fa411f
[Hexagon] [NFC] Moving function implementations out of header. Clang-formatting files.
...
llvm-svn: 223245
2014-12-03 17:35:39 +00:00
b4e5be4c66
[Hexagon] [NFC] Renaming *packetStart to *packetBegin
...
llvm-svn: 223243
2014-12-03 17:31:43 +00:00
6e0f9f8d61
[Hexagon] Adding cmp* immediate form instructions.
...
llvm-svn: 222849
2014-11-26 19:43:12 +00:00
31abe33726
[Hexagon] Adding and64, or64, and xor64 instructions.
...
llvm-svn: 222846
2014-11-26 18:55:59 +00:00
c50d64b07b
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files.
...
llvm-svn: 222801
2014-11-26 00:46:26 +00:00
b3d08bb44b
[Hexagon] Adding add64 and sub64 instructions.
...
llvm-svn: 222795
2014-11-25 22:15:44 +00:00
6f6c4ff1fc
Reverting 222792
...
llvm-svn: 222793
2014-11-25 21:39:57 +00:00
aaf33928ee
[Hexagon] Adding compare with immediate instructions.
...
llvm-svn: 222792
2014-11-25 21:30:28 +00:00
6f352b03a4
[Hexagon] Adding NOP encoding bits.
...
llvm-svn: 222791
2014-11-25 21:23:07 +00:00
e83bc7476f
[Hexagon] Adding C2_mux instruction.
...
llvm-svn: 222784
2014-11-25 20:20:09 +00:00
902157c249
[Hexagon] Replacing cmp* instructions with ones that contain encoding bits.
...
llvm-svn: 222771
2014-11-25 18:20:52 +00:00
287c4e1762
Removing unused variable.
...
llvm-svn: 222676
2014-11-24 18:55:32 +00:00
397a25e7cd
[Hexagon] Adding asrh instruction, removing unused multiclasses.
...
llvm-svn: 222670
2014-11-24 18:04:42 +00:00
3b3197ef95
[Hexagon] Adding aslh instruction.
...
llvm-svn: 222668
2014-11-24 17:44:19 +00:00
098256c5e6
[Hexagon] Adding zxth instruction.
...
llvm-svn: 222662
2014-11-24 17:11:34 +00:00
bb7d6f5514
[Hexagon] Adding zxtb instruction.
...
llvm-svn: 222660
2014-11-24 16:48:43 +00:00
310991c66f
[Hexagon] Adding sxth instruction.
...
llvm-svn: 222577
2014-11-21 21:54:59 +00:00
91ffec908f
[Hexagon] Adding sxtb instruction. Renaming some identically named classes that will be removed after converting referencing defs.
...
llvm-svn: 222575
2014-11-21 21:35:52 +00:00
e88447d8de
[Hexagon] Removing SUB_rr and replacing with A2_sub.
...
llvm-svn: 222571
2014-11-21 21:19:18 +00:00
357600eab5
Add out of line virtual destructors to all LLVMTargetMachine subclasses
...
These recently all grew a unique_ptr<TargetLoweringObjectFile> member in
r221878. When anyone calls a virtual method of a class, clang-cl
requires all virtual methods to be semantically valid. This includes the
implicit virtual destructor, which triggers instantiation of the
unique_ptr destructor, which fails because the type being deleted is
incomplete.
This is just part of the ongoing saga of PR20337, which is affecting
Blink as well. Because the MSVC ABI doesn't have key functions, we end
up referencing the vtable and implicit destructor on any virtual call
through a class. We don't actually end up emitting the dtor, so it'd be
good if we could avoid this unneeded type completion work.
llvm-svn: 222480
2014-11-20 23:37:18 +00:00
fee89e43ad
Update Makefile following directory removal in r222466
...
llvm-svn: 222475
2014-11-20 22:48:24 +00:00
ff06261aed
[Hexagon] [NFC] Merging InstPrinter directory in to MCTargetDesc since they have a circular dependency.
...
llvm-svn: 222458
2014-11-20 21:56:35 +00:00
ac00643603
[Hexagon] Adding A2_xor instruction with IR selection pattern and test.
...
llvm-svn: 222399
2014-11-19 23:22:23 +00:00
21866546ae
[Hexagon] Adding A2_or instruction with IR selection pattern and test.
...
llvm-svn: 222396
2014-11-19 22:58:04 +00:00
44fd1c8bdf
[Hexagon] Adding A2_and instruction.
...
llvm-svn: 222274
2014-11-18 22:45:47 +00:00
38765e6d89
[Hexagon] Adding A2_sub instruction
...
Renaming test files.
llvm-svn: 222263
2014-11-18 21:51:51 +00:00
efa74e0280
[Hexagon] Converting from ADD_rr to A2_add which has encoding bits.
...
Adding test to show correct instruction selection and encoding.
llvm-svn: 222249
2014-11-18 20:28:11 +00:00
3053155652
We can get the TLOF from the TargetMachine - so constructor no longer requires TargetLoweringObjectFile to be passed.
...
llvm-svn: 221926
2014-11-13 21:29:21 +00:00
b6bbeee744
[Hexagon]
...
NFC Renaming reserved identifier.
llvm-svn: 221898
2014-11-13 16:36:30 +00:00
a27193297f
This patch changes the ownership of TLOF from TargetLoweringBase to TargetMachine so that different subtargets could share the TLOF effectively
...
llvm-svn: 221878
2014-11-13 09:26:31 +00:00
7fc5b87480
Pass an ArrayRef to MCDisassembler::getInstruction.
...
With this patch MCDisassembler::getInstruction takes an ArrayRef<uint8_t>
instead of a MemoryObject.
Even on X86 there is a maximum size an instruction can have. Given
that, it seems way simpler and more efficient to just pass an ArrayRef
to the disassembler instead of a MemoryObject and have it do a virtual
call every time it wants some extra bytes.
llvm-svn: 221751
2014-11-12 02:04:27 +00:00
4aa6bea7a2
Misc style fixes. NFC.
...
This fixes a few cases of:
* Wrong variable name style.
* Lines longer than 80 columns.
* Repeated names in comments.
* clang-format of the above.
This make the next patch a lot easier to read.
llvm-svn: 221615
2014-11-10 18:11:10 +00:00
2c769209a1
[Hexagon] Adding basic Hexagon ELF object emitter.
...
llvm-svn: 221465
2014-11-06 17:05:51 +00:00
816ef086f6
[Hexagon] [NFC] Alphabetizing cmake files.
...
llvm-svn: 221370
2014-11-05 17:38:48 +00:00
5241881bbc
[Hexagon] Reverting 220584 to address ASAN errors.
...
llvm-svn: 221210
2014-11-04 00:14:36 +00:00
326f8af463
Handle ctor/init_array initialization.
...
Hexagon was not calling InitializeELF and could not select between
ctors and init_array.
Phabricator revision: http://reviews.llvm.org/D6061
llvm-svn: 221156
2014-11-03 14:56:05 +00:00
729be14435
Prune CRLF.
...
llvm-svn: 220678
2014-10-27 12:37:26 +00:00
838307b31f
[Hexagon] Resubmission of 220427
...
Modified library structure to deal with circular dependency between HexagonInstPrinter and HexagonMCInst.
Adding encoding bits for add opcode.
Adding llvm-mc tests.
Removing unit tests.
http://reviews.llvm.org/D5624
llvm-svn: 220584
2014-10-24 19:00:32 +00:00
5b6f789d7a
Hexagon/Disassembler/LLVMBuild.txt: Update libdeps.
...
llvm-svn: 220482
2014-10-23 11:32:16 +00:00
f459febb15
Hexagon/LLVMBuild.txt: Prune CRLF.
...
llvm-svn: 220481
2014-10-23 11:32:03 +00:00
bd20251a4a
[CMake] Prune CRLF in CMakeLists.txt(s).
...
llvm-svn: 220480
2014-10-23 11:31:50 +00:00
504bbf91cd
Revert r220427, "[Hexagon] Adding encoding bits for add opcode."
...
It brought cyclic dependecy between HexagonAsmPrinter and HexagonDesc.
llvm-svn: 220478
2014-10-23 11:31:22 +00:00
73a51a1a68
[Hexagon] Adding encoding bits for add opcode.
...
Adding llvm-mc tests.
Removing unit tests.
http://reviews.llvm.org/D5624
llvm-svn: 220427
2014-10-22 20:58:35 +00:00
db08566588
Fix VS2012 build; C++11 type aliases are not supported.
...
llvm-svn: 220399
2014-10-22 17:47:49 +00:00
b424cb1e57
Ammending 220393 - Removing unused decoding tables.
...
llvm-svn: 220397
2014-10-22 17:23:01 +00:00
9950d5c59a
Ammending 220393 - Removing unused functions.
...
llvm-svn: 220396
2014-10-22 17:03:19 +00:00
88ebb9e2da
[Hexagon] Adding basic disassembler.
...
Marking all instructions as CodeGenOnly since encoding bits are not set yet.
http://reviews.llvm.org/D5829?vs=on&id=15023&whitespace=ignore-all#toc
llvm-svn: 220393
2014-10-22 16:49:14 +00:00
7055365e77
Test commit
...
Fixing brief comment.
llvm-svn: 220299
2014-10-21 16:03:10 +00:00
c374ac97c8
Remove unnecessary else.
...
llvm-svn: 220200
2014-10-20 13:08:19 +00:00
a002296427
Wrong attribute. LLVM_ATTRIBUTE_UNUSED not LLVM_ATTRIBUTE_USED
...
This original fix for the build break was correct. LLVM_ATTRIBUTE_USED
removes the warning message because it keeps the function in the object
file. LLVM_ATTRIBUTE_UNUSED indicates that it may or may not be used
depending on build settings.
llvm-svn: 219846
2014-10-15 20:41:17 +00:00
2ceaeb6baf
Wrong attribute. LLVM_ATTRIBUTE_USED not LLVM_ATTRIBUTE_UNUSED
...
llvm-svn: 219837
2014-10-15 19:32:52 +00:00
74cd020fca
Add LLVM_ATTRIBUTE_UNUSED to function currently just used in an assert
...
Fixes break when -Wunused-function is used.
llvm-svn: 219833
2014-10-15 19:24:14 +00:00
12cd21aacd
Enable the instruction printer in HexagonMCTargetDesc
...
This adds the MCInstPrinter to the LLVMHexagonDesc library and removes
the dependency LLVMHexagonAsmPrinter had on LLVMHexagonDesc. This is
a prerequisite needed by the disassembler.
Phabricator Revision: http://reviews.llvm.org/D5734
llvm-svn: 219826
2014-10-15 18:27:40 +00:00
2a321f74f0
Remove the TargetMachine from DFAPacketizer since it was only
...
being used to grab subtarget specific things that we can grab
from the MachineFunction anyhow.
llvm-svn: 219650
2014-10-14 01:03:16 +00:00
143f02c47d
Remove unused argument to CreateTargetScheduleState and change
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the TargetMachine to a TargetSubtargetInfo since everything
we wanted is off of that.
llvm-svn: 219382
2014-10-09 01:59:35 +00:00
2a295fd337
HexagonMCCodeEmitter.cpp: Prune 2nd redundant \brief. [-Wdocumentation]
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llvm-svn: 219073
2014-10-05 04:54:54 +00:00
431c9d3f1f
HexagonDesc: Update LLVMBuild.txt.
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llvm-svn: 219071
2014-10-05 04:54:29 +00:00
c6cc58e703
Remove unnecessary copying or replace it with moves in a bunch of places.
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NFC.
llvm-svn: 219061
2014-10-04 16:55:56 +00:00
da47cf46de
HexagonMCCodeEmitter.h: deleted member functions are not supported in VS2012
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llvm-svn: 218990
2014-10-03 17:02:28 +00:00
40d809399f
Fix build break on Hexagon
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Differential Revision: http://reviews.llvm.org/D5600
llvm-svn: 218987
2014-10-03 13:59:01 +00:00
7da3f9acba
Adding skeleton for unit testing Hexagon Code Emission
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Adding and modifying CMakeLists.txt files to run unit tests under
unittests/Target/* if the directory exists. Adding basic unit test to check
that code emitter object can be retrieved.
Differential Revision: http://reviews.llvm.org/D5523
Change by: Colin LeMahieu
llvm-svn: 218986
2014-10-03 13:18:11 +00:00
31f7125562
Add missing attributes !cmp.[eq,gt,gtu] instructions.
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These instructions do not indicate they are extendable or the
number of bits in the extendable operand. Rename to match
architected names. Add a testcase for the intrinsics.
llvm-svn: 218453
2014-09-25 13:09:54 +00:00
bd8bd484c3
Loop instead of individual def's for each GPR.
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Differential Revision: http://reviews.llvm.org/D5450
llvm-svn: 218305
2014-09-23 13:55:50 +00:00
0bb041b5f4
Reverting NFC changes from r218050. Instead, the warning was disabled for GCC in r218059, so these changes are no longer required.
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llvm-svn: 218062
2014-09-18 17:34:23 +00:00
11fa97fa32
Fixing a bunch of -Woverloaded-virtual warnings due to hiding getSubtargetImpl from the base class. NFC.
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llvm-svn: 218050
2014-09-18 13:27:14 +00:00
e7b92f0e81
Add missing HWEncoding to base register class.
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This change gives tblgen the information needed to fill in the
HexagonRegEncodingTable.
llvm-svn: 217500
2014-09-10 13:09:25 +00:00
ac3e325d67
Spelling correction
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Another trivial spelling change.
llvm-svn: 217364
2014-09-08 13:05:23 +00:00
8c90fd71f7
Add override to overriden virtual methods, remove virtual keywords.
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No functionality change. Changes made by clang-tidy + some manual cleanup.
llvm-svn: 217028
2014-09-03 11:41:21 +00:00
fd38cbebda
Remove 'virtual' keyword from methods markedwith 'override' keyword.
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llvm-svn: 216823
2014-08-30 16:48:34 +00:00
67a8936a84
Minor spelling correction.
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Reviewers: adasgupt, jverma, sidneym
Differential Revision: http://reviews.llvm.org/D5025
llvm-svn: 216667
2014-08-28 14:16:32 +00:00
2651ae6513
Fix undefined behavior (left shift of negative value) in Hexagon backend.
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This bug is reported by UBSan.
llvm-svn: 216125
2014-08-20 21:22:03 +00:00
ea0aee622e
Cleanup: Delete seemingly unused reference to MachineDominatorTree from ScheduleDAGInstrs.
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llvm-svn: 216124
2014-08-20 20:57:26 +00:00
8968e6d1b0
Fix null reference creation in ScheduleDAGInstrs constructor call.
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Both MachineLoopInfo and MachineDominatorTree may be null in ScheduleDAGMI
constructor call. It is undefined behavior to take references to these values.
This bug is reported by UBSan.
llvm-svn: 216118
2014-08-20 19:36:05 +00:00
d18cda620c
Fix typos in comments
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llvm-svn: 215777
2014-08-15 22:17:28 +00:00
d610ba99cb
Remove HasLEB128.
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We already require CFI, so it should be safe to require .leb128 and .uleb128.
llvm-svn: 215712
2014-08-15 14:01:07 +00:00
a7c40ef022
Canonicalize header guards into a common format.
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Add header guards to files that were missing guards. Remove #endif comments
as they don't seem common in LLVM (we can easily add them back if we decide
they're useful)
Changes made by clang-tidy with minor tweaks.
llvm-svn: 215558
2014-08-13 16:26:38 +00:00
b5217507c7
Remove the target machine from CCState. Previously it was only used
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to get the subtarget and that's accessible from the MachineFunction
now. This helps clear the way for smaller changes where we getting
a subtarget will require passing in a MachineFunction/Function as
well.
llvm-svn: 214988
2014-08-06 18:45:26 +00:00
fc6de428c8
Have MachineFunction cache a pointer to the subtarget to make lookups
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shorter/easier and have the DAG use that to do the same lookup. This
can be used in the future for TargetMachine based caching lookups from
the MachineFunction easily.
Update the MIPS subtarget switching machinery to update this pointer
at the same time it runs.
llvm-svn: 214838
2014-08-05 02:39:49 +00:00
d913448b38
Remove the TargetMachine forwards for TargetSubtargetInfo based
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information and update all callers. No functional change.
llvm-svn: 214781
2014-08-04 21:25:23 +00:00
04b8b37f56
Prune Redundant libdeps in CMake's target_link_libraries and LLVMBuild.txt.
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I checked this with Release+Asserts on x86_64-mingw32. Please restore partially if this were overkill.
llvm-svn: 213064
2014-07-15 11:37:03 +00:00
cf21875d41
Fix 'platform-specific' hyphenations
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llvm-svn: 212056
2014-06-30 18:57:16 +00:00
c4c63ae9f4
Move all of the hexagon subtarget dependent variables from the target
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machine to the subtarget.
llvm-svn: 211824
2014-06-27 00:27:40 +00:00
4496eb0b09
Have HexagonSelectionDAGInfo take a DataLayout rather than a
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target machine since that's all it needs.
llvm-svn: 211822
2014-06-27 00:18:25 +00:00
dbe1cb0d59
Make HexagonISelLowering not dependent upon a HexagonTargetMachine,
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but a normal TargetMachine and remove a few cached uses.
llvm-svn: 211821
2014-06-27 00:13:52 +00:00
6e9bcd1528
Reduce indentation.
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llvm-svn: 211820
2014-06-27 00:13:49 +00:00
a68f376333
Remove unnecessary caching of the subtarget for HexagonFrameLowering and remove the unused constructor argument.
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llvm-svn: 211819
2014-06-27 00:13:47 +00:00
0d0b3600d8
InstrItineraryData is already on the subtarget, no reason to
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cache it on the target as well.
llvm-svn: 211818
2014-06-27 00:13:43 +00:00
35b2f75733
Convert some assert(0) to llvm_unreachable or fold an 'if' condition into the assert.
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llvm-svn: 211254
2014-06-19 06:10:58 +00:00
d172270c44
Hexagon: Expand i1 SELECT_CC
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il is legal for Hexagon, so I should have marked this as Expand for
SELECT_CC when I removed setOperationAction(ISD::SELECT_CC, MVT::Other,
Expand); in r210541.
llvm-svn: 210544
2014-06-10 16:42:41 +00:00
3787b12255
SelectionDAG: Don't use MVT::Other to determine legality of ISD::SELECT_CC
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The SelectionDAG bad a special case for ISD::SELECT_CC, where it would
allow targets to specify:
setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
to indicate that they wanted to expand ISD::SELECT_CC for all types.
This wasn't applied correctly everywhere, and it makes writing new
DAG patterns with ISD::SELECT_CC difficult.
llvm-svn: 210541
2014-06-10 16:01:29 +00:00
3ca1bfc728
SelectionDAG: Expand SELECT_CC to SELECT + SETCC
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This consolidates code from the Hexagon, R600, and XCore targets.
No functionality change intended.
llvm-svn: 210539
2014-06-10 16:01:22 +00:00
0dd8d486b3
Have TargetSelectionDAGInfo take a DataLayout initializer rather than
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a TargetMachine since the only thing it wants is DataLayout.
llvm-svn: 210366
2014-06-06 19:04:48 +00:00
0120db5f8a
Remove getTargetLowering from TargetPassConfig as the target lowering
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can change depending upon subtarget/subtarget features for a function.
llvm-svn: 209329
2014-05-21 22:42:07 +00:00
Colin LeMahieu