53d2de923a
Add definitions for function headers from MRegisterInfo.h:
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Some functions are in X86RegisterInfo.cpp, others, because of the data they
need, are in X86RegisterClasses.cpp, which also defines some register classes:
byte, short, and int.
llvm-svn: 4784
2002-11-20 18:59:43 +00:00
6e5d493e0f
Check not only for MO_VirtualRegister, but MO_MachineRegister as well when
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printing out assembly. After all, we want the real thing too.
llvm-svn: 4783
2002-11-20 18:56:41 +00:00
eaaceb1210
Add mapping in MachineFunction from SSA regs to Register Classes. Also,
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uncovered a bug where registers were not being put in a map if they were not
found...
llvm-svn: 4776
2002-11-20 00:58:23 +00:00
ade1143692
Sigh. Fixed some speling.
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llvm-svn: 4775
2002-11-20 00:56:42 +00:00
310afc5f8c
Thanks to the R8, R16, and R32 macros, I can now deal with registers that
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belong to different register classes easier.
llvm-svn: 4773
2002-11-20 00:47:40 +00:00
a648bc6674
Brian Gaeke says:
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lib/Target/X86/InstSelectSimple.cpp: Add a little something to
visitBranchInst which supports conditional branches.
lib/Target/X86/X86InstrInfo.def: Add defs of JNE, JE, CMPri8
llvm-svn: 4755
2002-11-19 09:08:47 +00:00
5812f06b30
Start trying to print instructions more correctly. For now we also print out the opcode for each instruction as well.
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llvm-svn: 4743
2002-11-18 06:56:51 +00:00
cf72e52df3
Expose base opcode
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llvm-svn: 4742
2002-11-18 06:56:24 +00:00
0018e8d5fc
Start to add more information to instr.def
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llvm-svn: 4741
2002-11-18 05:37:11 +00:00
f2e00c62ab
Add instruction annotation about whether it has a 0x0F opcode prefix
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llvm-svn: 4740
2002-11-18 01:59:28 +00:00
c6f7457e90
Add more void flags
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llvm-svn: 4739
2002-11-18 01:37:48 +00:00
dbdacac022
Set the void flag on instructions that should get it
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llvm-svn: 4738
2002-11-18 01:34:36 +00:00
5fd53046b0
Arrange to have a TargetMachine available in X86InstrInfo::print
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llvm-svn: 4734
2002-11-17 23:20:37 +00:00
b79ccae887
Wow, I'm incapable of the simplest things today...
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llvm-svn: 4732
2002-11-17 23:05:21 +00:00
afce16dec8
Rename registers to follow the intel style of all caps
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llvm-svn: 4731
2002-11-17 23:03:46 +00:00
9289d7d693
Reorganize printing interface a bit
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llvm-svn: 4728
2002-11-17 22:53:13 +00:00
64c3bb99ed
Fix minor detail
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llvm-svn: 4725
2002-11-17 22:33:26 +00:00
cb57e5ca17
Fix Mul/Div clobbers
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llvm-svn: 4718
2002-11-17 21:56:38 +00:00
ecdb49d74a
Fix a few typos, implement load/store
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llvm-svn: 4716
2002-11-17 21:11:55 +00:00
c682b4a9ab
Add functions to buld X86 specific constructs
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llvm-svn: 4714
2002-11-17 21:03:35 +00:00
6fd0ef303d
Add information about memory index representation
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llvm-svn: 4712
2002-11-17 20:33:26 +00:00
e86f98e06c
Add load/store instructions
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llvm-svn: 4711
2002-11-17 20:33:12 +00:00
09fddd97fb
Switch visitRet to use getClass()
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llvm-svn: 4710
2002-11-17 20:07:45 +00:00
e74543584a
include/llvm/CodeGen/MachineInstrBuilder.h: Add addClobber() inline
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convenience method. Fix typo in comment.
lib/Target/X86/InstSelectSimple.cpp: Explicitly specify some implicit uses.
Use MOVZX/MOVSX instead of MOV instructions with sign extend instructions.
Take out LEAVE instructions.
32-bit IDIV and DIV use CDQ, not CWQ (CWQ is a typo).
Fix typo in comment and remove some FIXME comments.
lib/Target/X86/Printer.cpp: Include X86InstrInfo.h and llvm/Function.h.
Add some simple code to Printer::runOnFunction to iterate over
MachineBasicBlocks and call X86InstrInfo::print().
lib/Target/X86/X86InstrInfo.def: Make some more instructions with
implicit defs "Void". Add more sign/zero extending "move" insns
(movsx, movzx).
lib/Target/X86/X86RegisterInfo.def: Add EFLAGS as a register.
llvm-svn: 4707
2002-11-14 22:32:30 +00:00
b2687880e2
InstSelectSimple.cpp: (visitReturnInst) Add return instructions with return
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values.
X86InstrInfo.def: add LEAVE instruction.
llvm-svn: 4691
2002-11-11 19:37:09 +00:00
9cbe229704
Add instruction selection code and tests for setcc instructions
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llvm-svn: 4603
2002-11-07 17:59:21 +00:00
781986c436
Implement signed and unsigned division and remainder
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llvm-svn: 4508
2002-11-02 20:54:46 +00:00
d12e1bc777
Implement multiply operator
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llvm-svn: 4506
2002-11-02 20:28:58 +00:00
e823fb32f4
* Implement subtract
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* Merge add code into logical code
llvm-svn: 4503
2002-11-02 20:13:22 +00:00
dd873d2179
shuffle code around a bit, implement and, or, xor
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llvm-svn: 4502
2002-11-02 20:04:26 +00:00
abe3280ad9
Add PHI node support, add comment for branch function
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llvm-svn: 4500
2002-11-02 19:45:49 +00:00
16af2d5aa8
Implement unconditional branching support
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llvm-svn: 4498
2002-11-02 19:27:56 +00:00
cfb187f6bb
* Fix nonconstant shift case
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* Turn table into 2d table
llvm-svn: 4496
2002-11-02 01:41:55 +00:00
ff3d28f403
Use a more table driven approach to handling types. Seems to simplify the
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code a bit
llvm-svn: 4493
2002-11-02 01:15:18 +00:00
63f4e752cd
Make switch statements denser, but only because of the follow-on patch
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llvm-svn: 4492
2002-11-02 00:49:56 +00:00
122b73b7a6
* Remove dead variable
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* Shift amount is always guaranteed to be 8 bits
llvm-svn: 4491
2002-11-02 00:44:25 +00:00
6e2d676829
InstSelectSimple.cpp: Include llvm/iOther.h for ShiftInst.
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Add ISel::visitShiftInst() to instruction select shift instructions.
Add a comment in visitAdd about how to do 64 bit adds.
X86InstrInfo.def: Add register-to-register move opcodes and shift opcodes.
llvm-svn: 4477
2002-10-31 23:03:59 +00:00
6c34c0baf5
Add lots more info
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llvm-svn: 4450
2002-10-30 06:04:46 +00:00
c9e1efd0f8
Make sure to set the destination register correctly
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llvm-svn: 4444
2002-10-30 01:49:01 +00:00
87b84a6913
Set the destination register field based on the target specific flags
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llvm-svn: 4442
2002-10-30 01:15:31 +00:00
60c59d5b4e
Add flag to specify when no value is produced by an instruction
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llvm-svn: 4441
2002-10-30 01:09:34 +00:00
858a4a6595
Implement the new optional getRegisterInfo
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llvm-svn: 4437
2002-10-30 00:56:18 +00:00
d7a855668d
Print machine code after instruction selection
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llvm-svn: 4434
2002-10-30 00:47:49 +00:00
e3ceb17d54
Make sure to pass the LLVM basic block in
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llvm-svn: 4433
2002-10-30 00:47:40 +00:00
7ee171b717
Construct annotation, to make sure it's attached to function
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llvm-svn: 4429
2002-10-29 23:40:58 +00:00
02a3d837c2
Convert backend to use passes, implement X86TargetMachine
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llvm-svn: 4421
2002-10-29 22:37:54 +00:00
27d247978b
Rename X86InstructionInfo to X86InstrInfo
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llvm-svn: 4413
2002-10-29 21:05:24 +00:00
f57420ee17
Minor renaming
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llvm-svn: 4410
2002-10-29 20:48:56 +00:00
2990e9b6cd
Switch to generating machineinstr's instead of MInstructions
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llvm-svn: 4396
2002-10-29 17:43:55 +00:00
6c3f9c1b8f
Be compatible with sparc backend
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llvm-svn: 4395
2002-10-29 17:43:38 +00:00
16cbd41c21
Implement MachineInstrInfo interface
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llvm-svn: 4394
2002-10-29 17:43:19 +00:00
f4b122dbc5
Switch to different flag set
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llvm-svn: 4393
2002-10-29 17:42:40 +00:00
1303f2f057
Initial stab at MachineInstr'ication
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llvm-svn: 4367
2002-10-28 23:55:19 +00:00
d5b45791a4
Fixed spelling and grammar.
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llvm-svn: 4353
2002-10-28 20:01:52 +00:00
52c2d10a19
Remove dead fixme
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llvm-svn: 4300
2002-10-27 21:23:43 +00:00
7d3e5dbf2b
Instruction select constant arguments correctly
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llvm-svn: 4297
2002-10-27 21:16:59 +00:00
407582dc5a
Add instruction definitions for mov r, imm instructions
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llvm-svn: 4296
2002-10-27 21:16:44 +00:00
d92fb0058b
Initial checkin of X86 backend.
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We can instruction select exactly one instruction 'ret void'. Wow.
llvm-svn: 4284
2002-10-25 22:55:53 +00:00
Misha Brukman