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3882 Commits

Author SHA1 Message Date
Jason W Kim 29805961d8 ARM/MC/ELF relocation "hello world" for movw/movt. 
Lifted adjustFixupValue() from Darwin for sharing w ELF.
Test added
TODO:
  refactor ELFObjectWriter::RecordRelocation more.
  Possibly share more code with Darwin?
  Lots more relocations...

llvm-svn: 120534
 2010-12-01 02:40:06 +00:00
Bill Wendling 9c25894995 Formatting. It's all the rage! 
llvm-svn: 120533
 2010-12-01 02:36:55 +00:00
Bill Wendling 8ed14ae48a More refactoring. This time the T1pI pattern. 
llvm-svn: 120532
 2010-12-01 02:28:08 +00:00
Eric Christopher 119ff7ff04 Refactor load/store handling again. Simplify and make some room for 
reg+reg handling.

llvm-svn: 120526
 2010-12-01 01:40:24 +00:00
Jan Wen Voung d602c2cc19 Initialize an ARMConstantPoolValue field. 
llvm-svn: 120525
 2010-12-01 01:38:58 +00:00
Bill Wendling c25545a1a7 s/T1pIEncode/T1pILdStEncode/g 
s/T1pIEncodeImm/T1pILdStEncodeImm/g

llvm-svn: 120524
 2010-12-01 01:38:08 +00:00
Bill Wendling 7c646b924b Renaming variables to coincide with documentation. No functionality change. 
llvm-svn: 120522
 2010-12-01 01:32:02 +00:00
Bill Wendling 490240a5d9 Refactor T1sI and T1sIt encodings into helper classes. 
llvm-svn: 120518
 2010-12-01 01:20:15 +00:00
Bill Wendling 4915f56669 Refactor the T1sIt encodings into a parent class to get rid of all of the "let" 
statements.

llvm-svn: 120512
 2010-12-01 00:48:44 +00:00
Owen Anderson 4472801765 Use by-name rather than by-order matching for NEON operands. 
llvm-svn: 120507
 2010-12-01 00:28:25 +00:00
Evan Cheng d4b0873c06 Enable sibling call optimization of libcalls which are expanded during 
legalization time. Since at legalization time there is no mapping from
SDNode back to the corresponding LLVM instruction and the return
SDNode is target specific, this requires a target hook to check for
eligibility. Only x86 and ARM support this form of sibcall optimization
right now.
rdar://8707777

llvm-svn: 120501
 2010-11-30 23:55:39 +00:00
Bill Wendling 05632cb5cc Rename operands to match ARM documentation. No functionality change. 
llvm-svn: 120500
 2010-11-30 23:54:45 +00:00
Jim Grosbach ee48d2daaa Fix typo. 
llvm-svn: 120499
 2010-11-30 23:51:41 +00:00
Jim Grosbach 38d90de7c3 Trailing whitespace. 
llvm-svn: 120497
 2010-11-30 23:29:24 +00:00
Jason W Kim c440e79126 Thanks to JimG for catching this! 
llvm-svn: 120494
 2010-11-30 23:27:18 +00:00
Bill Wendling 5c51fcda81 Inline classes that were used in only one place. 
llvm-svn: 120488
 2010-11-30 23:16:25 +00:00
Bill Wendling a9e3df7aa0 * Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same as 
t_addrmode_s4, but with a different scaling factor.

* Encode the Thumb1 load and store instructions. This involved a bit of
  refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and
  were removed.

llvm-svn: 120482
 2010-11-30 22:57:21 +00:00
Owen Anderson 8335e8fa63 Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. This allows the 
Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free.
It also allows us to fold away at least one codegen-only pattern.

llvm-svn: 120481
 2010-11-30 22:45:47 +00:00
Jim Grosbach 2d3e5c1aec Fix handling of ARM negative pc-relative fixups for loads and stores. 
llvm-svn: 120480
 2010-11-30 22:40:36 +00:00
Owen Anderson 0dc6246fc0 Provide Thumb2 encodings for a few miscellaneous instructions. 
llvm-svn: 120455
 2010-11-30 20:00:01 +00:00
Jim Grosbach 233890547d Add FIXME 
llvm-svn: 120451
 2010-11-30 19:25:56 +00:00
Owen Anderson 299382e8cb Add encoding support for Thumb2 PLD and PLI instructions. 
llvm-svn: 120449
 2010-11-30 19:19:31 +00:00
Eric Christopher 78b4efb472 Noticed this on inspection, fix and update some comments. 
llvm-svn: 120447
 2010-11-30 19:14:07 +00:00
Jim Grosbach 3b4e2ab5f3 Pseudo-ize ARM MOVPCRX 
llvm-svn: 120442
 2010-11-30 18:56:36 +00:00
Owen Anderson ebcd9c9258 Provide encodings for a few more load/store variants. 
llvm-svn: 120439
 2010-11-30 18:38:28 +00:00
Jim Grosbach cd5e30f6c6 Pseudo-ize BX_CALL and friends. Remove dead instruction format classes. 
rdar://8685712

llvm-svn: 120438
 2010-11-30 18:30:19 +00:00
Bill Wendling 811c936ed5 Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almost 
certainly be made more generic. But it does allow us to parse something like:

          ldr     r3, [r2, r4]

correctly in Thumb mode.

llvm-svn: 120408
 2010-11-30 07:44:32 +00:00
Bill Wendling ddce9f3757 Minor cleanups. No functional change. 
llvm-svn: 120372
 2010-11-30 00:50:22 +00:00
Bill Wendling 8294a30d54 s/ARM::BRIND/ARM::BX/g to coincide with r120366. 
llvm-svn: 120371
 2010-11-30 00:48:15 +00:00
Bill Wendling 62718de2b9 Add correct encoding for "bl __aeabi_read_tp". However, the asm matcher isn't 
able to match this yet.

llvm-svn: 120369
 2010-11-30 00:34:08 +00:00
Jim Grosbach 027bd47e3e Rename BX/BRIND/etc patterns to clarify which is actually the BX instruction 
and which are pseudos.

llvm-svn: 120366
 2010-11-30 00:24:05 +00:00
Bill Wendling 85a8a72d85 Add some encoding for the adr instruction. Labels still need to be finished. 
llvm-svn: 120365
 2010-11-30 00:18:30 +00:00
Owen Anderson e22c7322b8 Correct Thumb2 encodings for a much wider range of loads and stores. 
llvm-svn: 120364
 2010-11-30 00:14:31 +00:00
Jim Grosbach 49408cef39 Make a few more ARM pseudo instructions actually use the PseudoInst base class. 
llvm-svn: 120362
 2010-11-30 00:09:06 +00:00
Bill Wendling ce3d6ca564 Predicate encoding should be withing {}s. And general cleanup. 
llvm-svn: 120361
 2010-11-30 00:08:20 +00:00
Bill Wendling 795f211418 Predicate encoding should be withing {}s. 
llvm-svn: 120360
 2010-11-30 00:05:25 +00:00
Bob Wilson 318ce7cb3f Fix the encoding of VLD4-dup alignment. 
The only reasonable way I could find to do this is to provide an alternate
version of the addrmode6 operand with a different encoding function.  Use it
for all the VLD-dup instructions for the sake of consistency.

llvm-svn: 120358
 2010-11-30 00:00:42 +00:00
Bob Wilson 0b27b68164 Rename VLDnDUP instructions with double-spaced registers 
in an attempt to make things a little more consistent.

llvm-svn: 120357
 2010-11-30 00:00:38 +00:00
Bob Wilson 431ac4ef50 Add support for NEON VLD3-dup instructions. 
The encoding for alignment in VLD4-dup instructions is still a work in progress.

llvm-svn: 120356
 2010-11-30 00:00:35 +00:00
Jim Grosbach 9de9a73433 Simplify definitions of the ARM eh.sjlj.*jmp pseudo instructions. 
llvm-svn: 120354
 2010-11-29 23:51:31 +00:00
Jim Grosbach 0c51bb4b25 Parameterize ARMPseudoInst size property. 
llvm-svn: 120353
 2010-11-29 23:48:41 +00:00
Jim Grosbach cb803b043b Add a few missing initializers. 
llvm-svn: 120350
 2010-11-29 23:41:10 +00:00
Jim Grosbach 32ff5586fc Nuke trailing whitespace. 
llvm-svn: 120344
 2010-11-29 23:18:01 +00:00
Jim Grosbach 9f0356b3cc Nuke a FIXME. No need to be fancier here, as ARM handles constant pools 
locations and formatting specially. rdar://7353441

llvm-svn: 120343
 2010-11-29 23:09:20 +00:00
Owen Anderson 50d662b6cb Provide Thumb2 encodings for basic loads and stores. 
llvm-svn: 120340
 2010-11-29 22:44:32 +00:00
Evan Cheng 9a133f623c Mark Darwin call instructions as using "r7" to prevent the frame-register 
assignment instructions from being moved below / above calls.
rdar://8690640

llvm-svn: 120339
 2010-11-29 22:43:27 +00:00
Jim Grosbach d5cfca1e3d Nuke dead isCodeGenOnly annotation and extraneous comment. 
llvm-svn: 120338
 2010-11-29 22:40:58 +00:00
Jim Grosbach 1883d94630 tidy up. 
llvm-svn: 120335
 2010-11-29 22:38:48 +00:00
Bill Wendling ee7c5659d7 Thumb encodings for conditional moves. 
llvm-svn: 120334
 2010-11-29 22:37:46 +00:00
Jim Grosbach 7ec3d34553 Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw 
instructions. This simplifies instruction printing and disassembly.

llvm-svn: 120333
 2010-11-29 22:37:40 +00:00