119ff7ff04
Refactor load/store handling again. Simplify and make some room for
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reg+reg handling.
llvm-svn: 120526
2010-12-01 01:40:24 +00:00
78b4efb472
Noticed this on inspection, fix and update some comments.
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llvm-svn: 120447
2010-11-30 19:14:07 +00:00
43b0c6d94f
Update fastisel for the changes in r120272.
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llvm-svn: 120324
2010-11-29 21:56:23 +00:00
527da1b6e2
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.
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llvm-svn: 119990
2010-11-23 03:31:01 +00:00
0a3c28bd6b
Rewrite address handling to use a structure with all the possible address
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mode variables. Handle frame indexes in load/store and allocas again.
llvm-svn: 119912
2010-11-20 22:38:27 +00:00
d0aec3bf64
STRH only needs the additional operand, not t2STRH. Also invert conditional
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to match the one from the load emitter above.
llvm-svn: 119911
2010-11-20 22:01:38 +00:00
35e2d7f610
Don't need to save piecemeal now.
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llvm-svn: 119862
2010-11-19 22:39:56 +00:00
cee83d6e6b
Update comment.
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llvm-svn: 119861
2010-11-19 22:37:58 +00:00
558b61e2d4
Update comment.
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llvm-svn: 119859
2010-11-19 22:36:41 +00:00
fef5f315af
Refactor address mode handling into a single struct (ala x86), this
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should give allow a wider range of addressing modes.
No functional change.
llvm-svn: 119856
2010-11-19 22:30:02 +00:00
d7a3550a5e
Remove hard tabs.
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llvm-svn: 119810
2010-11-19 18:01:37 +00:00
964943780b
Recommit this change and remove the failing part of the test - it didn't
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pass in the first place and was masked by earlier failures not warning
and aborting the block.
llvm-svn: 119184
2010-11-15 21:11:06 +00:00
1293c6a23a
Temporarily revert this.
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llvm-svn: 118946
2010-11-12 23:50:48 +00:00
49a66f7d71
Make this happen for ARM like x86. Don't entirely bail out when
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an address is in a different block, get it into a register and go
from there.
llvm-svn: 118936
2010-11-12 22:52:32 +00:00
22d0492f34
Fix up a few more spots of addrmode2 (or not) changes that were
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missed. Update some comments accordingly.
Fixes rdar://8652289
llvm-svn: 118888
2010-11-12 09:48:30 +00:00
68147ee320
Trailing whitespace.
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llvm-svn: 118606
2010-11-09 19:22:26 +00:00
89965d7091
Make sure we have movw on the target before using it.
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Fixes 8559.
llvm-svn: 118333
2010-11-06 07:53:11 +00:00
71049f78ed
In the calling convention logic, ValVT is always a legal type,
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and as such can be represented by an MVT - the more complicated
EVT is not needed. Use MVT for ValVT everywhere.
llvm-svn: 118245
2010-11-04 10:49:57 +00:00
e4dd7378d0
Optimize generated code for integer materialization a bit.
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llvm-svn: 118192
2010-11-03 20:21:17 +00:00
1462777017
Simplify uses of MVT and EVT. An MVT can be compared directly
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with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.
llvm-svn: 118169
2010-11-03 12:17:33 +00:00
f5dda01f33
Inside the calling convention logic LocVT is always a simple
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value type, so there is no point in passing it around using
an EVT. Use the simpler MVT everywhere. Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.
llvm-svn: 118167
2010-11-03 11:35:31 +00:00
c63d846ad6
Invert these branches by default, it makes assembly comparisons a little
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easier to read.
llvm-svn: 118148
2010-11-03 04:29:11 +00:00
1e43892e4b
Make sure we're only storing a single bit here.
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llvm-svn: 118126
2010-11-02 23:59:09 +00:00
b2abb508ae
Remove an assert - it's possible to be hit, and we just want to avoid
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handling those cases for now.
llvm-svn: 117996
2010-11-02 01:24:49 +00:00
ac746e1b38
Whitespeace
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llvm-svn: 117995
2010-11-02 01:22:45 +00:00
e8fccc82e4
No really, no thumb1 for arm fast isel. Also add an informative comment as
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to what someone would need to do to support thumb1.
llvm-svn: 117994
2010-11-02 01:21:28 +00:00
04b0a3e651
Make sure we have a legal type (and simple) before continuing.
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llvm-svn: 117848
2010-10-30 21:25:26 +00:00
5c308f8452
Handle comparison values we already have - this fixes the consumer-typeset
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failure for llvm-gcc on arm fast isel.
llvm-svn: 117710
2010-10-29 21:08:19 +00:00
338de3ee56
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
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the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752
llvm-svn: 117505
2010-10-27 23:12:14 +00:00
055de2c789
Trailing whitespace
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llvm-svn: 117496
2010-10-27 21:39:08 +00:00
5a7c715470
Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on
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rdar://8477752.
llvm-svn: 117419
2010-10-27 00:19:44 +00:00
1e4d9a17c2
First part of refactoring ARM addrmode2 (load/store) instructions to be more
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explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.
llvm-svn: 117409
2010-10-26 22:37:02 +00:00
c9616f26bd
Move rejection of NEON parameters earlier in fast isel call processing,
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note that we can actually handle some f64 arguments.
llvm-svn: 117209
2010-10-23 09:37:17 +00:00
21abfc9450
Silence compiler warnings.
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llvm-svn: 117128
2010-10-22 18:57:05 +00:00
93bbe6599f
Add some basic ret instruction support to arm fast-isel.
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llvm-svn: 117085
2010-10-22 01:28:00 +00:00
2f8637d393
These don't need to be virtual.
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llvm-svn: 117068
2010-10-21 21:47:51 +00:00
b353e4f579
Handle storing args to the stack for calls.
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llvm-svn: 117055
2010-10-21 20:09:54 +00:00
73bc5b0f86
More load/store refactoring, call reg+offset simplification from within
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the emitter to handle the addresses. Only simplify the offset if we need
to - also fix bug where in addrmode 5 we weren't dividing the offset by
4, which showed up due to not always lowering.
llvm-svn: 117051
2010-10-21 19:40:30 +00:00
4ac3ed0219
Custom lower f64 args passed in integer registers.
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llvm-svn: 116977
2010-10-21 00:01:47 +00:00
af719ef86b
Fix a TODO by removing some unnecesary copies.
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llvm-svn: 116915
2010-10-20 08:02:24 +00:00
7b92c2a9a0
Revert r116220 - thus turning arm fast isel back on by default.
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llvm-svn: 116762
2010-10-18 22:53:53 +00:00
167a700229
Remove the check for invalid calling conventions. Testing shows that they're
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working just fine.
llvm-svn: 116698
2010-10-18 06:49:12 +00:00
c103c668ce
Lift arg promotion from the X86 backend. This should be unified at some point.
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llvm-svn: 116694
2010-10-18 02:17:53 +00:00
a8a9f3c52b
Now that we handle all allocas via a non-SP reg offset remove all of the
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special case handling for ARM::SP.
llvm-svn: 116688
2010-10-17 11:08:44 +00:00
730764da62
Allow more load types to be materialized through the allocas.
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llvm-svn: 116683
2010-10-17 06:07:26 +00:00
d265b3fcfe
Optimize GEP off of intermediate allocas.
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llvm-svn: 116681
2010-10-17 01:51:42 +00:00
a0b9c2e9c0
Fix comment.
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llvm-svn: 116680
2010-10-17 01:42:53 +00:00
abc3a9d34b
Turn on AddOperator folding in GEP.
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llvm-svn: 116679
2010-10-17 01:41:46 +00:00
947e422c46
Use the i12 immediate versions of the load instructions - they're handled
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more in the post-passes.
llvm-svn: 116678
2010-10-17 01:40:27 +00:00
c918d550b6
Fix some funky formatting that got through.
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llvm-svn: 116653
2010-10-16 01:10:35 +00:00
Eric Christopher