2bea69bf65
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC
...
llvm-svn: 367633
2019-08-01 23:27:28 +00:00
57495268ac
AMDGPU/GlobalISel: Remove manual store select code
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This regresses the weird types that are newly treated as legal load
types, but fixes incorrectly using flat instrucions on SI.
llvm-svn: 367512
2019-08-01 03:52:40 +00:00
26cb53b260
AMDGPU/GlobalISel: Handle G_ATOMICRMW_FADD
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llvm-svn: 367509
2019-08-01 03:33:15 +00:00
da5b9bfa95
AMDGPU/GlobalISel: Allow selection of DS atomicrmw
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llvm-svn: 367507
2019-08-01 03:29:01 +00:00
3baf4d3418
AMDGPU/GlobalISel: Select simple local stores
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llvm-svn: 367504
2019-08-01 03:09:15 +00:00
3594011de0
AMDGPU/GlobalISel: Select local loads
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llvm-svn: 367498
2019-08-01 00:53:38 +00:00
0e7d8698b5
AMDGPU/GlobalISel: Don't assume instruction can be erased when selecting exts
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The G_ANYEXT handling can end up reaching selectCOPY, which mutates
the instruction in place.
llvm-svn: 366915
2019-07-24 16:05:53 +00:00
937d0ee5d8
AMDGPU/GlobalISel: Remove unnecessary code
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The minnum/maxnum case are dead, and the cvt is handled by the
default.
llvm-svn: 366685
2019-07-22 13:05:25 +00:00
7161fb0be5
AMDGPU/GlobalISel: Select private loads
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llvm-svn: 366248
2019-07-16 19:22:21 +00:00
dad1f89210
AMDGPU/GlobalISel: Select flat stores
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llvm-svn: 366246
2019-07-16 18:42:53 +00:00
35c96598b1
AMDGPU/GlobalISel: Select flat loads
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Now that the patterns use the new PatFrag address space support, the
only blocker to importing most load patterns is the addressing mode
complex patterns.
llvm-svn: 366237
2019-07-16 18:05:29 +00:00
22c4a147a9
AMDGPU/GlobalISel: Fix test failures in release build
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Apparently the check for legal instructions during instruction
select does not happen without an asserts build, so these would
successfully select in release, and fail in debug.
Make s16 and/or/xor legal. These can just be selected directly
to the 32-bit operation, as is already done in SelectionDAG, so just
make them legal.
llvm-svn: 366210
2019-07-16 14:28:30 +00:00
c8291c94f8
AMDGPU/GlobalISel: Select G_AND/G_OR/G_XOR
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llvm-svn: 366121
2019-07-15 19:50:07 +00:00
ad19b50c00
AMDGPU/GlobalISel: Don't constrain source register of VCC copies
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This is a hack until I come up with a better way of dealing with the
pseudo-register banks used for boolean values. If the use instruction
constrains the register, the selector for the def instruction won't
see that the bank was VCC. A 1-bit SReg_32 is could ambiguously have
been SCCRegBank or VCCRegBank in wave32.
This is necessary to successfully select branches with and and/or/xor
condition.
llvm-svn: 366120
2019-07-15 19:48:36 +00:00
e1b52f4180
AMDGPU/GlobalISel: Fix selecting vcc->vcc bank copies
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The extra test change is correct, although how it arrives there is a
bug that needs work. With wave32, the test for isVCC ambiguously
reports true for an SCC or VCC source. A new allocatable pseudo
register class for SCC may be necesssary.
llvm-svn: 366119
2019-07-15 19:46:48 +00:00
3bfdb54d88
AMDGPU/GlobalISel: Fix not constraining result reg of copies to VCC
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llvm-svn: 366118
2019-07-15 19:45:49 +00:00
18b7133843
AMDGPU/GlobalISel: Fix handling of sgpr (not scc bank) s1 to VCC
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This was emitting a copy from a 32-bit register to a 64-bit.
llvm-svn: 366117
2019-07-15 19:44:07 +00:00
5dfd466032
AMDGPU/GlobalISel: Fix G_ICMP for wave32
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llvm-svn: 366114
2019-07-15 19:39:31 +00:00
53fa759ff5
AMDGPU/GlobalISel: Handle llvm.amdgcn.if.break
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llvm-svn: 366102
2019-07-15 18:25:24 +00:00
b390121efb
AMDGPU/GlobalISel: Select llvm.amdgcn.end.cf
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llvm-svn: 366099
2019-07-15 18:18:46 +00:00
a65913e752
AMDGPU/GlobalISel: Select easy cases for G_BUILD_VECTOR
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llvm-svn: 366087
2019-07-15 17:26:43 +00:00
e6d10f97dd
AMDGPU/GlobalISel: Select G_SUB
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llvm-svn: 365484
2019-07-09 14:05:11 +00:00
872f38be7e
AMDGPU/GlobalISel: Select G_UNMERGE_VALUES
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llvm-svn: 365483
2019-07-09 14:02:26 +00:00
9b7ffc4e55
AMDGPU/GlobalISel: Select G_MERGE_VALUES
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llvm-svn: 365482
2019-07-09 14:02:20 +00:00
50be3481d4
AMDGPU/GlobalISel: Try generated matcher with intrinsics
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llvm-svn: 364933
2019-07-02 14:52:16 +00:00
70a4d3f67c
AMDGPU/GlobalISel: Fix G_GEP with mixed SGPR/VGPR operands
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The register bank for the destination of the sample argument copy was
wrong. We shouldn't be constraining each source to the result register
bank. Allow constraining the original register to the right size.
llvm-svn: 364928
2019-07-02 14:40:22 +00:00
ed63399244
AMDGPU/GlobalISel: Select G_FENCE
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Manually select to workaround tablegen emitter emitting checks for
G_CONSTANT.
llvm-svn: 364927
2019-07-02 14:17:38 +00:00
9e8e8c60fa
AMDGPU/GlobalISel: Lower kernarg segment ptr intrinsics
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llvm-svn: 364835
2019-07-01 18:49:01 +00:00
a310727830
AMDGPU/GlobalISel: Fail instead of assert when selecting loads
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llvm-svn: 364807
2019-07-01 16:36:39 +00:00
0a52e9d026
AMDGPU/GlobalISel: Complete implementation of G_GEP
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Also works around tablegen defect in selecting add with unused carry,
but if we have to manually select GEP, might as well handle add
manually.
llvm-svn: 364806
2019-07-01 16:34:48 +00:00
e1006259d8
AMDGPU/GlobalISel: Select G_PHI
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llvm-svn: 364805
2019-07-01 16:32:47 +00:00
9e9dd30de3
AMDGPU/GlobalISel: Implement select for 32-bit G_ADD
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Reviewers: arsenm
Reviewed By: arsenm
Subscribers: hiraditya, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58804
llvm-svn: 364797
2019-07-01 16:09:33 +00:00
2ab25f9ceb
AMDGPU/GlobalISel: Select G_BRCOND for vcc
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llvm-svn: 364795
2019-07-01 16:06:02 +00:00
cda82f0bb6
AMDGPU/GlobalISel: Select G_FRAME_INDEX
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llvm-svn: 364789
2019-07-01 15:48:18 +00:00
fdf36729c7
AMDGPU/GlobalISel: Make s16 select legal
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This is easy to handle and avoids legalization artifacts which are
likely to obscure combines.
llvm-svn: 364787
2019-07-01 15:42:47 +00:00
6464280eb0
AMDGPU/GlobalISel: Select G_BRCOND for scc conditions
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llvm-svn: 364786
2019-07-01 15:39:27 +00:00
1daad91af6
AMDGPU/GlobalISel: Tolerate copies with no type set
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isVCC has the same bug, but isn't used in a context where it can cause
a problem.
llvm-svn: 364784
2019-07-01 15:23:04 +00:00
4f64ade04c
AMDGPU/GlobalISel: Select src modifiers
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llvm-svn: 364782
2019-07-01 15:18:56 +00:00
89fc8bcdd6
AMDGPU/GlobalISel: Fail on store to 32-bit address space
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llvm-svn: 364766
2019-07-01 13:37:39 +00:00
3b7668ae4b
AMDGPU/GlobalISel: Improve icmp selection coverage.
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Select s64 eq/ne scalar icmp.
llvm-svn: 364765
2019-07-01 13:34:26 +00:00
9f992c238a
AMDGPU/GlobalISel: Fix scc->vcc copy handling
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This was checking the size of the register with the value of the size,
which happens to be exec. Also fix assuming VCC is 64-bit to fix
wave32.
Also remove some untested handling for physical registers which is
skipped. This doesn't insert the V_CNDMASK_B32 if SCC is the physical
copy source. I'm not sure if this should be trying to handle this
special case instead of dealing with this in copyPhysReg.
llvm-svn: 364761
2019-07-01 13:22:07 +00:00
5dafcb9b11
AMDGPU/GlobalISel: Use and instead of BFE with inline immediate
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Zext from s1 is the only case where this should do anything with the
current legal extensions.
llvm-svn: 364760
2019-07-01 13:22:06 +00:00
d7ffa2a948
AMDGPU: Select G_SEXT/G_ZEXT/G_ANYEXT
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llvm-svn: 364308
2019-06-25 13:18:11 +00:00
dbb6c03175
AMDGPU/GlobalISel: Select G_TRUNC
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llvm-svn: 364215
2019-06-24 18:02:18 +00:00
f8a841b88e
AMDGPU/GlobalISel: Fix selecting G_IMPLICIT_DEF for s1
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Try to fail for scc, since I don't think that should ever be produced.
llvm-svn: 364199
2019-06-24 16:24:03 +00:00
fee1949b35
AMDGPU/GlobalISel: Account for multiple defs when finding intrinsic ID
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llvm-svn: 363578
2019-06-17 17:01:27 +00:00
8b1c53b528
AMDGPU/GlobalISel: Implement select for G_ICMP and G_SELECT
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Reviewers: arsenm
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60640
llvm-svn: 363576
2019-06-17 16:27:43 +00:00
a6322941ff
[AMDGPU] gfx1010 VMEM and SMEM implementation
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Differential Revision: https://reviews.llvm.org/D61330
llvm-svn: 359621
2019-04-30 22:08:23 +00:00
33634d1b25
AMDGPU/GlobalISel: Implement select for G_INSERT
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Re-commit r344310.
Reviewers: arsenm
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D53116
llvm-svn: 355159
2019-03-01 00:50:26 +00:00
41f32196a0
AMDGPU/GlobalISel: Implement select for G_EXTRACT
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Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D49714
llvm-svn: 355156
2019-02-28 23:37:48 +00:00
Daniel Sanders