2ca70df58b
Handle i32->f32 bitconvert results.
...
llvm-svn: 54315
2008-08-04 06:44:31 +00:00
77e3e86e70
Add atomic sub for other sizes
...
llvm-svn: 54314
2008-08-03 20:17:34 +00:00
796e9be3b1
Emit saveri with the correct operand order, patch by Richard Pennington!
...
llvm-svn: 54313
2008-08-03 18:16:14 +00:00
3e667cfe21
Fix PR2615
...
llvm-svn: 54312
2008-08-03 15:37:43 +00:00
3d4bdcc1a6
Improved asm inline for hi,lo results
...
Added hi,lo registers to be used,def implicitly. This provides better handle of
instructions which use hi/lo.
Fixes a small BranchAnalysis bug
llvm-svn: 54274
2008-08-02 19:42:36 +00:00
3397298b65
Apply the same pattern used in 'and' lowering for 'or'
...
llvm-svn: 54273
2008-08-02 19:37:33 +00:00
e4798c83d0
Expand fcopysign
...
llvm-svn: 54250
2008-07-31 18:50:54 +00:00
23471047be
Handle more SELECT corner cases considering legalize types, probabily wont work with
...
the default legalizer.
llvm-svn: 54249
2008-07-31 18:31:28 +00:00
c31eb205c1
Add a flag to disable jump table generation (all
...
switches use the binary search algorithm) for
environments that don't support it. PPC64 JIT
is such an environment; turn the flag on for that.
llvm-svn: 54248
2008-07-31 18:13:12 +00:00
2d7ddea240
Added pattern for floating point zero immediate (avoiding a constant pool
...
access).
Added pattern to match bitconvert node.
Fixed MTC1 asm string bug.
llvm-svn: 54229
2008-07-30 19:00:31 +00:00
86b06335aa
Reapply r54147 with a constraint to only use the 8-bit
...
subreg form on x86-64, to avoid the problem with x86-32
having GPRs that don't have 8-bit subregs.
Also, change several 16-bit instructions to use
equivalent 32-bit instructions. These have a smaller
encoding and avoid partial-register updates.
llvm-svn: 54223
2008-07-30 18:09:17 +00:00
a950422221
Fixed bug in global address lowering for functions and in Brcond lowering
...
llvm-svn: 54215
2008-07-30 17:06:13 +00:00
57e17f0e14
Removed small section flag for mips, the assembler doesnt support this flag
...
llvm-svn: 54214
2008-07-30 17:04:04 +00:00
f714e25f7e
Added new features to represent specific instructions groups
...
llvm-svn: 54213
2008-07-30 17:01:06 +00:00
89e2b163fb
Instruction definition cleanup
...
llvm-svn: 54212
2008-07-30 16:58:59 +00:00
2a24157364
Changed some methods order.
...
llvm-svn: 54169
2008-07-29 19:29:50 +00:00
82f1925708
Fix broken CellSPU lowering, re-instate braces in Legalize
...
llvm-svn: 54168
2008-07-29 19:07:27 +00:00
e683bbabc7
Added floating point lowering for select.
...
llvm-svn: 54167
2008-07-29 19:05:28 +00:00
43105328d3
Revert 54147.
...
llvm-svn: 54148
2008-07-29 01:02:18 +00:00
26ec56c75c
Add x86 isel patterns to match what would be a ZERO_EXTEND_INREG operation,
...
which is represented in codegen as an 'and' operation. This matches them
with movz instructions, instead of leaving them to be matched by and
instructions with an immediate field.
llvm-svn: 54147
2008-07-28 22:18:25 +00:00
98bda587e1
Disable gp_rel relocation for constant pools access for now.
...
llvm-svn: 54142
2008-07-28 19:26:25 +00:00
87c83704d3
Since build_vector is a variadic node, the number
...
of operands should be -1 not 0.
llvm-svn: 54141
2008-07-28 19:17:21 +00:00
bcaf6e5243
Added floating point lowering for setcc and brcond.
...
Fixed COMM asm directive usage.
ConstantPool using custom FourByteConstantSection.
llvm-svn: 54139
2008-07-28 19:11:24 +00:00
d4c8cbd776
Remove <iostream> include.
...
llvm-svn: 54131
2008-07-27 23:18:30 +00:00
2ce6f2ad5e
Rename SDOperand to SDValue.
...
llvm-svn: 54128
2008-07-27 21:46:04 +00:00
91e5dcb680
Tidy SDNode::use_iterator, and complete the transition to have it
...
parallel its analogue, Value::value_use_iterator. The operator* method
now returns the user, rather than the use.
llvm-svn: 54127
2008-07-27 20:43:25 +00:00
283b2da27a
Disable mov{L, LP, HP, HLP, *DUP} shuffles for mmx
...
mmx needs its own fancy shuffle logic based on unpack; for now we get correct but awful code.
Also commit Mon Ping's VSETCC patch
llvm-svn: 54039
2008-07-25 19:05:58 +00:00
6559ada908
Fit in 80 cols
...
llvm-svn: 54029
2008-07-25 17:34:41 +00:00
628ab8c673
Remove dead PatLeaf; there are a number of issues around MMX movl that need to be fixed.
...
llvm-svn: 54026
2008-07-25 17:25:04 +00:00
c90a11256e
Teach ARM isLegalAddressingMode to handle unknown type without crashing. This fixes pr2589.
...
llvm-svn: 54004
2008-07-25 00:55:17 +00:00
f29c5279e9
Avoid emitting casts in static initializer contexts. This fixes
...
large numbers of CBE regressions caused by r53958.
llvm-svn: 53990
2008-07-24 17:57:48 +00:00
0f0aee213f
Fix a catastrophic PPC64 ABI bug: i32 operands which are passed in memory (all of the parameter registers are used) are loaded from sp offsets that were off by 4.
...
llvm-svn: 53979
2008-07-24 08:17:07 +00:00
ae187c6eba
Use C99 aggregate literal syntax for first-class struct and array values.
...
This fixes several recent CBE regressions.
llvm-svn: 53958
2008-07-23 18:41:03 +00:00
fdb4cec2fe
Minor fixes.
...
Added ConstantPool support.
llvm-svn: 53951
2008-07-23 16:01:50 +00:00
fa1211f69b
Enable first-class aggregates support.
...
Remove the GetResultInst instruction. It is still accepted in LLVM assembly
and bitcode, where it is now auto-upgraded to ExtractValueInst. Also, remove
support for return instructions with multiple values. These are auto-upgraded
to use InsertValueInst instructions.
The IRBuilder still accepts multiple-value returns, and auto-upgrades them
to InsertValueInst instructions.
llvm-svn: 53941
2008-07-23 00:34:11 +00:00
a2b4b4ad99
Fix PR2485: do all 4-element SSE shuffles in max. of 2 shuffle instructions.
...
Based on patch by Nicolas Capens.
llvm-svn: 53939
2008-07-23 00:22:17 +00:00
0c23ed6364
Factor out SSE 4 wide shuffle lowering code into its own function. No functionality changes.
...
llvm-svn: 53933
2008-07-22 21:13:36 +00:00
0384670141
Fix PR2574: implement v2f32 scalar_to_vector.
...
llvm-svn: 53927
2008-07-22 18:39:19 +00:00
4fdeb9b2d3
Provide default implementation of different small-sections related stuff
...
llvm-svn: 53920
2008-07-22 17:09:59 +00:00
4a4484ee97
Tie small stuff to non-small by default on ELF platforms
...
llvm-svn: 53919
2008-07-22 17:09:41 +00:00
19b7f815a0
simplified small section logic
...
llvm-svn: 53912
2008-07-22 16:24:21 +00:00
2d29ee06cd
Fix encoding of atomic compare and swap for i64
...
llvm-svn: 53911
2008-07-22 16:22:48 +00:00
a380798988
Added small section asm emition logic for mips.
...
Fixed small bug.
llvm-svn: 53908
2008-07-22 15:34:27 +00:00
9cfd2f8e57
Basic support for small sections
...
llvm-svn: 53907
2008-07-22 15:26:53 +00:00
a6ac974bd1
Remove another tab.
...
llvm-svn: 53904
2008-07-22 08:54:38 +00:00
b83a9ee320
More tab removals.
...
llvm-svn: 53903
2008-07-22 08:50:44 +00:00
e343021fbd
Fix a typo in a comment.
...
llvm-svn: 53894
2008-07-22 00:52:04 +00:00
fa374ca223
Eliminate a compilation warning.
...
llvm-svn: 53873
2008-07-21 20:02:45 +00:00
581cc87f57
Add titles to the various SelectionDAG viewGraph calls
...
that include useful information like the name of the
block being viewed and the current phase of compilation.
llvm-svn: 53872
2008-07-21 20:00:07 +00:00
e5d1fcfe4e
Added initial support for small sections on Mips.
...
Added gp_rel relocations to support addressing small section contents.
Added command line to specify small section threshold in bytes.
llvm-svn: 53869
2008-07-21 18:52:34 +00:00
Bruno Cardoso Lopes