b28e691657
simplify and tidy up
...
llvm-svn: 119066
2010-11-14 20:31:06 +00:00
ca21cd749e
Simplify and clean up MC symbol lookup for ARM constant pool values. This fixes
...
double quoting of ObjC symbol names in constant pool entries.
rdar://8652107
llvm-svn: 118688
2010-11-10 17:59:10 +00:00
f23b2d9d8d
Update ARMConstantPoolValue to not use a modifier string. Use an explicit
...
VariantKind marker to indicate the additional information necessary. Update
MC to handle the new Kinds. rdar://8647623
llvm-svn: 118671
2010-11-10 03:26:07 +00:00
a942ad4222
Change the ARMConstantPoolValue modifier string to an enumeration. This will
...
help in MC'izing the references that use them.
llvm-svn: 118633
2010-11-09 21:36:17 +00:00
2fd4c37d8b
Handle ARM constant pool values that need an explicit reference to the '.'
...
pseudo-label. (TLS stuff).
llvm-svn: 118609
2010-11-09 19:40:22 +00:00
38f8e76e51
Further MCize ARM constant pool values. This allows basic PIC references for
...
object file emission.
llvm-svn: 118601
2010-11-09 18:45:04 +00:00
0ef474730f
Revert 118422 in search of bot verdancy.
...
llvm-svn: 118429
2010-11-08 19:17:22 +00:00
f3e224f830
Support -mcpu=cortex-a8 in ARM attributes - Has Fixme. 1 Test modified.
...
llvm-svn: 118422
2010-11-08 17:58:07 +00:00
5a2c68d308
MC'ize the '.code 16' and '.thumb_func' ARM directives.
...
llvm-svn: 118301
2010-11-05 22:08:08 +00:00
ff9e507d8e
MC'ize simple ARMConstantValue entry emission (with a FIXME).
...
llvm-svn: 118295
2010-11-05 20:34:24 +00:00
1df82e67d1
Add FIXME.
...
llvm-svn: 118280
2010-11-05 17:37:13 +00:00
4a0c2d73c3
Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it in
...
the ARMExpandPseudos pass rather than during the asm lowering.
llvm-svn: 117714
2010-10-29 21:35:25 +00:00
e477b1ad30
ARM::MOVi32imm is expanded in ARMExpandPseudoInsts, so there's no need to
...
handle it in the asm lowering.
llvm-svn: 117707
2010-10-29 20:37:06 +00:00
338de3ee56
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
...
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752
llvm-svn: 117505
2010-10-27 23:12:14 +00:00
5a7c715470
Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on
...
rdar://8477752.
llvm-svn: 117419
2010-10-27 00:19:44 +00:00
1e4d9a17c2
First part of refactoring ARM addrmode2 (load/store) instructions to be more
...
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.
llvm-svn: 117409
2010-10-26 22:37:02 +00:00
d9d0c348df
Produce the headers directly in the Finish method. This allows us to use
...
the existing streamer methods that are endian safe.
llvm-svn: 117323
2010-10-25 22:26:55 +00:00
752913d6ba
Add a virtual destructor.
...
llvm-svn: 117280
2010-10-25 18:38:32 +00:00
0ed1543d4e
Add support for emitting ARM file attributes.
...
llvm-svn: 117275
2010-10-25 17:50:35 +00:00
109ff296c8
Second set of ARM/MC/ELF changes.
...
Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)
llvm-svn: 116257
2010-10-11 23:01:44 +00:00
25cd3bfbd7
remove trailing whitespace
...
llvm-svn: 115860
2010-10-06 22:46:47 +00:00
bff84d418f
First in a sequence of ARM/MC/*ELF* specific work.
...
Lifted the EmitRawText calls to ARMAsmPrinter::emitAttribute()
Added ARMAsmPrinter::emitAttributes() (plural s).
TODO:
.cpu attribute needs to be refactored
llvm-svn: 115859
2010-10-06 22:36:46 +00:00
f49540cb4f
Kill of the vestiges of the 'call' Modifier (no longer needed for PLT).
...
llvm-svn: 115845
2010-10-06 21:36:43 +00:00
2c95027258
Now that VDUPfqf and VDUPfdfare properly pseudos, kill the no-longer-needed
...
"lane" operand modifier.
llvm-svn: 115843
2010-10-06 21:22:32 +00:00
8025f89860
target operand flag values aren't a bitmask
...
llvm-svn: 115798
2010-10-06 16:51:55 +00:00
fae8305e2b
Nuke the rest of the :comment references
...
llvm-svn: 115373
2010-10-01 23:21:38 +00:00
0e854f3d43
Rename the AsmPrinter directory to InstPrinter for those targets that have
...
been MC-ized for assembly printing. MSP430 is mostly so, but still has the
asm printer and lowering code in the printer subdir for the moment.
llvm-svn: 115360
2010-10-01 22:39:28 +00:00
c8e2e9d830
Nuke a few more unused asm strings
...
llvm-svn: 115193
2010-09-30 19:53:58 +00:00
136ed51b08
80 column fix
...
llvm-svn: 115149
2010-09-30 15:25:22 +00:00
645f6c2bef
Tiny patch for proof-of-concept cleanup of ARMAsmPrinter::EmitStartOfAsmFile()
...
Small test for sanity check of resulting ARM .s file.
Tested against -r115129.
llvm-svn: 115133
2010-09-30 02:45:56 +00:00
080fdf4609
Nuke it from orbit. It's the only way to be sure.
...
(Kill the dead non-MC asm printer for the ARM target.)
llvm-svn: 115127
2010-09-30 01:57:53 +00:00
05eccf0e44
One Printer to rule them all, One Printer to find them,
...
One Printer to lower them all and in the back end bind them.
(Remove option to use the old non-MC asm printer.)
llvm-svn: 115038
2010-09-29 15:23:40 +00:00
45c83d496f
Factor out dbg_value comment printing and teach MC asm printing to use it.
...
This should make the arm-linux self-host buildbot happy again.
llvm-svn: 114964
2010-09-28 17:05:56 +00:00
175d6411c8
Enable the MC-ized ARM asm printer. Passing all local tests, so it's time to
...
enable it for real. Leaving the CL option in place to it's easy to disable it
again if (when) testers find something I've missed.
llvm-svn: 114915
2010-09-27 22:28:11 +00:00
9e9ed98305
ARM-mode eh.sjlj.longjmp MC lowering
...
llvm-svn: 114896
2010-09-27 21:47:04 +00:00
11fed543c9
Enable the MC-ized ARM asm printer. Passing all local tests, so it's time to
...
enable it for real. Leaving the CL option in place to it's easy to disable it
again if (when) testers find something I've missed.
llvm-svn: 114892
2010-09-27 21:28:44 +00:00
4a6ab13fb9
Add ARM explicit MCInst lowering for the Thumb eh.sjlj.setjmp sequence.
...
llvm-svn: 114758
2010-09-24 20:47:58 +00:00
c0aed7179a
ARM-mode eh.sjlj.setjmp pseudo MC-inst lowering expansion
...
llvm-svn: 114707
2010-09-23 23:33:56 +00:00
7d34837676
never mind. I can't read, apparently
...
llvm-svn: 114689
2010-09-23 19:42:17 +00:00
836341a17a
Fix opcode value for the 'trap' instruction, keeping the type suffix on the
...
constant. Hopefully the non-Darwin bots will like it...
llvm-svn: 114687
2010-09-23 19:32:40 +00:00
3d50a3e237
explicit 'unsigned long' on constant value. Hopefully make bots happier.
...
llvm-svn: 114686
2010-09-23 19:08:04 +00:00
e38495dbc0
Unbreak build. Jim, please review.
...
llvm-svn: 114684
2010-09-23 18:57:26 +00:00
8503054410
Clean up the 'trap' instruction printing a bit. Non-Darwin assemblers don't
...
(yet) recognize the 'trap' mnemonic, so we use .short/.long to emit the
opcode directly. On Darwin, however, we do want the mnemonic for more
readable assembly code and better disassembly.
Adjust the .td file to use the 'trap' mnemonic and handle using the binutils
workaround in the assembly printer. Also tweak the formatting of the opcode
values to make them consistent between the MC printer and the old printer.
llvm-svn: 114679
2010-09-23 18:05:37 +00:00
1f57cc4a59
add FIXME
...
llvm-svn: 114578
2010-09-22 20:55:15 +00:00
284eebc1ae
Add MC instruction printer support for ARM and Thumb1 jump tables.
...
llvm-svn: 114555
2010-09-22 17:39:48 +00:00
1573b29ea7
Add MC instruction printer support for TB[BH] style thumb2 jump tables.
...
llvm-svn: 114553
2010-09-22 17:15:35 +00:00
754e1efffc
Clean up comment.
...
llvm-svn: 114550
2010-09-22 16:45:13 +00:00
d64f9b8381
Add start of support for MC instruction printer of ARM jump tables. Filling in
...
the rest of it is next up.
llvm-svn: 114500
2010-09-21 23:28:16 +00:00
cbac342e1a
Fix errant printing of [v]ldm instructions that aren't a pop
...
llvm-svn: 114445
2010-09-21 16:45:31 +00:00
af5d63583e
factor out a simple helper function to create a label for PC-relative
...
instructions (PICADD, PICLDR, et.al.)
llvm-svn: 114243
2010-09-18 00:05:05 +00:00
3d97920829
Add MC-inst handling for tPICADD
...
llvm-svn: 114237
2010-09-17 23:41:53 +00:00
7a6c37d3e7
Teach the (non-MC) instruction printer to use the cannonical names for push/pop,
...
and shift instructions on ARM. Update the tests to match.
llvm-svn: 114230
2010-09-17 22:36:38 +00:00
132a0ce787
Hook up verbose asm comment printing for SOImm operands in MC printer
...
llvm-svn: 114215
2010-09-17 21:33:25 +00:00
0d35df1cfe
handle the upper16/lower16 target operand flags on symbol references for MC
...
instruction lowering.
llvm-svn: 114191
2010-09-17 18:25:25 +00:00
a7d430b51c
expand PICLDR MC lowering to handle other PICLDR and PICSTR versions.
...
llvm-svn: 114183
2010-09-17 16:25:52 +00:00
218e22da8b
MC-ization of the PICLDR pseudo. Next up, adding the other variants
...
(PICLDRB, et. al.) and PICSTR*
llvm-svn: 114098
2010-09-16 17:43:25 +00:00
a625b0110b
Remove support for "dregpair" operand modifier, now that it is no longer being
...
used for anything.
llvm-svn: 114067
2010-09-16 04:55:00 +00:00
40e85fbf17
move getRegisterNumbering() to out of ARMBaseRegisterInfo into the helper
...
functions in ARMBaseInfo.h so it can be used in the MC library as well.
For anything bigger than this, we may want a means to have a small support
library for shared helper functions like this. Cross that bridge when we
come to it.
llvm-svn: 114016
2010-09-15 20:26:25 +00:00
a244f70113
Add predicate and 's' bit operands to PICADD instruction lowering.
...
llvm-svn: 113860
2010-09-14 21:28:17 +00:00
7ae94222cd
fix comment typo
...
llvm-svn: 113856
2010-09-14 21:05:34 +00:00
8ee5cd99ef
Remove trailing whitespace
...
llvm-svn: 112790
2010-09-02 01:02:06 +00:00
13ce07fa92
Change ARM VFP VLDM/VSTM instructions to use addressing mode #4 , just like
...
all the other LDM/STM instructions. This fixes asm printer crashes when
compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run
with -O0 to check this in the future.
Prior to this change VLDM/VSTM used addressing mode #5 , but not really.
The offset field was used to hold a count of the number of registers being
loaded or stored, and the AM5 opcode field was expanded to specify the IA
or DB mode, instead of the standard ADD/SUB specifier. Much of the backend
was not aware of these special cases. The crashes occured when rewriting
a frameindex caused the AM5 offset field to be changed so that it did not
have a valid submode. I don't know exactly what changed to expose this now.
Maybe we've never done much with -O0 and NEON. Regardless, there's no longer
any reason to keep a count of the VLDM/VSTM registers, so we can use
addressing mode #4 and clean things up in a lot of places.
llvm-svn: 112322
2010-08-27 23:18:17 +00:00
481d7a9ab4
Rename sat_shift operand to shift_imm, in preparation for using it for other
...
instructions besides saturate instructions. No functional changes.
llvm-svn: 111168
2010-08-16 18:27:34 +00:00
8e8f1c133a
Cleaned up the for-disassembly-only entries in the arm instruction table so that
...
the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.
llvm-svn: 110951
2010-08-12 20:46:17 +00:00
add513112a
Move the ARM SSAT and USAT optional shift amount operand out of the
...
instruction opcode. This also fixes part of PR7792.
llvm-svn: 110875
2010-08-11 23:10:46 +00:00
97886d59d1
ARM "rrx" shift operands do not have an immediate. PR7790.
...
llvm-svn: 110292
2010-08-05 00:34:42 +00:00
a52ddc496a
Implement target specific getDebugValueLocation().
...
llvm-svn: 110267
2010-08-04 22:39:39 +00:00
b128824b60
Move newlines before inline jumptables from the asm strings in .td files to
...
the jtblock_operand print methods. This avoids extra newlines in the
disassembler's output. PR7757.
llvm-svn: 109948
2010-07-31 06:28:10 +00:00
4320e2d1bb
Add the __TEXT,__StaticInit section to the list of sections emitted at the
...
beginning on ARM Darwin assembly files so that it won't be placed after
debug sections. Radar 8252813.
llvm-svn: 109879
2010-07-30 19:55:47 +00:00
965a73a28c
For ARM/Darwin, add a dwarf entry indicating whether a function is arm or thumb
...
rdar://8202967
llvm-svn: 109057
2010-07-21 23:03:52 +00:00
b792b463af
sink the arm implementations of ASmPrinter and MCInstLower
...
out of the AsmPrinter directory into libarm. Now the
ARM InstPrinters depend jsut on the MC stuff, not on vmcore
or codegen.
llvm-svn: 108783
2010-07-19 23:44:46 +00:00
17d28de8ac
Move ARM to pluggable asmprinter
...
llvm-svn: 54889
2008-08-17 13:55:10 +00:00
ed47329174
Handle visibility printing with all generality. Remove bunch of duplicate code.
...
llvm-svn: 54540
2008-08-08 18:25:07 +00:00
df8c7faf60
Undo most of r54519.
...
llvm-svn: 54534
2008-08-08 17:56:50 +00:00
655fa0fec4
It's not legal to output a GV in a coalesced section if it's used in an ARM PIC relative constantpool.
...
llvm-svn: 54519
2008-08-08 06:56:16 +00:00
04083529df
Switch ARM to new section handling stuff
...
llvm-svn: 54458
2008-08-07 09:54:23 +00:00
c4650f4b56
Emit debug info for data-only files. ARM version.
...
llvm-svn: 53360
2008-07-09 21:20:54 +00:00
49c8e68e4c
Back out 53254. It broke ppc debug info codegen.
...
llvm-svn: 53280
2008-07-09 06:36:53 +00:00
b9097a71d4
Make debug info come out in data-only files.
...
This is a question of the debugging setup code not
being called at the right time, and it's called from
target-dependent code for some reason. I have only
attempted to fix Darwin, but I'm pretty sure it's
broken elsewhere; I'll leave that to people who can
test it.
llvm-svn: 53254
2008-07-08 21:56:22 +00:00
c7fc432b19
Minor const-correctness fixes.
...
llvm-svn: 53196
2008-07-07 20:06:06 +00:00
5bf742f2aa
Handle quoted names when constructing $stub's,
...
$non_lazy_ptr's and $lazy_ptr's.
llvm-svn: 51277
2008-05-19 21:38:18 +00:00
c799065cc3
Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to 16-byte boundaries.
...
llvm-svn: 47703
2008-02-28 00:43:03 +00:00
c24ea4fb41
Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool
...
would have been a Godsend here!
llvm-svn: 47625
2008-02-26 21:11:01 +00:00
7b1431785b
Handle \n's in value names for more targets. The asm printers
...
really really really need refactoring :(
llvm-svn: 47171
2008-02-15 19:04:54 +00:00
ffde4ff5b1
__DATA not __DATA__ is the right segment name on darwin.
...
Spotted by Nick Kledzik.
llvm-svn: 47037
2008-02-12 23:35:09 +00:00
3a4be0fdef
Rename MRegisterInfo to TargetRegisterInfo.
...
llvm-svn: 46930
2008-02-10 18:45:23 +00:00
32e5347eb8
Get rid of the annoying blank lines before labels.
...
llvm-svn: 46667
2008-02-02 08:39:46 +00:00
96a1b810ec
If the function has no machine instructions, then emit a "nop" so that
...
the function label isn't associated with something it shouldn't be.
llvm-svn: 46449
2008-01-28 09:15:03 +00:00
7f1ff5fedd
Honor explicit section information on Darwin.
...
llvm-svn: 46267
2008-01-23 00:58:14 +00:00
8ef89eabc2
Revert the part of 45849 that treated weak globals
...
as weak globals rather than commons. While not wrong,
this change tickled a latent bug in Darwin's strip,
so revert it for now as a workaround.
llvm-svn: 46147
2008-01-17 23:36:04 +00:00
193daf0698
Weak zeroes don't go in bss on Darwin.
...
llvm-svn: 45849
2008-01-11 01:59:45 +00:00
a5bb370aa4
Add new shorter predicates for testing machine operands for various types:
...
e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on
switching everything over, so new clients should just start using the
shorter names.
Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(),
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.
llvm-svn: 45464
2007-12-30 23:10:15 +00:00
5c4637816e
Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
...
llvm-svn: 45453
2007-12-30 20:49:49 +00:00
f3ebc3f3d2
Remove attribution from file headers, per discussion on llvmdev.
...
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
797d56ff17
Much improved pic jumptable codegen:
...
Then:
call "L1$pb"
"L1$pb":
popl %eax
...
LBB1_1: # entry
imull $4, %ecx, %ecx
leal LJTI1_0-"L1$pb"(%eax), %edx
addl LJTI1_0-"L1$pb"(%ecx,%eax), %edx
jmpl *%edx
.align 2
.set L1_0_set_3,LBB1_3-LJTI1_0
.set L1_0_set_2,LBB1_2-LJTI1_0
.set L1_0_set_5,LBB1_5-LJTI1_0
.set L1_0_set_4,LBB1_4-LJTI1_0
LJTI1_0:
.long L1_0_set_3
.long L1_0_set_2
Now:
call "L1$pb"
"L1$pb":
popl %eax
...
LBB1_1: # entry
addl LJTI1_0-"L1$pb"(%eax,%ecx,4), %eax
jmpl *%eax
.align 2
.set L1_0_set_3,LBB1_3-"L1$pb"
.set L1_0_set_2,LBB1_2-"L1$pb"
.set L1_0_set_5,LBB1_5-"L1$pb"
.set L1_0_set_4,LBB1_4-"L1$pb"
LJTI1_0:
.long L1_0_set_3
.long L1_0_set_2
llvm-svn: 43924
2007-11-09 01:32:10 +00:00
1a30c18e88
[ARM] Fix code generation for:
...
static __thread struct {
int a;
int b;
} teste = {0, 0};
llvm-svn: 43722
2007-11-05 18:33:37 +00:00
283207a71c
Eliminate the remaining uses of getTypeSize. This
...
should only effect x86 when using long double. Now
12/16 bytes are output for long double globals (the
exact amount depends on the alignment). This brings
globals in line with the rest of LLVM: the space
reserved for an object is now always the ABI size.
One tricky point is that only 10 bytes should be
output for long double if it is a field in a packed
struct, which is the reason for the additional
argument to EmitGlobalConstant.
llvm-svn: 43688
2007-11-05 00:04:43 +00:00
cdf3609130
Revert 42908 for now.
...
llvm-svn: 42960
2007-10-14 05:57:21 +00:00
dc35bd79ca
Change the names used for internal labels to use the current
...
function symbol name instead of a codegen-assigned function
number.
Thanks Evan! :-)
llvm-svn: 42908
2007-10-12 14:53:36 +00:00
c731c97fac
Use empty() member functions when that's what's being tested for instead
...
of comparing begin() and end().
llvm-svn: 42585
2007-10-03 19:26:29 +00:00
Chris Lattner