77ad1dc56d
Rename the narrow shift right immediate operands to "shr_imm*" operands. Also
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expand the testing of the narrowing shift right instructions.
No functionality change.
llvm-svn: 127193
2011-03-07 23:38:41 +00:00
3b1459b810
Narrow right shifts need to encode their immediates differently from a normal
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shift.
16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>
llvm-svn: 126723
2011-03-01 01:00:59 +00:00
4ebf471c9b
Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being.
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llvm-svn: 125127
2011-02-08 22:39:40 +00:00
d2e2f56c36
Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps.
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(yes, this is different from R_ARM_CALL)
- Adds a new method getARMBranchTargetOpValue() which handles the
necessary distinction between the conditional and unconditional br/bl
needed for ARM/ELF
At least for ARM mode, the needed fixup for conditional versus unconditional
br/bl is identical, but the ARM docs and existing ARM tools expect this
reloc type...
Added a few FIXME's for future naming fixups in ARMInstrInfo.td
llvm-svn: 124895
2011-02-04 19:47:15 +00:00
7f639c11d7
Add support for parsing and encoding ARM's official syntax for the BFI instruction
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llvm-svn: 123770
2011-01-18 20:45:56 +00:00
d4a5c05c97
Completed :lower16: / :upper16: support for movw / movt pairs on Darwin.
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- Fixed :upper16: fix up routine. It should be shifting down the top 16 bits first.
- Added support for Thumb2 :lower16: and :upper16: fix up.
- Added :upper16: and :lower16: relocation support to mach-o object writer.
llvm-svn: 123424
2011-01-14 02:38:49 +00:00
965b3c7323
Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step
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in the right direction. It eliminated some hacks and will unblock codegen
work. But it's far from being done. It doesn't reject illegal expressions,
e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all.
llvm-svn: 123369
2011-01-13 07:58:56 +00:00
3077bb64e9
Mostly undo r123297, but move the default case in EvaluateAsPCRel to the top
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of the switch block to appease GCC.
llvm-svn: 123317
2011-01-12 18:02:55 +00:00
ea43172297
Prefer llvm_unreachable to assert(0)
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llvm-svn: 123297
2011-01-12 01:42:42 +00:00
9c5b65d289
1. Support ELF pcrel relocations for movw/movt:
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R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC.
2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum.
3. Add support for 3 new elf section types (no-ops)
llvm-svn: 123294
2011-01-12 00:19:25 +00:00
0c9d9fdd81
MC: Move target specific fixup info descriptors to TargetAsmBackend instead of
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the MCCodeEmitter, which seems like a better organization.
- Also, cleaned up some magic constants while in the area.
llvm-svn: 121953
2010-12-16 03:20:06 +00:00
e9afc740a8
Delete an extra "Imm5 = ", caught by GCC's -Wsequence-point but not by Clang
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(see PR4579).
llvm-svn: 121939
2010-12-16 01:34:26 +00:00
9613a09e5c
Remove fixup_arm_thumb_ldst. The code was never calling the "fixup" stuff for
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it. I.e., it was always an immediate value.
llvm-svn: 121932
2010-12-16 00:50:33 +00:00
7d3bde98f1
If we're changing the frame register to a physical register other than SP, we
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need to use tLDRi and tSTRi instead of tLDRspi and tSTRspi respectively.
llvm-svn: 121915
2010-12-15 23:32:27 +00:00
622ad5170b
Implement cleanups suggested by Daniel.
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llvm-svn: 121875
2010-12-15 18:48:27 +00:00
03e7576dee
Add fixups for Thumb LDR/STR instructions.
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llvm-svn: 121858
2010-12-15 08:51:02 +00:00
eda5177ca6
thumb adr fixup needs alignment just like the t2 version.
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llvm-svn: 121812
2010-12-14 23:47:35 +00:00
509dc2a700
Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755
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llvm-svn: 121798
2010-12-14 22:28:03 +00:00
a9b9300bb8
MC/ARM: Fix-up fixup offset for fixup_arm_branch target specific fixup.
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llvm-svn: 121772
2010-12-14 17:37:16 +00:00
092a7bdf9f
The tLDR et al instructions were emitting either a reg/reg or reg/imm
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instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.
The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.
There are some obvious cleanups here, which will happen shortly.
llvm-svn: 121747
2010-12-14 03:36:38 +00:00
6d375e5637
Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering much later, which makes the entire
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process cleaner.
llvm-svn: 121735
2010-12-14 00:36:49 +00:00
9a4d42855d
Revert r121721, which broke buildbots.
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llvm-svn: 121726
2010-12-13 22:51:08 +00:00
4efa445f3c
Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. Provide correct fixups for Thumb2 ADR,
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which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup.
llvm-svn: 121721
2010-12-13 22:29:52 +00:00
578074b2f3
In Thumb2, direct branches can be encoded as either a "short" conditional branch with a null predicate, or
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as a "long" direct branch. While the mnemonics are the same, they encode the branch offset differently, and
the Darwin assembler appears to prefer the "long" form for direct branches. Thus, in the name of bitwise
equivalence, provide encoding and fixup support for it.
llvm-svn: 121710
2010-12-13 19:31:11 +00:00
aecdd871da
Add FIXME
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llvm-svn: 121598
2010-12-10 23:41:10 +00:00
235c276442
Attempt to get Thumb2 branch fixups working properly.
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llvm-svn: 121593
2010-12-10 23:02:28 +00:00
7cdd232895
Fix merge error in my last fix to Thumb2 vldr fixups.
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llvm-svn: 121588
2010-12-10 22:53:48 +00:00
4743d75640
Fixups for Thumb2 vldr's need to have the effective PC aligned as well.
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llvm-svn: 121587
2010-12-10 22:46:47 +00:00
006ab13b59
The MCFixupKindInfo table needs to be in the order that the enums were
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declared. Add a note specifying this and spruce up the list a bit.
llvm-svn: 121586
2010-12-10 22:37:19 +00:00
b0fa127f60
Fix encoding of Thumb1 LDRB and STRB.
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llvm-svn: 121581
2010-12-10 22:11:13 +00:00
c4a0c29edb
Trailing whitespace.
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llvm-svn: 121580
2010-12-10 21:57:34 +00:00
e69f724935
Fix encoding of 'U' bit for Thumb2 STRD/LDRD instructions. rdar://8755726
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llvm-svn: 121524
2010-12-10 21:05:07 +00:00
e119da1146
Thumb unconditional branch binary encoding. rdar://8754994
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llvm-svn: 121496
2010-12-10 18:21:33 +00:00
78485ad65e
Thumb conditional branch binary encodings. rdar://8745367
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llvm-svn: 121493
2010-12-10 17:13:40 +00:00
0c4838bab7
Thumb ldr reg+imm offsets were encoded incorrectly. The scaling factor of the
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t_addrmode_s# address modes is used for ASM printing, not for encoding.
<rdar://problem/8745375>
llvm-svn: 121417
2010-12-09 21:49:07 +00:00
cb4d8f2e74
Use the new IsAligned fixup flag to improve fixup encodings for Thumb2 branches. This is still not perfect,
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but it gets many more of them correct than it did previously.
llvm-svn: 121414
2010-12-09 21:34:47 +00:00
3ef19d9d48
Fix an issue in some Thumb fixups, where the effective PC address needs to be 4-byte aligned when calculating
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the offset. Add a new fixup flag to represent this, and use it for the one fixups that I have a testcase for needing
this. It's quite likely that the other Thumb fixups will need this too, and to have their fixup encoding logic
adjusted accordingly.
llvm-svn: 121408
2010-12-09 20:27:52 +00:00
68b27eb9d1
Rename CB/CBZ specific fixup accordingly.
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llvm-svn: 121404
2010-12-09 19:50:12 +00:00
62b68112da
Rename the encoder method for t_cbtarget to match.
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llvm-svn: 121399
2010-12-09 19:04:53 +00:00
3e6ee1db3e
Fix Thumb2 fixups for ldr.
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llvm-svn: 121350
2010-12-09 01:51:07 +00:00
3392bfc8f3
The BLX instruction is encoded differently than the BL, because why not? In
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particular, the immediate has 20-bits of value instead of 21. And bit 0 is '0'
always. Going through the BL fixup encoding was trashing the "bit 0 is '0'"
invariant.
Attempt to get the encoding at slightly more correct with this.
llvm-svn: 121336
2010-12-09 00:39:08 +00:00
302d5fd0d8
Fix Thumb2 BCC encoding and fixups.
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llvm-svn: 121329
2010-12-09 00:27:41 +00:00
a7d6aa902a
Support the "target" encodings for the CB[N]Z instructions.
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llvm-svn: 121308
2010-12-08 23:01:43 +00:00
8a6449c46e
Add support for loading from a constant pool.
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llvm-svn: 121226
2010-12-08 01:57:09 +00:00
0f7142d808
VLDR fixups need special handling under Thumb. While the encoding is the same,
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the order of the bytes in the data stream is flipped around.
llvm-svn: 121215
2010-12-08 00:18:36 +00:00
56de7c2773
Fix a warning about a variable which is only used in an assertion.
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llvm-svn: 121206
2010-12-07 23:26:21 +00:00
49bcd6ff85
Binary encoding for ARM tLDRspi and tSTRspi.
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llvm-svn: 121186
2010-12-07 21:50:47 +00:00
99ea8a3510
Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it.
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llvm-svn: 121082
2010-12-07 00:45:21 +00:00
9e1994698d
Add fixup for Thumb1 BL/BLX instructions.
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llvm-svn: 121072
2010-12-06 23:57:07 +00:00
567ebd0cb5
Encode the 32-bit wide Thumb (and Thumb2) instructions with the high order
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halfword being emitted to the stream first. rdar://8728174
llvm-svn: 120848
2010-12-03 22:31:40 +00:00
Bill Wendling