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Author SHA1 Message Date
Johnny Chen 57c892860e Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should 
print out ldr, not ldr.n.

rdar://problem/9267772

llvm-svn: 130008
 2011-04-22 19:12:43 +00:00
Chris Lattner 0ab5e2cded Fix a ton of comment typos found by codespell. Patch by 
Luis Felipe Strano Moraes!

llvm-svn: 129558
 2011-04-15 05:18:47 +00:00
Johnny Chen dc8bf9ec08 Thumb disassembler was erroneously rejecting "blx sp" instruction. 
rdar://problem/9267838

llvm-svn: 129320
 2011-04-11 23:33:30 +00:00
Johnny Chen 72f4a95144 delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 instructions, and add a test case for that. 
llvm-svn: 128249
 2011-03-25 00:17:42 +00:00
Johnny Chen ceef55466a The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been stale since 
the change to ("tLDMIA", "tLDMIA_UPD").  Update the conflict resolution code and add
test cases for that.

llvm-svn: 128247
 2011-03-24 23:42:31 +00:00
Johnny Chen 73193f2475 The ARM disassembler was confused with the 16-bit tSTMIA instruction. 
According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available.
Ignore tSTMIA for the decoder emitter and add a test case for that.

llvm-svn: 128246
 2011-03-24 23:21:14 +00:00
Johnny Chen 8bbc12824a ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled. 
Set the encoding bits to {0,?,?,0}, not 0.  Plus delegate the disassembly of ADR to
the more generic ADDri/SUBri instructions, and add a test case for that.

llvm-svn: 128234
 2011-03-24 20:42:48 +00:00
Jim Grosbach fcc34cacd9 Remove no-longer-correct special case for disasm of ARM BL instructions. 
llvm-svn: 127517
 2011-03-12 01:05:29 +00:00
Jim Grosbach f026d9ed53 Pseudo-ize the ARM 'B' instruction. 
llvm-svn: 127510
 2011-03-11 23:24:15 +00:00
Jim Grosbach 2fee5327aa Remove dead code. These ARM instruction definitions no longer exist. 
llvm-svn: 127509
 2011-03-11 23:15:02 +00:00
Jim Grosbach 376d5e8772 Remove dead code. These ARM instruction definitions no longer exist. 
llvm-svn: 127508
 2011-03-11 23:11:41 +00:00
Jim Grosbach bb0547d9c4 Pseudo-ize VMOVDcc and VMOVScc. 
llvm-svn: 127506
 2011-03-11 23:09:50 +00:00
Jim Grosbach 52594d99e4 Remove dead code. These ARM instruction definitions don't exist. 
llvm-svn: 127491
 2011-03-11 20:51:07 +00:00
Jim Grosbach 59eea670f8 ARM VDUPfd and VDUPfq can just be patterns. The instruction is the same 
as for VDUP32d and VDUP32q, respectively.

llvm-svn: 127489
 2011-03-11 20:44:08 +00:00
Jim Grosbach 6c609d626f Remove dead code. These ARM instruction definitions don't exist. 
llvm-svn: 127488
 2011-03-11 20:38:18 +00:00
Jim Grosbach c77dea7f55 ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q 
and VDUPLN32d, respectively.

llvm-svn: 127486
 2011-03-11 20:31:17 +00:00
Jim Grosbach 24fe5e36ea ARM VREV64df and VREV64qf can just be patterns. The instruction is the same 
as for VREV64d32 and VREV64q32, respectively.

llvm-svn: 127485
 2011-03-11 20:18:05 +00:00
Jim Grosbach d0fc231e13 Tidy up since ARM MOVCCi and MOVCCi16 are now pseudos. 
llvm-svn: 127445
 2011-03-11 01:16:49 +00:00
Jim Grosbach 62a7b473af Properly pseudo-ize MOVCCr and MOVCCs. 
llvm-svn: 127434
 2011-03-10 23:56:09 +00:00
Jim Grosbach a186cadcaa Memory barrier instructions don't need special handling in tblgen anymore. 
llvm-svn: 127419
 2011-03-10 19:05:48 +00:00
Bob Wilson 6f6d739b6e TableGen should not ignore BX instructions for the ARM disassembler. pr9368. 
llvm-svn: 126931
 2011-03-03 07:19:52 +00:00
Bob Wilson ec84568904 pr9367: Add missing predicated BLX instructions. 
Patch by Jyun-Yan You, with some minor adjustments and a testcase from me.

llvm-svn: 126915
 2011-03-03 01:41:01 +00:00
Owen Anderson 4e81890d36 Add FixedLenDecoderEmitter, the skeleton of a new disassembler emitter for fixed-length instruction encodings. 
A major part of its (eventual) goal is to support a much cleaner separation between disassembly callbacks
provided by the target and the disassembler emitter itself, i.e. not requiring hardcoding of knowledge in tblgen
like the existing disassembly emitters do.

The hope is that some day this will allow us to replace the existing non-Thumb ARM disassembler and remove
some of the hacks the old one introduced to tblgen.

llvm-svn: 125966
 2011-02-18 21:51:29 +00:00
Bruno Cardoso Lopes 7f639c11d7 Add support for parsing and encoding ARM's official syntax for the BFI instruction 
llvm-svn: 123770
 2011-01-18 20:45:56 +00:00
Jim Grosbach 509dc2a700 Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755 
llvm-svn: 121798
 2010-12-14 22:28:03 +00:00
Bob Wilson 651eaa02b8 Remove the rest of the *_sfp Neon instruction patterns. 
Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions.
This change made a big difference in the code generated for the
CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing
a fine job, but some instructions that were previously moved outside the loop
are not moved now.  It's using fewer VFP registers now, which is generally
a good thing, so I think the estimates for register pressure changed and that
affected the LICM behavior.  Since that isn't obviously wrong, I've just
changed the test file.  This completes the work for Radar 8711675.

llvm-svn: 121730
 2010-12-13 23:02:37 +00:00
Bill Wendling dc913e64d7 Merge DEBUG statements. 
llvm-svn: 121660
 2010-12-13 01:03:49 +00:00
Chris Lattner 77d369c8eb eliminate the Records global variable, patch by Garrison Venn! 
llvm-svn: 121659
 2010-12-13 00:23:57 +00:00
Jim Grosbach f878e62a0d Remove reference to the CMPz instruction patterns for ARM. 
llvm-svn: 121180
 2010-12-07 20:44:33 +00:00
Bill Wendling 4e7eb12f6f I did it wrong. Don't disregard these encodings here. 
llvm-svn: 120786
 2010-12-03 02:25:59 +00:00
Bill Wendling e38f1149fa Ignore decode table conflicts in the tMOVgpr2tgpr, tMOVgpr2gpr, and tMOVtgpr2gpr 
instructions. They are handled as special moves, but encoded as a normal move.

llvm-svn: 120779
 2010-12-03 01:55:30 +00:00
Jim Grosbach 8b16618685 The VLDMQ/VSTMQ instructions are reprented as true Pseudo-insts now (i.e., 
no extra encoding information), so we no longer need to special case them
here.

llvm-svn: 120444
 2010-11-30 19:08:32 +00:00
Jim Grosbach f01da1a7df Tidy up. 
llvm-svn: 120443
 2010-11-30 19:00:13 +00:00
Jim Grosbach 89a4795b52 Delete a few no longer needed references to pseudos. 
llvm-svn: 120441
 2010-11-30 18:56:13 +00:00
Jim Grosbach 7ec3d34553 Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw 
instructions. This simplifies instruction printing and disassembly.

llvm-svn: 120333
 2010-11-29 22:37:40 +00:00
Jim Grosbach 81af4f9eb1 Rename t2 TBB and TBH instructions to reference that they encode the jump table 
data. Next up, pseudo-izing them.

llvm-svn: 120320
 2010-11-29 21:28:32 +00:00
Michael J. Spencer 447762da85 Merge System into Support. 
llvm-svn: 120298
 2010-11-29 18:16:10 +00:00
Bill Wendling a68e3a5397 Encode the multi-load/store instructions with their respective modes ('ia', 
'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>

llvm-svn: 119310
 2010-11-16 01:16:36 +00:00
Chris Lattner d8adec70f3 factor the operand list (and related fields/operations) out of 
CodeGenInstruction into its own helper class.  No functionality change.

llvm-svn: 117893
 2010-11-01 04:03:32 +00:00
Jim Grosbach b75d0ca38e A few 80 column cleanups 
llvm-svn: 116069
 2010-10-08 18:13:57 +00:00
Jim Grosbach 33c1eb16e8 Move checking for t2MOVCCi16 to the right place. 
llvm-svn: 115994
 2010-10-07 22:14:01 +00:00
Nick Lewycky 1e00173d20 Fix typo in comment. 
llvm-svn: 115986
 2010-10-07 21:55:16 +00:00
Jim Grosbach 5b255c2dd6 Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode. 
llvm-svn: 115890
 2010-10-07 00:53:56 +00:00
Jim Grosbach 742adc328a Allow use of the 16-bit literal move instruction in CMOVs for ARM mode. 
llvm-svn: 115884
 2010-10-07 00:42:42 +00:00
Jim Grosbach b270f28c1a Now that VDUPfqf and VDUPfdfare properly pseudos, nuke the special handling. 
llvm-svn: 115841
 2010-10-06 21:17:07 +00:00
Bob Wilson aaff8f539a Fix a comment typo. 
llvm-svn: 112302
 2010-08-27 21:56:59 +00:00
Bob Wilson 9664984be8 Add a separate ARM instruction format for Saturate instructions. 
(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!!  Two of them were already out of sync.  I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.)  Add support for encoding these instructions.

llvm-svn: 110754
 2010-08-11 00:01:18 +00:00
Dale Johannesen e2289285ae Changes to ARM tail calls, mostly cosmetic. 
Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.

llvm-svn: 107851
 2010-07-08 01:18:23 +00:00
Dale Johannesen a06c2f79fc An attempt to fix the problem Anton reported with 
ARM tail calls.  Don't know if it works, but it
doesn't break Darwin.

llvm-svn: 106309
 2010-06-18 20:44:28 +00:00
Dale Johannesen 44f9dfc9cf Next round of tail call changes. Register used in a tail 
call must not be callee-saved; following x86, add a new
regclass to represent this.  Also fixes a couple of bugs.
Still disabled by default; Thumb doesn't work yet.

llvm-svn: 106053
 2010-06-15 22:08:33 +00:00