9eb62cd159
Delete unnecessarily cautious LastCALLSEQ code.
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llvm-svn: 136156
2011-07-26 22:00:59 +00:00
06b8b571b2
Add obvious missing case to switch. PR10497.
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llvm-svn: 136130
2011-07-26 20:38:49 +00:00
fee02c6c13
Initial implementation of 'fence' instruction, the new C++0x-style replacement for llvm.memory.barrier.
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This is just a LangRef entry and reading/writing/memory representation; optimizer+codegen support coming soon.
llvm-svn: 136009
2011-07-25 23:16:38 +00:00
cbd3ba91b7
Make sure this DAGCombine actually returns an UNDEF of the correct type; PR10476.
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llvm-svn: 135993
2011-07-25 22:25:42 +00:00
6ed783228d
PR10421: Fix a straightforward bug in the widening logic for CONCAT_VECTORS.
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llvm-svn: 135595
2011-07-20 18:14:33 +00:00
9ab3cac694
Revert r135423.
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llvm-svn: 135454
2011-07-19 00:28:24 +00:00
7a16288157
Add APInt(numBits, ArrayRef<uint64_t> bigVal) constructor to prevent future ambiguity
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errors like the one corrected by r135261. Migrate all LLVM callers of the old
constructor to the new one.
llvm-svn: 135431
2011-07-18 21:45:40 +00:00
4dc76f2438
During bottom up fast-isel, instructions emitted to materalize registers are at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases.
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[take 2]
llvm-svn: 135423
2011-07-18 20:55:23 +00:00
229907cd11
land David Blaikie's patch to de-constify Type, with a few tweaks.
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llvm-svn: 135375
2011-07-18 04:54:35 +00:00
76d51c6c89
Minor code cleanups
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llvm-svn: 135362
2011-07-17 19:05:00 +00:00
945864d6dc
LegalizeDAG doesn't need its own copy of this enum.
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llvm-svn: 135320
2011-07-15 22:51:43 +00:00
e49e74261a
Delete LegalizeDAG's own version of isTypeLegal and getTypeAction
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and just use the ones from TargetLowering directly.
llvm-svn: 135318
2011-07-15 22:39:09 +00:00
8c5ca645ce
Delete an unused variable and a redundant assert.
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llvm-svn: 135311
2011-07-15 22:19:02 +00:00
ad94608b1f
Modernize comments.
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llvm-svn: 135305
2011-07-15 21:42:20 +00:00
92464be28c
Check register class matching instead of width of type matching
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when determining validity of matching constraint. Allow i1
types access to the GR8 reg class for x86.
Fixes PR10352 and rdar://9777108
llvm-svn: 135180
2011-07-14 20:13:52 +00:00
771f29677f
[VECTOR-SELECT]
...
During type legalization we often use the SIGN_EXTEND_INREG SDNode.
When this SDNode is legalized during the LegalizeVector phase, it is
scalarized because non-simple types are automatically marked to be expanded.
In this patch we add support for lowering SIGN_EXTEND_INREG manually.
This fixes CodeGen/X86/vec_sext.ll when running with the '-promote-elements'
flag.
llvm-svn: 135144
2011-07-14 11:11:14 +00:00
db213c0400
Add assertion for the chain value type
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llvm-svn: 135143
2011-07-14 10:37:54 +00:00
15cd5a3f12
Don't emit a bit test if there is only one case the test can yield false. A simple SETNE is sufficient.
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llvm-svn: 135126
2011-07-14 01:38:42 +00:00
d6300d2956
Add a dag combine pattern for folding C2-(A+C1) -> (C2-C1)-A
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Fixes rdar://9761830
llvm-svn: 135123
2011-07-14 01:12:15 +00:00
57aa636794
Convert InsertValueInst and ExtractValueInst APIs to use ArrayRef.
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llvm-svn: 135040
2011-07-13 10:26:04 +00:00
f03fa189ca
Add an intrinsic and codegen support for fused multiply-accumulate. The intent
...
is to use this for architectures that have a native FMA instruction.
llvm-svn: 134742
2011-07-08 21:39:21 +00:00
2bb8b26aa8
Apparently we can't expect a BinaryOperator here.
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Should fix llvm-gcc selfhost.
llvm-svn: 134699
2011-07-08 12:08:24 +00:00
9960a25006
Emit a more efficient magic number multiplication for exact sdivs.
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We have to do this in DAGBuilder instead of DAGCombiner, because the exact bit is lost after building.
struct foo { char x[24]; };
long bar(struct foo *a, struct foo *b) { return a-b; }
is now compiled into
movl 4(%esp), %eax
subl 8(%esp), %eax
sarl $3, %eax
imull $-1431655765, %eax, %eax
instead of
movl 4(%esp), %eax
subl 8(%esp), %eax
movl $715827883, %ecx
imull %ecx
movl %edx, %eax
shrl $31, %eax
sarl $2, %edx
addl %eax, %edx
movl %edx, %eax
llvm-svn: 134695
2011-07-08 10:31:30 +00:00
6a6d8fc7fd
Remove a FIXME. All of the standard ones are in the list.
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llvm-svn: 134647
2011-07-07 22:29:03 +00:00
5a00499e87
Add functions 'hasPredecessor' and 'hasPredecessorHelper' to SDNode. The
...
hasPredecessorHelper function allows predecessors to be cached to speed up
repeated invocations. This fixes PR10186.
X.isPredecessorOf(Y) now just calls Y.hasPredecessor(X)
Y.hasPredecessor(X) calls Y.hasPredecessorHelper(X, Visited, Worklist) with
empty Visited and Worklist sets (i.e. no caching over invocations).
Y.hasPredecessorHelper(X, Visited, Worklist) caches search state in Visited
and Worklist to speed up repeated calls. The Visited set is searched for X
before going to the worklist to further search the DAG if necessary.
llvm-svn: 134592
2011-07-07 04:31:51 +00:00
ea336c797c
Grammar and 80-col.
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llvm-svn: 134555
2011-07-06 22:41:18 +00:00
3f158fdf6e
Introduce "expect" intrinsic instructions.
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llvm-svn: 134516
2011-07-06 18:22:43 +00:00
0d639a28aa
Rename TargetSubtarget to TargetSubtargetInfo for consistency.
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llvm-svn: 134259
2011-07-01 21:01:15 +00:00
f81292ba3b
Remove getRegClassForInlineAsmConstraint and all dependencies.
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Fixes rdar://9643582
llvm-svn: 134123
2011-06-30 01:20:03 +00:00
0eada03216
Revert r133953 for now.
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llvm-svn: 134116
2011-06-29 23:50:13 +00:00
8665f8d916
Revert a part of r126557 which could create unschedulable DAGs.
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llvm-svn: 134067
2011-06-29 13:47:25 +00:00
8264e272a9
Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries) into MC.
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llvm-svn: 134049
2011-06-29 01:14:12 +00:00
6cc775f905
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
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sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.
llvm-svn: 134021
2011-06-28 19:10:37 +00:00
4dc034df1d
During bottom up fast-isel, instructions emitted to materalize registers are at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases.
...
llvm-svn: 133953
2011-06-27 22:32:04 +00:00
8d71a75777
More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.
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llvm-svn: 133944
2011-06-27 21:26:13 +00:00
b0a5a1ee29
The index stored in the RegDefIter is one after the current index. When getting the index, decrement it so that it points to the current element. Fixes an off-by-one bug encountered when trying to make use of MVT::untyped.
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llvm-svn: 133923
2011-06-27 18:34:12 +00:00
31f25bc66f
pre-RA-sched: Cleanup register pressure tracking.
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Removed the check that peeks past EXTRA_SUBREG, which I don't think
makes sense any more. Intead treat it as a normal register def. No
significant affect on x86 or ARM benchmarks.
llvm-svn: 133917
2011-06-27 18:01:20 +00:00
537a302d1a
Distinguish early clobber output operands from clobbered registers.
...
Both become <earlyclobber> defs on the INLINEASM MachineInstr, but we
now use two different asm operand kinds.
The new Kind_Clobber is treated identically to the old
Kind_RegDefEarlyClobber for now, but x87 floating point stack inline
assembly does care about the difference.
This will pop a register off the stack:
asm("fstp %st" : : "t"(x) : "st");
While this will pop the input and push an output:
asm("fst %st" : "=&t"(r) : "t"(x));
We need to know if ST0 was a clobber or an output operand, and we can't
depend on <dead> flags for that.
llvm-svn: 133902
2011-06-27 04:08:33 +00:00
99adfec0b1
The scheduler needs to be aware on the existence of untyped nodes when it performs type propagation for EXTRACT_SUBREG.
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llvm-svn: 133838
2011-06-24 23:02:22 +00:00
f071d72c44
Handle debug info for i128 constants.
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llvm-svn: 133821
2011-06-24 20:46:11 +00:00
83be361b8a
Replace the existing forms of ConstantArray::get() with a single form
...
that takes an ArrayRef.
llvm-svn: 133615
2011-06-22 09:24:39 +00:00
d1955e78b4
Fix some trailing issues from my introduction of MVT::untyped and its use for REGISTER_SEQUENCE.
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llvm-svn: 133567
2011-06-21 22:54:23 +00:00
4c0bd9629d
Teach dag combine to match halfword byteswap patterns.
...
1. (((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8)
=> (bswap x) >> 16
2. ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0xff000000)>>8)|((x&0x00ff0000)<<8))
=> (rotl (bswap x) 16)
This allows us to eliminate most of the def : Pat patterns for ARM rev16
revsh instructions. It catches many more cases for ARM and x86.
rdar://9609108
llvm-svn: 133503
2011-06-21 06:01:08 +00:00
d34ce4344b
Fix PromoteIntRes_TRUNCATE: Add support for cases where the
...
source vector type is to be split while the target vector is to be promoted.
(eg: <4 x i64> -> <4 x i8> )
llvm-svn: 133424
2011-06-20 07:15:58 +00:00
94d67a02e0
Code cleanups: Remove duplicated logic in PromotInteRes_BITCAST, reserve vector space, reuse types.
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llvm-svn: 133389
2011-06-19 10:49:57 +00:00
35d600d9f4
Calls to AssertZext and getZeroExtendInReg must be made using scalar types.
...
llvm-svn: 133388
2011-06-19 10:22:39 +00:00
36896bfd0c
When promoting the vector elements in CopyToParts, use vector trunc
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instead of scalarizing, and doing an element-by-element truncat.
llvm-svn: 133382
2011-06-19 08:49:38 +00:00
e1fc29b6ac
Don't allocate empty read-only SmallVectors during SelectionDAG deallocation.
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llvm-svn: 133348
2011-06-18 13:13:44 +00:00
25e17b0f89
Remove unused but set variables.
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llvm-svn: 133347
2011-06-18 11:09:41 +00:00
e4a1266a9a
Fix UMULO support for 2x register width to allow the full
...
range without a libcall to a new mulo<mode> libcall
that we'd have to create.
Finishes the rest of rdar://9090077 and rdar://9210061
llvm-svn: 133318
2011-06-18 00:09:57 +00:00
Dan Gohman