Commit Graph

4827 Commits

Author SHA1 Message Date
Jim Grosbach a5f7a8cfde ARM rot_imm printing adjustment.
Allow the rot_imm operand to be optional. This sets the stage for refactoring
away the "rr" versions from the multiclasses and replacing them with Pat<>s.

llvm-svn: 136154
2011-07-26 21:44:37 +00:00
Jim Grosbach d2659138da ARM cleanup of rot_imm encoding.
Start of cleaning this up a bit. First step is to remove the encoder hook by
storing the operand as the bits it'll actually encode to so it can just be
directly used. Map it to the assembly source values 8/16/24 when we print it.

llvm-svn: 136152
2011-07-26 21:28:43 +00:00
Owen Anderson 2aedba6c5e Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE.
llvm-svn: 136141
2011-07-26 20:54:26 +00:00
Jim Grosbach 0d6022da6b Fix over-zealous rename from r136095.
llvm-svn: 136132
2011-07-26 20:41:24 +00:00
Jim Grosbach edaa35ae6f ARM diagnostics for ldrexd/stredx out of order paired register operands.
llvm-svn: 136110
2011-07-26 18:25:39 +00:00
Jim Grosbach cb31193670 ARM fix for LDREX source register encoding.
rdar://9842203

llvm-svn: 136102
2011-07-26 17:44:46 +00:00
Jim Grosbach 15e8d74231 ARM assembly parsing and encoding for SWP[B] instructions.
llvm-svn: 136098
2011-07-26 17:15:11 +00:00
Jim Grosbach dbc1c5479e ARM SWP instructions store, too, not just load.
llvm-svn: 136096
2011-07-26 17:11:05 +00:00
Jim Grosbach eab1c0d09c Clean up the ARM asm parser a bit.
No intendeded functional change. Just cleaning up a bit to make things more
self-consistent in layout and style.

llvm-svn: 136095
2011-07-26 17:10:22 +00:00
Jim Grosbach ddeda0fad3 ARM fix asm parsing range check for [0,31] immediates.
llvm-svn: 136091
2011-07-26 16:44:05 +00:00
Jim Grosbach f16378479b ARM parsing and encoding for SVC instruction.
llvm-svn: 136090
2011-07-26 16:24:27 +00:00
Evan Cheng 3a79225b4c Rename createCodeEmitter to createMCCodeEmitter; createObjectStreamer to createMCObjectStreamer.
llvm-svn: 136031
2011-07-26 00:42:34 +00:00
Evan Cheng 1142444565 Rename TargetAsmParser to MCTargetAsmParser and TargetAsmLexer to MCTargetAsmLexer; rename createAsmLexer to createMCAsmLexer and createAsmParser to createMCAsmParser.
llvm-svn: 136027
2011-07-26 00:24:13 +00:00
Chandler Carruth 97c069c1d2 Clean up a pile of hacks in our CMake build relating to TableGen.
The first problem to fix is to stop creating synthetic *Table_gen
targets next to all of the LLVM libraries. These had no real effect as
CMake specifies that add_custom_command(OUTPUT ...) directives (what the
'tablegen(...)' stuff expands to) are implicitly added as dependencies
to all the rules in that CMakeLists.txt.

These synthetic rules started to cause problems as we started more and
more heavily using tablegen files from *subdirectories* of the one where
they were generated. Within those directories, the set of tablegen
outputs was still available and so these synthetic rules added them as
dependencies of those subdirectories. However, they were no longer
properly associated with the custom command to generate them. Most of
the time this "just worked" because something would get to the parent
directory first, and run tablegen there. Once run, the files existed and
the build proceeded happily. However, as more and more subdirectories
have started using this, the probability of this failing to happen has
increased. Recently with the MC refactorings, it became quite common for
me when touching a large enough number of targets.

To add insult to injury, several of the backends *tried* to fix this by
adding explicit dependencies back to the parent directory's tablegen
rules, but those dependencies didn't work as expected -- they weren't
forming a linear chain, they were adding another thread in the race.

This patch removes these synthetic rules completely, and adds a much
simpler function to declare explicitly that a collection of tablegen'ed
files are referenced by other libraries. From that, we can add explicit
dependencies from the smaller libraries (such as every architectures
Desc library) on this and correctly form a linear sequence. All of the
backends are updated to use it, sometimes replacing the existing attempt
at adding a dependency, sometimes adding a previously missing dependency
edge.

Please let me know if this causes any problems, but it fixes a rather
persistent and problematic source of build flakiness on our end.

llvm-svn: 136023
2011-07-26 00:09:08 +00:00
Evan Cheng 5928e69d20 Rename TargetAsmBackend to MCAsmBackend; rename createAsmBackend to createMCAsmBackend.
llvm-svn: 136010
2011-07-25 23:24:55 +00:00
Jim Grosbach 475c6dbef6 ARM assembly parsing and encoding for SSAT16 instruction.
llvm-svn: 136006
2011-07-25 23:09:14 +00:00
Jim Grosbach 3a9cbeed73 ARM assembly parsing and encoding for SSAT instruction.
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').

Add tests for diagnostics and proper encoding.

llvm-svn: 135990
2011-07-25 22:20:28 +00:00
Evan Cheng 9eec764c15 Fix more MC layering violations.
llvm-svn: 135979
2011-07-25 21:32:49 +00:00
Evan Cheng 61faa55b74 Separate MCInstPrinter registration from AsmPrinter registration.
llvm-svn: 135974
2011-07-25 21:20:24 +00:00
Jim Grosbach 3ddf6aa503 Simply ARM so_reg MIOperandInfo definitions.
The shift immediate encoding, printing, etc. is handled directly by the
enclosing operand definition, so it should be a vanilla immediate, not a
nested complex operand (shift_imm).

llvm-svn: 135968
2011-07-25 21:04:58 +00:00
Evan Cheng f60768a14e Fix last bits of MC layer issues. llvm-mc doesn't need to initialize TargetMachine's anymore.
llvm-svn: 135963
2011-07-25 20:53:02 +00:00
Jim Grosbach ac798e1533 ARM asm operand renaming. Make things a bit more explicit.
llvm-svn: 135959
2011-07-25 20:49:51 +00:00
Jim Grosbach eeaab22166 More simple cleanup of ARM asm operand definitions.
llvm-svn: 135958
2011-07-25 20:38:18 +00:00
Evan Cheng f5bf19530b Code clean up.
llvm-svn: 135954
2011-07-25 20:18:48 +00:00
Jim Grosbach 2d6ef44d39 Make assembly parser method names more consistent.
llvm-svn: 135950
2011-07-25 20:14:50 +00:00
Jim Grosbach 46d575acc6 Tidy up formatting.
Remove some inititalizers that are the same as the default, move defs next to
their (singular) uses and generally simplify some formatting of asm operand
definitions.

llvm-svn: 135946
2011-07-25 20:06:30 +00:00
Jim Grosbach 5ed9fe8037 Tidy up a bit.
llvm-svn: 135945
2011-07-25 20:00:32 +00:00
NAKAMURA Takumi 287bc6bdf6 ARMMCTargetDesc.h: Fixup to add DataTypes.h, or uint32_t would be unavailable.
llvm-svn: 135837
2011-07-23 01:16:22 +00:00
Evan Cheng f2596bc62a Move TargetAsmParser.h TargetAsmBackend.h and TargetAsmLexer.h to MC where they belong.
llvm-svn: 135833
2011-07-23 00:45:41 +00:00
Evan Cheng ad5f485957 Sink ARM mc routines into MCTargetDesc.
llvm-svn: 135825
2011-07-23 00:00:19 +00:00
Jim Grosbach 801e0a3fde ARM SSAT instruction 5-bit immediate handling.
The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield.
Update the representation such that we store the operand as 0-31, allowing us
to remove the encoder method and the special case handling in the disassembler.
Update the assembly parser and the instruction printer accordingly.

llvm-svn: 135823
2011-07-22 23:16:18 +00:00
Jim Grosbach e7e1e163db ARM assembly parsing and encoding updates.
Tests for SMULBB, SMLALBT, SMLALTB, SMLALTT, and SMULL. Fix parsing of SMULLS.

llvm-svn: 135817
2011-07-22 22:06:05 +00:00
Evan Cheng 8c886a40d2 Combine all MC initialization routines into one. e.g. InitializeX86MCAsmInfo,
InitializeX86MCInstrInfo, etc. are combined into InitializeX86TargetMC.

llvm-svn: 135812
2011-07-22 21:58:54 +00:00
Jim Grosbach 8dfcc0bb92 ARM assembly parsing and encoding of SMLAL instruction.
Fix parsing of carry-setting variant SMLALS and add tests.

llvm-svn: 135797
2011-07-22 20:18:21 +00:00
Jim Grosbach d7c8c35301 ARM encoding and assembly parsing of SMLAD{X} instructions.
Fix encoding of destination register. Add tests.

llvm-svn: 135796
2011-07-22 20:11:20 +00:00
Owen Anderson 3fa7ca84d9 Fix test failures caused by my so_reg refactoring.
llvm-svn: 135785
2011-07-22 18:30:30 +00:00
Jim Grosbach d1f8bde10f ARM assembly parsing and encoding for SMC instruction.
llvm-svn: 135782
2011-07-22 18:13:31 +00:00
Jim Grosbach bc9d841878 Clean up a few more comments.
These instruction definitions are for the assembler, too, not just the
disassembler.

llvm-svn: 135781
2011-07-22 18:06:01 +00:00
Jim Grosbach 163eb27c1a Tidy up.
llvm-svn: 135779
2011-07-22 18:04:10 +00:00
Jim Grosbach 39f9388a9d Thumb assembly support for SETEND instruction.
llvm-svn: 135778
2011-07-22 17:52:23 +00:00
Jim Grosbach 9afae0d01b Tidy up.
llvm-svn: 135777
2011-07-22 17:46:13 +00:00
Jim Grosbach 0a547701a4 ARM assembly parsing and encoding for SETEND instruction.
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.

llvm-svn: 135776
2011-07-22 17:44:50 +00:00
Jim Grosbach 41d084f807 Tidy up.
llvm-svn: 135771
2011-07-22 16:59:04 +00:00
Owen Anderson 0491270f99 Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits.
llvm-svn: 135722
2011-07-21 23:38:37 +00:00
Jim Grosbach 72e7c4f9ac ARM Asm parser range checking for [0,31] immediates.
llvm-svn: 135719
2011-07-21 23:26:25 +00:00
Jim Grosbach 2a0320c877 ARM assembly parsing support for RSC instruction.
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.

llvm-svn: 135713
2011-07-21 22:56:30 +00:00
Jim Grosbach 17806e6636 ARM assembly parsing support for RSB instruction.
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.

llvm-svn: 135712
2011-07-21 22:37:43 +00:00
Jim Grosbach 4aaae18d73 Tidy up.
llvm-svn: 135706
2011-07-21 21:26:05 +00:00
Jim Grosbach 0a8d89242f ARM assembly parsing POP/PUSH mnemonics.
Aliases for LDM/STM. The single-register versions should encode to LDR/STR
with writeback, but we don't (yet) get that correct. Neither does Darwin's
system assembler, though, so that's not a deal-breaker of a limitation.

llvm-svn: 135702
2011-07-21 19:57:11 +00:00
Owen Anderson b595ed0085 Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH.
llvm-svn: 135693
2011-07-21 18:54:16 +00:00