9857229aba
Add the README files to the distribution.
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llvm-svn: 27651
2006-04-13 06:39:24 +00:00
3f9c17906f
Disable switch lowering for targets based on the selection dag isel,
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letting the code generator handle them directly.
llvm-svn: 27539
2006-04-08 19:46:55 +00:00
2d7298c362
Foundation for call frame information.
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llvm-svn: 27491
2006-04-07 16:34:46 +00:00
d1aa1638c6
Expose base register for DwarfWriter. Refactor code accordingly.
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llvm-svn: 27225
2006-03-28 13:48:33 +00:00
fa53b276d0
Translate llvm target registers to dwarf register numbers properly.
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llvm-svn: 27180
2006-03-27 20:18:45 +00:00
ed728c1291
SelectionDAGISel can now natively handle Switch instructions, in the same
...
manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks. The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.
This functionality is currently only enabled on x86, but should be safe for
every target. In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.
llvm-svn: 27156
2006-03-27 01:32:24 +00:00
5d70a7c4a5
#include Intrinsics.h into all dag isels
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llvm-svn: 27109
2006-03-25 06:47:10 +00:00
bb84eae239
D'oh - should be even numbered.
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llvm-svn: 27088
2006-03-24 22:48:02 +00:00
f0729b4067
Add dwarf register numbering to register data.
...
llvm-svn: 27081
2006-03-24 21:15:58 +00:00
3c43609f1f
Add support to locate local variables in frames (early version.)
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llvm-svn: 26994
2006-03-23 18:12:57 +00:00
6f95ab7abb
Eliminate IntrinsicLowering from TargetMachine.
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Make the CBE and V9 backends create their own, since they're the only ones that use it.
llvm-svn: 26974
2006-03-23 05:43:16 +00:00
bb01d4f272
Remove BRTWOWAY*
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Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
llvm-svn: 26814
2006-03-17 01:40:33 +00:00
e363fdf318
Add support for 'special' llvm globals like debug info and static ctors/dtors.
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llvm-svn: 26628
2006-03-09 06:14:35 +00:00
9c7f50376a
Copysign needs to be expanded everywhere. Note that Alpha and IA64 should
...
implement copysign as a native op if they have it.
llvm-svn: 26541
2006-03-05 05:08:37 +00:00
ec185f7843
Don't print constant initializers, they may span lines now.
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llvm-svn: 26403
2006-02-27 20:09:23 +00:00
747cf60696
The HasNoV9 hack isn't needed here, now that tblgen knows that CustomDAGSchedInserter
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instructions are expensive.
llvm-svn: 26298
2006-02-21 18:04:32 +00:00
5965bd19f8
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
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and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
llvm-svn: 26255
2006-02-17 05:43:56 +00:00
8a77efe4f7
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
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and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.
llvm-svn: 26238
2006-02-16 21:11:51 +00:00
6db414e8de
Sparc actually *DOES* have a directive for emitting zeros. In fact, it requires
...
it, because this:
.bss
X:
.byte 0
results in the assembler warning: "initialization in bss segment". Annoying.
llvm-svn: 26204
2006-02-15 07:07:14 +00:00
a9d0b5800a
Fix SingleSource/Regression/C/2004-08-12-InlinerAndAllocas.c on Sparc.
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The ABI specifies that there is a register save area at the bottom of the
stack, which means the actual used pointer needs to be an offset from
the subtracted value.
llvm-svn: 26202
2006-02-15 06:41:34 +00:00
62c3484e43
Switch targets over to using SelectionDAG::getCALLSEQ_START to create
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CALLSEQ_START nodes.
llvm-svn: 26143
2006-02-13 09:00:43 +00:00
fcb8a3aa76
Use the auto-generated call matcher. Remove a broken impl of the frameaddr/returnaddr
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intrinsics.
Autogen frameindex matcher
llvm-svn: 26107
2006-02-10 07:35:42 +00:00
0c4dea4cb2
Update to new-style flags usage, simplifying the .td file
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llvm-svn: 26106
2006-02-10 06:58:25 +00:00
4c0bd5bcdf
Done
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llvm-svn: 26091
2006-02-09 20:00:19 +00:00
5259aa1c86
Enable LSR by default for SPARC: it is a clear win.
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llvm-svn: 26090
2006-02-09 19:59:55 +00:00
d1b82d8db0
Match getTargetNode() changes (now return SDNode* instead of SDOperand).
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llvm-svn: 26085
2006-02-09 07:17:49 +00:00
c75d5b093d
add an option to turn on LSR.
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llvm-svn: 26080
2006-02-09 05:06:36 +00:00
f6190821da
Adjust to MachineConstantPool interface change: instead of keeping a
...
value/alignment pair for each constant, keep a value/offset pair.
llvm-svn: 26078
2006-02-09 04:46:04 +00:00
6dc90ca172
Change Select() from
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SDOperand Select(SDOperand N);
to
void Select(SDOperand &Result, SDOperand N);
llvm-svn: 26067
2006-02-09 00:37:58 +00:00
463fa70eaa
Fix the Sparc backend with Evan's recent tblgen changes
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llvm-svn: 26009
2006-02-05 08:35:50 +00:00
a28b764886
Use SelectRoot() as the entry to any tblgen based isel.
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llvm-svn: 25998
2006-02-05 06:51:51 +00:00
a3e5b2c61c
remove V8 reference
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llvm-svn: 25991
2006-02-05 06:32:59 +00:00
158e1f519c
Rename SPARC V8 target to be the LLVM SPARC target.
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llvm-svn: 25985
2006-02-05 05:50:24 +00:00
94e95d2b3e
Great renaming: Sparc --> SparcV9
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llvm-svn: 11826
2004-02-25 18:44:15 +00:00
10a32da382
FunctionLiveVarInfo.h moved: include/llvm/CodeGen -> lib/Target/Sparc/LiveVar
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llvm-svn: 11804
2004-02-24 19:46:00 +00:00
8358cc573d
Move MOTy::UseType enum into MachineOperand. This eliminates the
...
switch statements in the constructors and simplifies the
implementation of the getUseType() member function. You will have to
specify defs using MachineOperand::Def instead of MOTy::Def though
(similarly for Use and UseAndDef).
llvm-svn: 11715
2004-02-22 19:23:26 +00:00
76b2ff4ded
Adjustments to support the new ConstantAggregateZero class
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llvm-svn: 11474
2004-02-15 05:55:15 +00:00
5a92240270
Use newly added next() and prior() utility functions.
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llvm-svn: 11430
2004-02-14 01:18:34 +00:00
8cdd0215bf
Remove getAllocatedRegNum(). Use getReg() instead.
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llvm-svn: 11393
2004-02-13 21:01:20 +00:00
cbf0667743
Squish warning
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llvm-svn: 11375
2004-02-13 16:14:50 +00:00
c07b64f3cb
Remove this MachineOpCodeFlags assertion - its test can never be false.
...
llvm-svn: 11342
2004-02-12 04:01:07 +00:00
80da865f77
Change MachineBasicBlock's vector of MachineInstr pointers into an
...
ilist of MachineInstr objects. This allows constant time removal and
insertion of MachineInstr instances from anywhere in each
MachineBasicBlock. It also allows for constant time splicing of
MachineInstrs into or out of MachineBasicBlocks.
llvm-svn: 11340
2004-02-12 02:27:10 +00:00
b22186adf0
MachineInstr::getOpCode() --> getOpcode() in SPARC back-end.
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llvm-svn: 11335
2004-02-11 20:47:34 +00:00
8f4142616d
Increase constness.
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llvm-svn: 11322
2004-02-11 17:55:09 +00:00
2f21547208
Remove assert as the only integer registers on the sparc are physical.
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llvm-svn: 11317
2004-02-11 06:04:51 +00:00
fcb99fe370
Fix previous broken commit. A MachineOperand may have opType ==
...
MO_VirtualRegister but if the register number is one of a physical
register is it considered as a physical register.
llvm-svn: 11315
2004-02-11 05:55:00 +00:00
adcc14d96a
Remove assert as it is meaningless. MachineOperands can be tagged as
...
MO_VirtualRegister but actually be representing a physical register.
llvm-svn: 11310
2004-02-11 04:52:30 +00:00
1cb6d2697d
Stop using this method
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llvm-svn: 11282
2004-02-10 21:12:06 +00:00
2d5feb5e04
Remvoe use of MO.isVirtualRegister(), turn an assertion into an assert()
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llvm-svn: 11280
2004-02-10 20:47:24 +00:00
2aea68ccfd
Remove use of isPhysicalRegister
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llvm-svn: 11277
2004-02-10 20:35:42 +00:00
Reid Spencer