5032c32d30
add a note
...
llvm-svn: 26549
2006-03-05 20:00:08 +00:00
c726a5c31f
Do not fold (add (shl x, c1), (shl c2, c1)) -> (shl (add x, c2), c1),
...
we want to canonicalize the other way.
llvm-svn: 26547
2006-03-05 19:52:57 +00:00
9c7f50376a
Copysign needs to be expanded everywhere. Note that Alpha and IA64 should
...
implement copysign as a native op if they have it.
llvm-svn: 26541
2006-03-05 05:08:37 +00:00
c2dd7aae71
add a note for something evan noticed
...
llvm-svn: 26539
2006-03-05 01:15:18 +00:00
8d8b4cf63d
Implemented.
...
llvm-svn: 26536
2006-03-04 23:33:44 +00:00
c9a318d8fa
Add a note
...
llvm-svn: 26523
2006-03-04 08:44:51 +00:00
c66fd44541
Add an entry
...
llvm-svn: 26520
2006-03-04 07:49:50 +00:00
6dc73297c3
MEMSET / MEMCPY lowering bugs: we can't issue a single WORD / DWORD version of
...
rep/stos and rep/mov if the count is not a constant. We could do
rep/stosl; and $count, 3; rep/stosb
For now, I will lower them to memset / memcpy calls. We will revisit this after
a little bit experiment.
Also need to take care of the trailing bytes even if the count is a constant.
Since the max. number of trailing bytes are 3, we will simply issue loads /
stores.
llvm-svn: 26517
2006-03-04 02:48:56 +00:00
e43e5c0697
add a note
...
llvm-svn: 26513
2006-03-04 01:19:34 +00:00
084a102b17
Typo
...
llvm-svn: 26512
2006-03-04 01:12:00 +00:00
a7fb285c60
Number of NodeTypes now exceeds 128.
...
llvm-svn: 26503
2006-03-03 06:58:59 +00:00
b203355298
Split the valuetypes out of Target.td into ValueTypes.td
...
llvm-svn: 26490
2006-03-03 01:55:26 +00:00
ad3c974a77
remove the read/write port/io intrinsics.
...
llvm-svn: 26479
2006-03-03 00:19:58 +00:00
9067500e2e
add a note
...
llvm-svn: 26472
2006-03-02 22:34:38 +00:00
60a60f4b1e
Implement CodeGen/PowerPC/or-addressing-mode.ll, which is also PR668.
...
llvm-svn: 26450
2006-03-01 07:14:48 +00:00
3cb349a068
add a note
...
llvm-svn: 26448
2006-03-01 06:36:20 +00:00
27f5345b1f
Compile this:
...
void foo(float a, int *b) { *b = a; }
to this:
_foo:
fctiwz f0, f1
stfiwx f0, 0, r4
blr
instead of this:
_foo:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
stw r2, 0(r4)
blr
This implements CodeGen/PowerPC/stfiwx.ll, and also incidentally does the
right thing for GCC bugzilla 26505.
llvm-svn: 26447
2006-03-01 05:50:56 +00:00
f418435819
Use a target-specific dag-combine to implement CodeGen/PowerPC/fp-int-fp.ll.
...
llvm-svn: 26445
2006-03-01 04:57:39 +00:00
4a2eeea671
Add interfaces for targets to provide target-specific dag combiner optimizations.
...
llvm-svn: 26442
2006-03-01 04:52:55 +00:00
1926427351
Vector op lowering.
...
llvm-svn: 26438
2006-03-01 01:11:20 +00:00
91c574b642
New type v2f32.
...
llvm-svn: 26435
2006-03-01 01:06:22 +00:00
0e69f45b07
Another entry.
...
llvm-svn: 26430
2006-02-28 23:38:49 +00:00
990c3602bd
Don't match x << 1 to LEAL. It's better to emit x + x.
...
llvm-svn: 26429
2006-02-28 21:13:57 +00:00
b9f35f06bc
Add a subtarget feature for the stfiwx instruction. I know the G5 has it,
...
but I don't know what other PPC impls do. If someone could update the proc
table, I would appreciate it :)
llvm-svn: 26421
2006-02-28 07:08:22 +00:00
872810da6c
remove implemented item
...
llvm-svn: 26418
2006-02-28 06:36:04 +00:00
f918ed2e33
readme updates
...
llvm-svn: 26405
2006-02-27 22:08:36 +00:00
ec185f7843
Don't print constant initializers, they may span lines now.
...
llvm-svn: 26403
2006-02-27 20:09:23 +00:00
8f2c1021b4
Removed dependency on how operands are printed (want multi-line.)
...
llvm-svn: 26399
2006-02-27 10:29:04 +00:00
ab8164042a
Implement bit propagation through sub nodes, this (re)implements
...
PowerPC/div-2.ll
llvm-svn: 26392
2006-02-27 01:00:42 +00:00
a60751dd43
Check RHS simplification before LHS simplification to avoid infinitely looping
...
on PowerPC/small-arguments.ll
llvm-svn: 26389
2006-02-27 00:36:27 +00:00
27220f8958
Just like we use the RHS of an AND to simplify the LHS, use the LHS to
...
simplify the RHS. This allows for the elimination of many thousands of
ands from multisource, and compiles CodeGen/PowerPC/and-elim.ll:test2
into this:
_test2:
srwi r2, r3, 1
xori r3, r2, 40961
blr
instead of this:
_test2:
rlwinm r2, r3, 31, 17, 31
xori r2, r2, 40961
rlwinm r3, r2, 0, 16, 31
blr
llvm-svn: 26388
2006-02-27 00:22:28 +00:00
118ddba929
Add a bunch of missed cases. Perhaps the most significant of which is that
...
assertzext produces zero bits.
llvm-svn: 26386
2006-02-26 23:36:02 +00:00
877ab55e06
ConstantPoolIndex is now the displacement portion of the address (rather
...
than base).
llvm-svn: 26382
2006-02-26 09:12:34 +00:00
75b8783aaf
Fixed ConstantPoolIndex operand asm print bug. This fixed 2005-07-17-INT-To-FP
...
and 2005-05-12-Int64ToFP.
llvm-svn: 26380
2006-02-26 08:28:12 +00:00
77d86ff8fc
* Cleaned up addressing mode matching code.
...
* Cleaned up and tweaked LEA cost analysis code. Removed some hacks.
* Handle ADD $X, c to MOV32ri $X+c. These patterns cannot be autogen'd and
they need to be matched before LEA.
llvm-svn: 26376
2006-02-25 10:09:08 +00:00
1c557bfeb5
Updates.
...
llvm-svn: 26375
2006-02-25 10:04:07 +00:00
1fac3b3360
* Allow mul, shl nodes to be codegen'd as LEA (if appropriate).
...
* Add patterns to handle GlobalAddress, ConstantPool, etc.
MOV32ri to materialize these nodes in registers.
ADD32ri to handle %reg + GA, etc.
MOV32mi to handle store GA, etc. to memory.
llvm-svn: 26374
2006-02-25 10:02:21 +00:00
e4a8b74e4f
ConstantPoolIndex is now the displacement field of addressing mode.
...
llvm-svn: 26373
2006-02-25 09:56:50 +00:00
994700101e
Added a common about the need for X86ISD::Wrapper.
...
llvm-svn: 26372
2006-02-25 09:55:19 +00:00
ed169db8a5
Added an offset field to ConstantPoolSDNode.
...
llvm-svn: 26371
2006-02-25 09:54:52 +00:00
42d5ac557c
Fix an obvious bug exposed when we are doing
...
ADD X, 4
==>
MOV32ri $X+4, ...
llvm-svn: 26366
2006-02-25 01:37:02 +00:00
7674d90fa1
Add memory printing support for PPC. Input memory operands now work with
...
inline asms! :)
llvm-svn: 26365
2006-02-24 20:27:40 +00:00
a1ec1ddd59
Implement selection of inline asm memory operands
...
llvm-svn: 26348
2006-02-24 02:13:12 +00:00
2a9e1e3e74
Recognize memory operand codes
...
llvm-svn: 26345
2006-02-24 01:10:46 +00:00
0ed48fe601
PPC JIT relocation model should be DynamicNoPIC.
...
llvm-svn: 26338
2006-02-23 22:18:07 +00:00
e0ed6ec13f
- Clean up the lowering and selection code of ConstantPool, GlobalAddress,
...
and ExternalSymbol.
- Use C++ code (rather than tblgen'd selection code) to match the above
mentioned leaf nodes. Do not mutate and nodes and do not record the
selection in CodeGenMap. These nodes should be safe to duplicate. This is
a performance win.
llvm-svn: 26335
2006-02-23 20:41:18 +00:00
1bad2546d0
Implement the PPC inline asm "L" modifier. This allows us to compile:
...
long long test(long long X) {
__asm__("foo %0 %L0 %1 %L1" : "=r"(X): "r"(X));
return X;
}
to:
foo r2 r3 r2 r3
llvm-svn: 26333
2006-02-23 19:31:10 +00:00
16f08f53b1
"." isn't enough to get a private label on linux, use ".L".
...
llvm-svn: 26327
2006-02-23 05:25:02 +00:00
2bacf981bf
add a small and simple case.
...
llvm-svn: 26326
2006-02-23 05:17:43 +00:00
f4448cee66
A couple of new entries.
...
llvm-svn: 26325
2006-02-23 02:50:21 +00:00
1f342c2884
PIC related bug fixes.
...
1. Various asm printer bug.
2. Lowering bug. Now TargetGlobalAddress is wrapped in X86ISD::TGAWrapper.
llvm-svn: 26324
2006-02-23 02:43:52 +00:00
7eabbfd618
X86 codegen tweak to use lea in another case:
...
Suppose base == %eax and it has multiple uses, then instead of
movl %eax, %ecx
addl $8, %ecx
use
leal 8(%eax), %ecx.
llvm-svn: 26323
2006-02-23 00:13:58 +00:00
7714a59d91
Missing .globl for weak / link-once .text symbols.
...
llvm-svn: 26321
2006-02-22 23:59:57 +00:00
2e124af406
Don't return registers from register classes that aren't legal.
...
llvm-svn: 26317
2006-02-22 23:00:51 +00:00
73136dfecc
- Added option -relocation-model to set relocation model. Valid values include static, pic,
...
dynamic-no-pic, and default.
PPC and x86 default is dynamic-no-pic for Darwin, pic for others.
- Removed options -enable-pic and -ppc-static.
llvm-svn: 26315
2006-02-22 20:19:42 +00:00
2fa33a989d
Coordinate activities with llvm-gcc4 and dwarf.
...
llvm-svn: 26314
2006-02-22 19:02:11 +00:00
9e252e3bcf
Added MMX, SSE1, and SSE2 vector instructions and some simple patterns.
...
Fixed some existing bugs (wrong predicates, prefixes) at the same time.
llvm-svn: 26310
2006-02-22 02:26:30 +00:00
7ad77dfc2a
split register class handling from explicit physreg handling.
...
llvm-svn: 26308
2006-02-22 00:56:39 +00:00
7bb4696dc3
Updates to match change of getRegForInlineAsmConstraint prototype
...
llvm-svn: 26305
2006-02-21 23:11:00 +00:00
d58478161f
One more round of reorg so sabre doesn't freak out. :-)
...
llvm-svn: 26303
2006-02-21 20:00:20 +00:00
6fc1162855
A big more cleaning up.
...
llvm-svn: 26302
2006-02-21 19:30:30 +00:00
8711b6bff3
Moving things to their proper places.
...
llvm-svn: 26301
2006-02-21 19:26:52 +00:00
6e595b9fd8
Split instruction info into multiple files, one for each of x87, MMX, and SSE.
...
llvm-svn: 26300
2006-02-21 19:13:53 +00:00
0a08f44704
missed optzn
...
llvm-svn: 26299
2006-02-21 18:29:44 +00:00
747cf60696
The HasNoV9 hack isn't needed here, now that tblgen knows that CustomDAGSchedInserter
...
instructions are expensive.
llvm-svn: 26298
2006-02-21 18:04:32 +00:00
d57203c0a1
Added separate alias instructions for SSE logical ops that operate on non-packed types.
...
llvm-svn: 26297
2006-02-21 02:24:38 +00:00
afffe63fc1
Added MMX and XMM packed integer move instructions, movd and movq.
...
llvm-svn: 26296
2006-02-21 01:39:57 +00:00
fa57a0add9
Added SSE2 128-bit integer packed types: V16I8, V8I16, V4I32, and V2I64.
...
Added generic vector types: VR64 and VR128.
llvm-svn: 26295
2006-02-21 01:38:21 +00:00
43070b7541
Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit
...
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).
llvm-svn: 26294
2006-02-20 22:34:53 +00:00
4547400ae2
Some updates
...
llvm-svn: 26292
2006-02-20 19:58:27 +00:00
d13778eb30
If SSE3 is available, promote FP_TO_UINT i32 to FP_TO_SINT i64 to take
...
advantage of fisttpll.
llvm-svn: 26288
2006-02-18 07:26:17 +00:00
983ca89714
Add a fold for add that exchanges it with a constant shift if possible, so
...
that the shift may be more easily folded into other operations.
llvm-svn: 26286
2006-02-18 02:43:25 +00:00
70af620709
Added fisttp for fp to int conversion.
...
llvm-svn: 26283
2006-02-18 02:36:28 +00:00
06c2e6d1b3
Disable PIC for JIT.
...
llvm-svn: 26281
2006-02-18 01:49:25 +00:00
5caed8a231
Jit does not support PIC yet.
...
llvm-svn: 26278
2006-02-18 00:57:10 +00:00
5588de9415
x86 / Darwin PIC support.
...
llvm-svn: 26273
2006-02-18 00:15:05 +00:00
5f99760ae7
Moved PICEnabled to include/llvm/Target/TargetOptions.h
...
llvm-svn: 26272
2006-02-18 00:08:58 +00:00
07a2677e43
unbreak the build
...
llvm-svn: 26260
2006-02-17 07:09:27 +00:00
593bea73ba
Unbreak x86 be
...
llvm-svn: 26259
2006-02-17 07:01:52 +00:00
5965bd19f8
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
...
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
llvm-svn: 26255
2006-02-17 05:43:56 +00:00
67c21b6c46
add note about div by power of 2
...
llvm-svn: 26253
2006-02-17 04:20:13 +00:00
0d62ebd13f
Fix bug noticed by VC++.
...
llvm-svn: 26252
2006-02-17 02:12:18 +00:00
3920ce4d8d
Whoops, didn't mean to check this in yet.
...
llvm-svn: 26250
2006-02-17 00:56:19 +00:00
4a0dc0c8f6
Add a missing and useful pat frag
...
llvm-svn: 26249
2006-02-17 00:51:06 +00:00
b590d3a72b
Remind ourselves to revisit the "pxor vs. xorps/xorpd to clear XMM registers"
...
issue. Need to do more experiments.
llvm-svn: 26247
2006-02-17 00:04:28 +00:00
7e5496d5fe
Kill the x86 pattern isel. boom.
...
llvm-svn: 26246
2006-02-17 00:03:04 +00:00
db1dbbe8d6
Remove the entry about using movapd for SSE reg-reg moves.
...
llvm-svn: 26245
2006-02-17 00:00:58 +00:00
eb7b3380fd
pxor (for FLD0SS) encoding was missing the OpSize prefix.
...
llvm-svn: 26244
2006-02-16 23:59:30 +00:00
936cc9fe53
Remove the skeleton target, it doesn't produce useful code and there are
...
other small targets that do that can be learned from. They also have
the added advantage of being tested :)
llvm-svn: 26243
2006-02-16 23:14:50 +00:00
24c461b51e
1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. This
...
proves to be worth 20% on Ptrdist/ks. Might be related to dependency
breaking support.
2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These
are used for FR32 / FR64 reg-to-reg copies.
3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to
spill / restore FsMOVAPSrr and FsMOVAPDrr.
llvm-svn: 26241
2006-02-16 22:45:17 +00:00
3f99628939
Use movaps / movapd to spill / restore V4F4 / V2F8 registers.
...
llvm-svn: 26240
2006-02-16 21:20:26 +00:00
8a77efe4f7
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
...
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.
llvm-svn: 26238
2006-02-16 21:11:51 +00:00
01afec2adb
MOVAPSrr and MOVAPDrr instruction format should be MRMSrcReg.
...
llvm-svn: 26234
2006-02-16 19:34:41 +00:00
36a2ee299e
distinguish between objects and register names, now we can have stuff
...
with names like "f84", "in6" etc etc.
this should fix one or two tests
llvm-svn: 26232
2006-02-16 13:12:57 +00:00
42c01c8d39
If the false case is the current basic block, then this is a self loop.
...
We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra
instruction in the loop. Instead, invert the condition and emit
"Loop: ... br!cond Loop; br Out.
Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering.
llvm-svn: 26231
2006-02-16 08:27:56 +00:00
ae82498e81
Use movaps / movapd (instead of movss / movsd) to do FR32 / FR64 reg to reg
...
transfer.
According to the Intel P4 Optimization Manual:
Moves that write a portion of a register can introduce unwanted
dependences. The movsd reg, reg instruction writes only the bottom
64 bits of a register, not to all 128 bits. This introduces a dependence on
the preceding instruction that produces the upper 64 bits (even if those
bits are not longer wanted). The dependence inhibits register renaming,
and thereby reduces parallelism.
Not to mention movaps is shorter than movss.
llvm-svn: 26226
2006-02-16 01:50:02 +00:00
03c1e6f48e
A bit more memset / memcpy optimization.
...
Turns them into calls to memset / memcpy if 1) buffer(s) are not DWORD aligned,
2) size is not known to be greater or equal to some minimum value (currently 128).
llvm-svn: 26224
2006-02-16 00:21:07 +00:00
76a7775ce1
Remove an entry.
...
llvm-svn: 26222
2006-02-15 22:14:34 +00:00
6afb5587da
new test
...
llvm-svn: 26217
2006-02-15 19:52:06 +00:00
6db414e8de
Sparc actually *DOES* have a directive for emitting zeros. In fact, it requires
...
it, because this:
.bss
X:
.byte 0
results in the assembler warning: "initialization in bss segment". Annoying.
llvm-svn: 26204
2006-02-15 07:07:14 +00:00
a9d0b5800a
Fix SingleSource/Regression/C/2004-08-12-InlinerAndAllocas.c on Sparc.
...
The ABI specifies that there is a register save area at the bottom of the
stack, which means the actual used pointer needs to be an offset from
the subtracted value.
llvm-svn: 26202
2006-02-15 06:41:34 +00:00
7a6c21ac26
Remove an entry.
...
llvm-svn: 26197
2006-02-15 01:56:48 +00:00
2d23c9f1ab
Use .zerofill on x86/darwin.
...
llvm-svn: 26196
2006-02-15 01:56:23 +00:00
aacc4c3b4c
cvtsd2ss / cvtss2sd encoding bug.
...
llvm-svn: 26193
2006-02-15 00:31:03 +00:00
665c26ab40
movaps, movapd encoding bug.
...
llvm-svn: 26192
2006-02-15 00:11:37 +00:00
e3c793a71a
new note
...
llvm-svn: 26186
2006-02-14 22:19:54 +00:00
b134520b86
If we have zero initialized data with external linkage, use .zerofill to
...
emit it (instead of .space), saving a bit of space in the .o file.
For example:
int foo[100];
int bar[100] = {};
when compiled with C++ or -fno-common results in shrinkage from 1160 to 360
bytes of space. The X86 backend can also do this on darwin.
llvm-svn: 26185
2006-02-14 22:18:23 +00:00
f84774ed46
Don't special case XS, XD prefixes.
...
llvm-svn: 26183
2006-02-14 21:52:51 +00:00
fb7b5ef74b
Bug fix: XS, XD prefixes were being emitted twice.
...
XMM registers were not being handled.
llvm-svn: 26182
2006-02-14 21:45:24 +00:00
84fb09eba4
Make sure that weak functions are aligned properly
...
llvm-svn: 26181
2006-02-14 20:42:33 +00:00
43b72f4421
Duh
...
llvm-svn: 26180
2006-02-14 20:37:37 +00:00
ad8c20cd2b
Remove -disable-x86-sse
...
llvm-svn: 26179
2006-02-14 20:30:14 +00:00
4b40a42653
Rename maxStoresPerMemSet to maxStoresPerMemset, etc.
...
llvm-svn: 26174
2006-02-14 08:38:30 +00:00
f976d79f78
Add a entry.
...
llvm-svn: 26173
2006-02-14 08:25:32 +00:00
6a37456d73
Set maxStoresPerMemSet to 16. Ditto for maxStoresPerMemCpy and
...
maxStoresPerMemMove. Although the last one is not used.
llvm-svn: 26172
2006-02-14 08:25:08 +00:00
40b6eb9973
Enable SSE (for the right subtargets)
...
llvm-svn: 26169
2006-02-14 08:07:58 +00:00
d2d174dd0e
Another hack due to allowing multiple symbols with the same name.
...
llvm-svn: 26150
2006-02-13 22:22:42 +00:00
a438ef0ee7
improved zap discovery
...
llvm-svn: 26148
2006-02-13 18:52:29 +00:00
62c3484e43
Switch targets over to using SelectionDAG::getCALLSEQ_START to create
...
CALLSEQ_START nodes.
llvm-svn: 26143
2006-02-13 09:00:43 +00:00
3a0ad47b39
Switch to using getCALLSEQ_START instead of using our own creation calls
...
llvm-svn: 26142
2006-02-13 08:55:29 +00:00
bc3ec1d37b
Add missing patterns for andi. and andis., fixing test/Regression/CodeGen/
...
PowerPC/and-imm.ll
llvm-svn: 26136
2006-02-12 09:09:52 +00:00
4698e4f5fe
fix storing booleans (grawp missed this one)
...
llvm-svn: 26120
2006-02-11 07:33:17 +00:00
0010a92375
now short immediates will get matched (previously constants were all
...
triggering movl 64bit imm fat instructions)
llvm-svn: 26119
2006-02-11 07:32:15 +00:00
a86ba85dc5
Prevent certain nodes that have already been selected from being folded into
...
X86 addressing mode. Currently we do not allow any node whose target node
produces a chain as well as any node that is at the root of the addressing
mode expression tree.
llvm-svn: 26117
2006-02-11 02:05:36 +00:00
2b6f78b664
Nicer code. :-)
...
llvm-svn: 26111
2006-02-10 22:46:26 +00:00
d49cc3634e
Added X86 isel debugging stuff.
...
llvm-svn: 26110
2006-02-10 22:24:32 +00:00
fcb8a3aa76
Use the auto-generated call matcher. Remove a broken impl of the frameaddr/returnaddr
...
intrinsics.
Autogen frameindex matcher
llvm-svn: 26107
2006-02-10 07:35:42 +00:00
0c4dea4cb2
Update to new-style flags usage, simplifying the .td file
...
llvm-svn: 26106
2006-02-10 06:58:25 +00:00
907be3e24c
Remove a completed entry; add a new entry about fisttp op
...
llvm-svn: 26105
2006-02-10 05:48:15 +00:00
101e4b916a
Match tblgen change.
...
llvm-svn: 26096
2006-02-09 22:12:53 +00:00
4c0bd5bcdf
Done
...
llvm-svn: 26091
2006-02-09 20:00:19 +00:00
5259aa1c86
Enable LSR by default for SPARC: it is a clear win.
...
llvm-svn: 26090
2006-02-09 19:59:55 +00:00
d1b82d8db0
Match getTargetNode() changes (now return SDNode* instead of SDOperand).
...
llvm-svn: 26085
2006-02-09 07:17:49 +00:00
c75d5b093d
add an option to turn on LSR.
...
llvm-svn: 26080
2006-02-09 05:06:36 +00:00
f6190821da
Adjust to MachineConstantPool interface change: instead of keeping a
...
value/alignment pair for each constant, keep a value/offset pair.
llvm-svn: 26078
2006-02-09 04:46:04 +00:00
ba97264e72
rename fields of constant pool entries
...
llvm-svn: 26076
2006-02-09 04:22:52 +00:00
832d78d981
Always pass in an alignment.
...
llvm-svn: 26070
2006-02-09 02:19:16 +00:00
d94a3d2c8a
provide an explicit alignment for cp entries
...
llvm-svn: 26069
2006-02-09 02:15:30 +00:00
6dc90ca172
Change Select() from
...
SDOperand Select(SDOperand N);
to
void Select(SDOperand &Result, SDOperand N);
llvm-svn: 26067
2006-02-09 00:37:58 +00:00
2e07d6370a
Darwin doesn't support #APP/#NO_APP
...
llvm-svn: 26066
2006-02-08 23:42:22 +00:00
26e385a623
Rename BSel -> PPCBSel for the benefit of doxygen users.
...
Move the methods out of line.
Remove unused Debug.h stuff.
Teach getNumBytesForInstruction to know the size of an inline asm.
llvm-svn: 26064
2006-02-08 19:33:26 +00:00
b4fc050f0f
add a simple optimization
...
llvm-svn: 26062
2006-02-08 17:47:22 +00:00
b7e074ab9b
more email -> README moving
...
llvm-svn: 26054
2006-02-08 07:12:07 +00:00
f7b962d7d7
Emit the 'mr' pseudoop for easier reading.
...
llvm-svn: 26053
2006-02-08 06:56:40 +00:00
45bb34b715
Add some random notes, not high-prio
...
llvm-svn: 26052
2006-02-08 06:52:06 +00:00
b97142eec0
Move emails from nate into public places
...
llvm-svn: 26051
2006-02-08 06:43:51 +00:00
adeb8fb5a2
Fixed a local common symbol bug.
...
llvm-svn: 26044
2006-02-07 23:32:58 +00:00
ec212fb66d
For ELF, .comm takes alignment value as the optional 3rd argument. It must be
...
specified in bytes.
llvm-svn: 26043
2006-02-07 21:54:08 +00:00
203b2f1288
Implement getConstraintType for PPC.
...
llvm-svn: 26042
2006-02-07 20:16:30 +00:00
5a76680de1
Darwin ABI issues: weak, linkonce, etc. dynamic-no-pic support is complete.
...
Also fixed a function stub bug. Added weak and linkonce support for
x86 Linux.
llvm-svn: 26038
2006-02-07 08:38:37 +00:00
227e469c25
Remind myself to add PIC and static asm printer support.
...
llvm-svn: 26037
2006-02-07 08:35:44 +00:00
15a6c4c444
Add the simple PPC integer constraints
...
llvm-svn: 26027
2006-02-07 00:47:13 +00:00
d62a3bfa66
Eliminate the printCallOperand method, using a 'call' modifier on
...
printOperand instead.
llvm-svn: 26025
2006-02-06 23:41:19 +00:00
2bf2c8d7e7
Change prototype
...
llvm-svn: 26022
2006-02-06 22:18:19 +00:00
f5b7f16259
see what this allignment thing will do
...
llvm-svn: 26017
2006-02-06 17:15:17 +00:00
58d48c8118
We seem to have settled to __DWARF for section name.
...
llvm-svn: 26015
2006-02-06 14:16:15 +00:00
d5f2ba0d6f
- Update load folding checks to match those auto-generated by tblgen.
...
- Manually select SDOperand's returned by TryFoldLoad which make up the
load address.
llvm-svn: 26012
2006-02-06 06:02:33 +00:00
bfa4b7cc75
Complex pattern isel code shouldn't select nodes.
...
llvm-svn: 26010
2006-02-05 08:45:01 +00:00
463fa70eaa
Fix the Sparc backend with Evan's recent tblgen changes
...
llvm-svn: 26009
2006-02-05 08:35:50 +00:00
8467e5d6af
This xform isn't safe
...
llvm-svn: 26007
2006-02-05 08:26:16 +00:00
4b8fcc229f
some stuff is done
...
llvm-svn: 26004
2006-02-05 07:54:37 +00:00
a28b764886
Use SelectRoot() as the entry to any tblgen based isel.
...
llvm-svn: 25998
2006-02-05 06:51:51 +00:00
54cb1833a4
Use SelectRoot() as entry of any tblgen based isel.
...
llvm-svn: 25997
2006-02-05 06:46:41 +00:00
25777c8c25
Remove the SparcV8 backend. It has been renamed to be the Sparc backend.
...
llvm-svn: 25992
2006-02-05 06:33:29 +00:00
a3e5b2c61c
remove V8 reference
...
llvm-svn: 25991
2006-02-05 06:32:59 +00:00
158e1f519c
Rename SPARC V8 target to be the LLVM SPARC target.
...
llvm-svn: 25985
2006-02-05 05:50:24 +00:00
c0e48c6c58
add a note
...
llvm-svn: 25984
2006-02-05 05:27:35 +00:00
d19d51f414
Re-commit the last bit of change that was backed out.
...
llvm-svn: 25983
2006-02-05 05:25:07 +00:00
c070cb685d
Use getPreferredAlignmentLog.
...
llvm-svn: 25980
2006-02-05 01:45:04 +00:00
1b1a8731c0
Use the asmprinter to find out what the preferred alignment of a global is.
...
This patch speeds up 172.mgrid from 31.81s to 11.39s on darwin/ppc.
Many many thanks to Nate for tracking down the root cause of the issue.
llvm-svn: 25979
2006-02-05 01:30:45 +00:00
1fcff15f86
linkage fix for weak functions
...
llvm-svn: 25976
2006-02-04 19:13:09 +00:00
22b4edfb42
Temporarily revert this patch, which probably breaks with the
...
tblgen patch reverted.
llvm-svn: 25971
2006-02-04 09:24:16 +00:00
ce87cac555
Complex pattern's custom matcher should not call Select() on any operands.
...
Select them afterwards if it returns true.
llvm-svn: 25968
2006-02-04 08:50:49 +00:00
ab146eae38
Custom lower VAARG for the case when we are doing vaarg(double). In this
...
case, the double being loaded may not be 8-byte aligned, so we have to use
our standard bit_convert game.
llvm-svn: 25967
2006-02-04 08:31:30 +00:00
a1fa8b1c88
Fix a nasty typo that broke functions with big stack frames.
...
llvm-svn: 25966
2006-02-04 08:04:21 +00:00
d096b2f3e0
fix a bug in my last checkin
...
llvm-svn: 25965
2006-02-04 07:48:46 +00:00
a1e895cf97
Remove some stuff that now works
...
llvm-svn: 25963
2006-02-04 07:29:35 +00:00
32ed2b45c7
add a note
...
llvm-svn: 25962
2006-02-04 07:07:31 +00:00
2c0956bcea
Two changes:
...
1. Treat FMOVD as a copy instruction, to help with coallescing in V9 mode
2. When in V9 mode, insert FMOVD instead of FpMOVD instructions, as we don't
ever rewrite FpMOVD instructions into FMOVS instructions, thus we just end
up with commented out copies!
This should fix a bunch of failures in V9 mode on sparc.
llvm-svn: 25961
2006-02-04 06:58:46 +00:00
0a977c95aa
Remove an unnecessary predicate.
...
llvm-svn: 25954
2006-02-04 02:23:01 +00:00
11613a5219
Separate FILD and FILD_FLAG, the later is only used for SSE2. It produces a
...
flag so it can be flagged to a FST.
llvm-svn: 25953
2006-02-04 02:20:30 +00:00
ee1dadbccf
implementation of some methods for inlineasm
...
llvm-svn: 25951
2006-02-04 02:13:02 +00:00
20a894282d
Implement some feedback from sabre
...
llvm-svn: 25946
2006-02-03 22:38:07 +00:00
dc7bba9ffe
Add a framework for eliminating instructions that produces undemanded bits.
...
llvm-svn: 25945
2006-02-03 22:24:05 +00:00
81e66abd1e
add a note
...
llvm-svn: 25944
2006-02-03 22:06:45 +00:00
d079dbb9b0
another case Nate came up with
...
llvm-svn: 25943
2006-02-03 22:05:41 +00:00
277462e20f
add a note
...
llvm-svn: 25942
2006-02-03 21:25:23 +00:00
a1d312c6ea
remove an old comment
...
llvm-svn: 25940
2006-02-03 18:59:39 +00:00
23d55f2547
Remove the X86PeepholeOptimizerPass, a truly horrible old hack that is now
...
obsolete. yaay :)
llvm-svn: 25939
2006-02-03 18:54:24 +00:00
c408558638
When rewriting frame instructions, emit the appropriate small-immediate
...
instruction when possible.
llvm-svn: 25938
2006-02-03 18:20:04 +00:00
ca76917388
Teach sparc to fold loads/stores into copies.
...
Remove the dead getRegClassForType method
minor formating changes.
llvm-svn: 25936
2006-02-03 07:06:25 +00:00
d7d98611ca
Implement isLoadFromStackSlot and isStoreToStackSlot
...
llvm-svn: 25932
2006-02-03 06:44:54 +00:00
a23b04acdb
remove some target-indep and implemented notes
...
llvm-svn: 25930
2006-02-03 06:22:11 +00:00
d1aaee03ce
target independent notes
...
llvm-svn: 25929
2006-02-03 06:21:43 +00:00
fc567d85d5
Flesh out a couple of the items in the README
...
llvm-svn: 25928
2006-02-03 05:17:06 +00:00
1318240fd0
isStoreToStackSlot
...
llvm-svn: 25925
2006-02-03 03:07:37 +00:00
a1eac9b978
the X86 backend no longer needs to delete its own noop copies
...
llvm-svn: 25923
2006-02-03 02:59:58 +00:00
f0a2d66d1c
Add a note
...
llvm-svn: 25921
2006-02-03 01:49:49 +00:00
9b178ce225
update a note
...
llvm-svn: 25918
2006-02-02 23:50:22 +00:00
4efb328926
add 64b gpr store to the possible list of isStoreToStackSlot opcodes.
...
llvm-svn: 25916
2006-02-02 21:07:50 +00:00
5123346708
fix operand numbers
...
llvm-svn: 25915
2006-02-02 20:38:12 +00:00
c327d71e06
implement isStoreToStackSlot for PPC
...
llvm-svn: 25914
2006-02-02 20:16:12 +00:00
bb53acd03c
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :)
...
llvm-svn: 25913
2006-02-02 20:12:32 +00:00
246ee44c8f
implement isStoreToStackSlot
...
llvm-svn: 25911
2006-02-02 20:00:41 +00:00
0acc90c67e
add a method
...
llvm-svn: 25910
2006-02-02 19:57:16 +00:00
d8208c3665
more notes
...
llvm-svn: 25908
2006-02-02 19:43:28 +00:00
d3f033e8e0
add a note, I have no idea how important this is.
...
llvm-svn: 25907
2006-02-02 19:16:34 +00:00
e10e1024bc
%fcc is not an alias for %fcc0
...
llvm-svn: 25906
2006-02-02 08:02:20 +00:00
cb34968d19
correct an opcode
...
llvm-svn: 25905
2006-02-02 07:56:15 +00:00
9dd7df7ee7
new example
...
llvm-svn: 25903
2006-02-02 07:37:11 +00:00
cd018525f8
Update the README
...
llvm-svn: 25902
2006-02-02 07:27:56 +00:00
e0c60d63b1
Implement MaskedValueIsZero for ANY_EXTEND nodes
...
llvm-svn: 25900
2006-02-02 06:43:15 +00:00
4b2ec8af23
implemented, testcase here: test/Regression/CodeGen/X86/compare-add.ll
...
llvm-svn: 25899
2006-02-02 06:36:48 +00:00
d3908f79cb
Update.
...
llvm-svn: 25896
2006-02-02 02:40:17 +00:00
d8fba3a1ee
Fix a erroneous comment.
...
llvm-svn: 25894
2006-02-02 00:28:23 +00:00
6132a87cf4
more notes
...
llvm-svn: 25890
2006-02-01 23:38:08 +00:00
b3ea2677a4
Tell codegen MOVAPSrr and MOVAPDrr are copies.
...
llvm-svn: 25889
2006-02-01 23:03:16 +00:00
f1ed826c2a
Added SSE entries to foldMemoryOperand().
...
llvm-svn: 25888
2006-02-01 23:02:25 +00:00
8b40cde148
Rearrange code to my liking. :)
...
llvm-svn: 25887
2006-02-01 23:01:57 +00:00
f7f056751c
add a method
...
llvm-svn: 25884
2006-02-01 22:38:46 +00:00
2f7650f9dc
another note
...
llvm-svn: 25883
2006-02-01 21:44:48 +00:00
4b1c726fbb
Add immediate forms of cmov and remove some cruft
...
llvm-svn: 25882
2006-02-01 19:37:33 +00:00
ba56b5dc35
Finegrainify namespacification
...
llvm-svn: 25877
2006-02-01 18:10:56 +00:00
a983beab37
add a note
...
llvm-svn: 25876
2006-02-01 17:54:23 +00:00
7e7f439f85
Fix some of the stuff in the PPC README file, and clean up legalization
...
of the SELECT_CC, BR_CC, and BRTWOWAY_CC nodes.
llvm-svn: 25875
2006-02-01 07:19:44 +00:00
3da1bb520e
add a note, I'll take care of this after nate commits his big patch
...
llvm-svn: 25873
2006-02-01 06:40:32 +00:00
9e350cd6ad
- Use xor to clear integer registers (set R, 0).
...
- Added a new format for instructions where the source register is implied
and it is same as the destination register. Used for pseudo instructions
that clear the destination register.
llvm-svn: 25872
2006-02-01 06:13:50 +00:00
c404b5748c
Remove another entry.
...
llvm-svn: 25871
2006-02-01 06:08:48 +00:00
b0a76b0981
Another regression from the pattern isel
...
llvm-svn: 25867
2006-02-01 01:44:25 +00:00
7ed3101d14
Beef up the interface to inline asm constraint parsing, making it more general, useful, and easier to use.
...
llvm-svn: 25866
2006-02-01 01:29:47 +00:00
a24617f5d4
Return's chain should be matching either the chain produced by the
...
value or the chain going into the load.
llvm-svn: 25863
2006-02-01 01:19:32 +00:00
a0527473ac
another testcase.
...
llvm-svn: 25862
2006-02-01 00:28:12 +00:00
e1ce4d7115
When folding a load into a return of SSE value, check the chain to
...
ensure the memory location has not been clobbered.
llvm-svn: 25861
2006-02-01 00:20:21 +00:00
bc1fcd074e
Remove an item. It's done.
...
llvm-svn: 25860
2006-02-01 00:15:53 +00:00
5659ca8f47
Be smarter about whether to store the SSE return value in memory. If
...
it is already available in memory, do a fld directly from there.
llvm-svn: 25859
2006-01-31 23:19:54 +00:00
64387c3e9c
turning these into 'adds' would require extra copies
...
llvm-svn: 25858
2006-01-31 22:59:46 +00:00
72d5c256c9
- Allow XMM load (for scalar use) to be folded into ANDP* and XORP*.
...
- Use XORP* to implement fneg.
llvm-svn: 25857
2006-01-31 22:28:30 +00:00
a91eb48547
Remove entries on fabs and fneg. These are done.
...
llvm-svn: 25856
2006-01-31 22:26:21 +00:00
32be2dc0af
Allow the specification of explicit alignments for constant pool entries.
...
llvm-svn: 25855
2006-01-31 22:23:14 +00:00
c642aa5e1c
* Fix 80-column violations
...
* Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'.
* Add inline asm constraint specification.
llvm-svn: 25854
2006-01-31 19:43:35 +00:00
0151361d21
add info about the inline asm register constraints for PPC
...
llvm-svn: 25853
2006-01-31 19:20:21 +00:00
0962ffc4a6
add a missing break that caused a lot of failures last night :(
...
llvm-svn: 25851
2006-01-31 17:20:06 +00:00
a162f208ee
Codegen
...
bool %test(int %X) {
%Y = seteq int %X, 13
ret bool %Y
}
as
_test:
addi r2, r3, -13
cntlzw r2, r2
srwi r3, r2, 5
blr
rather than
_test:
cmpwi cr7, r3, 13
mfcr r2
rlwinm r3, r2, 31, 31, 31
blr
This has very little effect on most code, but speeds up analyzer 23% and
mason 11%
llvm-svn: 25848
2006-01-31 08:17:29 +00:00
ac9892ccaf
okay, one more
...
llvm-svn: 25847
2006-01-31 07:45:45 +00:00
882611dc25
another note
...
llvm-svn: 25846
2006-01-31 07:45:08 +00:00
24b0742476
More notes
...
llvm-svn: 25845
2006-01-31 07:43:33 +00:00
57480d0634
another one
...
llvm-svn: 25844
2006-01-31 07:38:32 +00:00
17cd988419
add a note
...
llvm-svn: 25843
2006-01-31 07:37:20 +00:00
799716141b
add conditional moves of float and double values on int/fp condition codes.
...
llvm-svn: 25842
2006-01-31 07:26:55 +00:00
b0fe138b65
example nate pointed out
...
llvm-svn: 25841
2006-01-31 07:16:34 +00:00
6f9bf658a7
treat conditional branches the same way as conditional moves (giving them
...
an operand that contains the condcode), making things significantly simpler.
llvm-svn: 25840
2006-01-31 06:56:30 +00:00
21ec192419
compactify all of the integer conditional moves into one instruction that takes
...
a CC as an operand. Much smaller, much happier.
llvm-svn: 25839
2006-01-31 06:49:09 +00:00
196d58373c
Add immediate forms of integer cmovs
...
llvm-svn: 25838
2006-01-31 06:24:29 +00:00
283492b4fe
Shrinkify
...
llvm-svn: 25837
2006-01-31 06:18:16 +00:00
70c9e42593
Add the full complement of conditional moves of integer registers.
...
llvm-svn: 25834
2006-01-31 05:26:36 +00:00
b6493b3165
Compile this:
...
void %X(int %A) {
%C = setlt int %A, 123 ; <bool> [#uses=1]
br bool %C, label %T, label %F
T: ; preds = %0
call int %main( int 0 ) ; <int>:0 [#uses=0]
ret void
F: ; preds = %0
ret void
}
to this:
X:
save -96, %o6, %o6
subcc %i0, 122, %l0
bg .LBBX_2 ! F
nop
...
not this:
X:
save -96, %o6, %o6
sethi 0, %l0
or %g0, 1, %l1
subcc %i0, 122, %l2
bg .LBBX_4 !
nop
.LBBX_3: !
or %g0, %l0, %l1
.LBBX_4: !
subcc %l1, 0, %l0
bne .LBBX_2 ! F
nop
llvm-svn: 25833
2006-01-31 05:05:52 +00:00
2dd217b88f
Added custom lowering of fabs
...
llvm-svn: 25831
2006-01-31 03:14:29 +00:00
a9bfca8d1e
add the 'lucas' optimization
...
llvm-svn: 25830
2006-01-31 02:55:28 +00:00
0e70729e83
I don't see why this optimization isn't safe, but it isn't, so disable it
...
llvm-svn: 25829
2006-01-31 02:45:52 +00:00
d916e78b0a
Another high-prio selection performance bug
...
llvm-svn: 25828
2006-01-31 02:10:06 +00:00
2b70a6f853
more mumbling
...
llvm-svn: 25826
2006-01-31 00:45:37 +00:00
b521361fb9
add some notes
...
llvm-svn: 25825
2006-01-31 00:20:38 +00:00
45df7f84ff
Don't generate complex sequence for SETOLE, SETOLT, SETULT, and SETUGT. Flip
...
the order of the compare operands and generate SETOGT, SETOGE, SETUGE, and
SETULE instead.
llvm-svn: 25824
2006-01-30 23:41:35 +00:00
9a90572374
Fix FP constants, and the SparcV8/2006-01-22-BitConvertLegalize.ll failure from last night
...
llvm-svn: 25819
2006-01-30 22:20:49 +00:00
08390f6a21
i64 -> f32, f32 -> i64 and some clean up.
...
llvm-svn: 25818
2006-01-30 22:13:22 +00:00
5b97fcf0f5
Always use FP stack instructions to perform i64 to f64 as well as f64 to i64
...
conversions. SSE does not have instructions to handle these tasks.
llvm-svn: 25817
2006-01-30 08:02:57 +00:00
37faeb2b02
Revamp the ICC/FCC reading instructions to be parameterized in terms of the
...
SPARC condition codes, not in terms of the DAG condcodes. This allows us to
write nice clean patterns for cmovs/branches.
llvm-svn: 25815
2006-01-30 07:43:04 +00:00
33a79cae7c
Compile:
...
uint %test(uint %X) {
%Y = call uint %llvm.ctpop.i32(uint %X)
ret uint %Y
}
to:
test:
save -96, %o6, %o6
sll %i0, 0, %l0
popc %l0, %i0
restore %g0, %g0, %g0
retl
nop
instead of to 40 logical ops. Note the shift-by-zero that clears the top
part of the 64-bit V9 register.
Testcase here: CodeGen/SparcV8/ctpop.ll
llvm-svn: 25814
2006-01-30 06:14:02 +00:00
321e337d95
If the target has V9 instructions, this pass is a noop, don't bother
...
running it.
llvm-svn: 25811
2006-01-30 05:51:14 +00:00
90d3fd9e7c
When in v9 mode, emit fabsd/fnegd/fmovd
...
llvm-svn: 25810
2006-01-30 05:48:37 +00:00
99dcb95e14
First step towards V9 instructions in the V8 backend, two conditional move
...
patterns. This allows emission of this code:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
move %icc, %i0, %i2
or %g0, %i2, %i0
restore %g0, %g0, %g0
retl
nop
instead of this:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
be .LBBt1_2 !
nop
.LBBt1_1: !
or %g0, %i2, %i0
.LBBt1_2: !
restore %g0, %g0, %g0
retl
nop
for this:
int %t1(int %a, int %b, int %c) {
%tmp.2 = seteq int %a, %b
%tmp3 = select bool %tmp.2, int %a, int %c
ret int %tmp3
}
llvm-svn: 25809
2006-01-30 05:35:57 +00:00
238fe93242
Two changes:
...
1. Default to having V9 instructions, instead of just V8.
2. unless -enable-sparc-v9-insts is passed, disable V9 (for use with llcbeta)
llvm-svn: 25807
2006-01-30 04:57:43 +00:00
af209b8b13
When lowering SELECT_CC, see if the input is a lowered SETCC. If so, fold
...
the two operations together. This allows us to compile this:
void %two(int %a, int* %b) {
%tmp.2 = seteq int %a, 0
%tmp.0.0 = select bool %tmp.2, int 10, int 20
store int %tmp.0.0, int* %b
ret void
}
into:
two:
save -96, %o6, %o6
or %g0, 20, %l0
or %g0, 10, %l1
subcc %i0, 0, %l2
be .LBBtwo_2 ! entry
nop
.LBBtwo_1: ! entry
or %g0, %l0, %l1
.LBBtwo_2: ! entry
st %l1, [%i1]
restore %g0, %g0, %g0
retl
nop
instead of:
two:
save -96, %o6, %o6
sethi 0, %l0
or %g0, 1, %l1
or %g0, 20, %l2
or %g0, 10, %l3
subcc %i0, 0, %l4
be .LBBtwo_2 ! entry
nop
.LBBtwo_1: ! entry
or %g0, %l0, %l1
.LBBtwo_2: ! entry
subcc %l1, 0, %l0
bne .LBBtwo_4 ! entry
nop
.LBBtwo_3: ! entry
or %g0, %l2, %l3
.LBBtwo_4: ! entry
st %l3, [%i1]
restore %g0, %g0, %g0
retl
nop
llvm-svn: 25806
2006-01-30 04:34:44 +00:00
f0b24d2dc0
Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler.
...
llvm-svn: 25803
2006-01-30 04:09:27 +00:00
4ac0fa2aa5
Implement isMaskedValueZeroForTargetNode for the various v8 selectcc nodes,
...
allowing redundant and's to be eliminated by the dag combiner.
llvm-svn: 25800
2006-01-30 03:51:45 +00:00
c6fa0282d2
adjust prototype
...
llvm-svn: 25798
2006-01-30 03:49:07 +00:00
32058cfb7b
Functions that are lazily streamed in from the .bc file are *not* external.
...
This fixes llvm-test/SingleSource/UnitTests/2006-01-29-SimpleIndirectCall.c
and PR704
llvm-svn: 25793
2006-01-29 20:49:17 +00:00
3c6a950653
add another note
...
llvm-svn: 25789
2006-01-29 09:46:06 +00:00
dabee1f655
add some performance notes from looking at sgefa
...
llvm-svn: 25788
2006-01-29 09:42:20 +00:00
7c7cbde0e5
add a high-priority SSE issue from sgefa
...
llvm-svn: 25787
2006-01-29 09:14:47 +00:00
5a7a22c9dd
add a missed optimization
...
llvm-svn: 25786
2006-01-29 09:08:15 +00:00
3072af4d4f
Now that OpActions is big enough, we can specify actions for vector types
...
llvm-svn: 25784
2006-01-29 08:41:37 +00:00
8a4a3deaf9
clean up interface to ValueTypeActions
...
llvm-svn: 25783
2006-01-29 08:41:12 +00:00
d7738e6b32
disable this for now
...
llvm-svn: 25778
2006-01-29 07:31:33 +00:00
0c05a2c99c
Add a note about lowering llvm.memset, llvm.memcpy, and llvm.memmove to a
...
few stores under certain conditions.
llvm-svn: 25777
2006-01-29 06:48:25 +00:00
35d20a4c00
remove now-dead code, the legalizer takes care of this for us
...
llvm-svn: 25776
2006-01-29 06:45:31 +00:00
132177e103
The FP stack doesn't support UNDEF, ask the legalizer to legalize it
...
instead of lying and saying we have it.
llvm-svn: 25775
2006-01-29 06:44:22 +00:00
d33c60b52b
Request expansion of ConstantVec nodes.
...
llvm-svn: 25773
2006-01-29 06:32:58 +00:00
61c9a8e942
Targets all now request ConstantFP to be legalized into TargetConstantFP.
...
'fpimm' in .td files is now TargetConstantFP.
llvm-svn: 25771
2006-01-29 06:26:08 +00:00
b5f0ba6051
Update alpha to reflect recent constantfp legalize changes. It's not clear
...
why all this code isn't autogenerated. :(
llvm-svn: 25770
2006-01-29 06:25:22 +00:00
1b09c6ba87
cmovle != cmovlt
...
llvm-svn: 25761
2006-01-29 03:47:30 +00:00
4ab39e43e8
Fix typo.
...
llvm-svn: 25760
2006-01-29 03:45:35 +00:00
8643ea67b1
Flesh out AMD family/models.
...
llvm-svn: 25755
2006-01-28 20:30:18 +00:00
58ca0be9af
Correctly determine CPU vendor.
...
llvm-svn: 25754
2006-01-28 19:48:34 +00:00
71287085a1
Use union instead of reinterpret_cast.
...
llvm-svn: 25751
2006-01-28 18:47:32 +00:00
b5de47cd9a
Fix recognition of Intel CPUs.
...
llvm-svn: 25750
2006-01-28 18:38:20 +00:00
b3ab2d3a42
Is64Bit reflects the capability of the chip, not an aspect of the target os
...
llvm-svn: 25749
2006-01-28 18:23:48 +00:00
be08957dc5
Fix a bunch of JIT failures with the new isel
...
llvm-svn: 25748
2006-01-28 18:19:37 +00:00
e128d5f724
Improve X86 subtarget support for Windows and AMD.
...
llvm-svn: 25747
2006-01-28 18:09:06 +00:00
ccd2a20c4b
silence a warning
...
llvm-svn: 25745
2006-01-28 10:34:47 +00:00
30432e07f0
Fix a bug in my elimination of ISD::CALL this morning. PPC now has to
...
provide the expansion for i64 calls itself
llvm-svn: 25735
2006-01-28 07:33:03 +00:00
dc8bbb6527
make this work on non-native hosts
...
llvm-svn: 25734
2006-01-28 06:05:41 +00:00
0c7b4666a3
add a note about how we should implement this FIXME from the legalizer:
...
// FIXME: revisit this when we have some kind of mechanism by which targets
// can decided legality of vector constants, of which there may be very
// many.
llvm-svn: 25733
2006-01-28 05:40:47 +00:00
595ec734fc
Implement Promote for VAARG, and allow it to be custom promoted for people
...
who don't want the default behavior (Alpha).
llvm-svn: 25726
2006-01-28 03:14:31 +00:00
6c82262289
Add a couple more things to the readme.
...
llvm-svn: 25724
2006-01-28 01:22:10 +00:00
b292de6703
Remove some dead code
...
llvm-svn: 25719
2006-01-28 00:02:51 +00:00
2c00db82bd
Switch to AlphaISD::CALL instead of ISD::CALL
...
llvm-svn: 25718
2006-01-27 23:39:00 +00:00
f424a66524
Use PPCISD::CALL instead of ISD::CALL
...
llvm-svn: 25717
2006-01-27 23:34:02 +00:00
a9382ca59e
Use V8ISD::CALL instead of ISD::CALL
...
llvm-svn: 25716
2006-01-27 23:30:03 +00:00
18243826fd
A bit of wisdom from Chris on the last entry.
...
llvm-svn: 25715
2006-01-27 22:54:32 +00:00
63045d221b
AT&T assembly convention: registers are in lower case.
...
llvm-svn: 25714
2006-01-27 22:53:29 +00:00
a502b93fae
initialize member vars
...
llvm-svn: 25712
2006-01-27 22:38:36 +00:00
dbfc299915
initialize all instance vars
...
llvm-svn: 25711
2006-01-27 22:37:09 +00:00
4d967a4cbb
Make llvm.frame/returnaddr not crash on ppc
...
llvm-svn: 25710
2006-01-27 22:25:06 +00:00
9857d075b5
Added notes about a x86 isel deficiency.
...
llvm-svn: 25706
2006-01-27 22:11:01 +00:00
1073ae07b0
Added a temporary option -enable-x86-sse to enable sse support. It is used by
...
llc-beta.
llvm-svn: 25701
2006-01-27 21:49:34 +00:00
a814f0b31c
Bye bye Pattern ISel, hello DAG ISel.
...
llvm-svn: 25700
2006-01-27 21:26:54 +00:00
8c47c3a3b1
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
...
the same functionality. This addresses another piece of bug 680. Next,
on to fixing Alpha VAARG, which I broke last time.
llvm-svn: 25696
2006-01-27 21:09:22 +00:00
afab7aa8f2
A better workaround
...
llvm-svn: 25692
2006-01-27 19:30:30 +00:00
4be147f456
force sse/3dnow off until they work. This fixes all the x86 failures last night
...
llvm-svn: 25690
2006-01-27 18:30:50 +00:00
ed2bb8562f
Unbreak the JIT with SSE
...
llvm-svn: 25688
2006-01-27 18:27:18 +00:00
cde9e30bc6
x86 CPU detection and proper subtarget support
...
llvm-svn: 25679
2006-01-27 08:10:46 +00:00
d98701c639
Subtarget feature can now set any variable to any value
...
llvm-svn: 25678
2006-01-27 08:09:42 +00:00
1240574609
PHI and INLINEASM are now built-in instructions provided by Target.td
...
llvm-svn: 25674
2006-01-27 01:46:15 +00:00
1c341ac1fe
Add a default NoItinerary class for targets to use.
...
llvm-svn: 25670
2006-01-27 01:41:38 +00:00
15a8c15a1f
Improve compatibility with VC2005, patch by Morten Ofstad!
...
llvm-svn: 25661
2006-01-26 20:41:32 +00:00
32fef53f5c
Implement a method for inline asm support
...
llvm-svn: 25660
2006-01-26 20:37:03 +00:00
0bbdc55333
Set up MachineDebugInfo to scan for debug information form "llvm.db"g globals.
...
Global Variable information is now pulled from "llvm.dbg.globals"
llvm-svn: 25655
2006-01-26 20:21:46 +00:00
ebbfb386a5
Improve compatibility with VC2005, patch by Morten Ofstad!
...
llvm-svn: 25653
2006-01-26 19:55:20 +00:00
54c13da29c
Added preliminary x86 subtarget support.
...
llvm-svn: 25645
2006-01-26 09:53:06 +00:00
0ebb0b1c5c
fix stack corruption! Previously, 16-byte whole-FP-register stores were
...
being treated as needing only 8 bytes (though they were 16 byte aligned.)
This should fix a bunch of tests - anyone have any comments, though?
- in Target.td , SpillSize and SpillAlignment seem dead - is this what
Size and Alignment do now?
- in CodeGenRegisters.h/CodeGenTarget.cpp , DeclaredSpillSize and
DeclaredSpillAlignment seem dead.
- there are a bunch of comments here and there that don't clearly
distinguish between 'size' and 'spillsize' etc. hmm.
llvm-svn: 25644
2006-01-26 09:45:03 +00:00
c090ac13bd
some hoovering
...
llvm-svn: 25643
2006-01-26 09:08:31 +00:00
dbc2aac1e7
Rest of subtarget support, remove references to ppc
...
llvm-svn: 25642
2006-01-26 07:22:22 +00:00
e6842a9da6
Add trivial subtarget support
...
llvm-svn: 25641
2006-01-26 06:51:21 +00:00
0a01374299
minor renaming
...
llvm-svn: 25640
2006-01-26 03:24:15 +00:00
153f808f53
allow R28 to be used for frame calculations without entirely removing it from circulation
...
llvm-svn: 25639
2006-01-26 03:22:07 +00:00
fcdce6d26f
Work around some x86 Darwin assembler bugs
...
llvm-svn: 25638
2006-01-26 02:27:43 +00:00
944d1e91ea
When trying to fold X86::SETCC into a Select, make a copy if it has more than
...
one use. This allows more CMOV instructions.
llvm-svn: 25634
2006-01-26 02:13:10 +00:00
97c68f0f5c
Remove the uses of STATUS flag register. Rely on node property SDNPInFlag,
...
SDNPOutFlag, and SDNPOptInFlag instead.
llvm-svn: 25629
2006-01-26 00:29:36 +00:00
5c3dd5fafd
oops
...
llvm-svn: 25623
2006-01-25 23:33:32 +00:00
a852660e74
forgot one
...
llvm-svn: 25620
2006-01-25 22:28:07 +00:00
93fd315292
make things compile again
...
llvm-svn: 25614
2006-01-25 21:54:38 +00:00
d07c86465d
initialize an instance var, apparently I forgot to commit this long ago
...
llvm-svn: 25609
2006-01-25 18:57:15 +00:00
030e002fb9
Set SchedulingForLatency to be the default scheduling preference for all.
...
llvm-svn: 25607
2006-01-25 18:52:42 +00:00
e74795cd70
First part of bug 680:
...
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
llvm-svn: 25606
2006-01-25 18:21:52 +00:00
1092a02619
Default scheduling preference is SchedulingForLatency.
...
llvm-svn: 25603
2006-01-25 09:15:54 +00:00
83eeefbbd1
X86 prefer scheduling for reduced register pressure.
...
llvm-svn: 25602
2006-01-25 09:15:17 +00:00
aff0800fd1
Fix a selectcc lowering bug. Make a copy of X86ISD::CMP when folding it.
...
llvm-svn: 25596
2006-01-25 09:05:09 +00:00
bc7226a7cc
Loosen up these checks to allow direct uses of ESP
...
llvm-svn: 25595
2006-01-25 08:00:36 +00:00
5ea06a9f13
add bundling! well not really, for now it's just stop-insertion.
...
llvm-svn: 25593
2006-01-25 02:23:38 +00:00
94150f0666
maintaining stackpointer alignment. Perhaps it doesn't matter
...
llvm-svn: 25592
2006-01-25 01:51:08 +00:00
27d30a5f42
use ESP directly, not a copy of ESP into some other register for fastcc calls
...
llvm-svn: 25584
2006-01-24 06:14:44 +00:00
6f33eaeb81
Emit the copies out of call return registers *after* the ISD::CALLSEQ_END
...
node, fixing fastcc and the case where a function has a frame pointer due
to dynamic allocas.
llvm-svn: 25580
2006-01-24 05:17:12 +00:00
68e62a5184
Allow jit-beta to work
...
llvm-svn: 25578
2006-01-24 04:50:48 +00:00
3e65f28ffe
Crude Dwarf global variable debugging.
...
llvm-svn: 25569
2006-01-24 00:49:18 +00:00
c0bf377f98
bye bye Pattern ISEL
...
llvm-svn: 25553
2006-01-23 21:56:07 +00:00
fef7dec9cc
added stores to lsmark
...
llvm-svn: 25552
2006-01-23 21:51:33 +00:00
208bbe9ca9
fix up more lsmark stuff
...
llvm-svn: 25550
2006-01-23 21:23:26 +00:00
ba97ea52d4
yea, lowering this stuff will basically work
...
llvm-svn: 25549
2006-01-23 20:59:50 +00:00
8935e3eb7d
remove the V8 simple isel
...
llvm-svn: 25534
2006-01-23 07:20:15 +00:00
37c8ad14f4
die, die!! r15, you are not callee-saved
...
llvm-svn: 25527
2006-01-23 06:11:45 +00:00
cc87402925
fix register corruption! (my god.) r15 is a scratch reg, using that as
...
a frame pointer is a pretty doofus thing to do. use r5 instead, and
mark it callee-saved, coz that's what it is!
llvm-svn: 25526
2006-01-23 06:08:46 +00:00
de02d7727f
Add explicit #includes of <iostream>
...
llvm-svn: 25515
2006-01-22 23:41:00 +00:00
469640e506
Add explicit #includes of <iostream>
...
llvm-svn: 25509
2006-01-22 22:53:01 +00:00
4204e02fc6
insignificant, but next up is proper stack frame layout!
...
llvm-svn: 25497
2006-01-21 14:27:19 +00:00
468fecdc99
Rename fcmovae to fcmovnb and fcmova to fcmovnbe (following Intel manual).
...
Some assemblers can't recognize the aliases.
llvm-svn: 25494
2006-01-21 02:55:41 +00:00
9436aa74a9
trivial formatting improvement: don't insert extra blank lines between .comm
...
vars.
llvm-svn: 25492
2006-01-21 01:35:26 +00:00
4b41c8e929
Make the C writer work with packed types. printContainedStructs is
...
still not quite right and will be fixed later.
llvm-svn: 25488
2006-01-20 20:43:57 +00:00
f54c9395e7
remove RET hack, add proper support for rets (watching out for ret voids)
...
llvm-svn: 25486
2006-01-20 20:24:31 +00:00
eca87342b4
Simplify CWriter::printContainedStructs, also allowing it to work with
...
PackedTypes as a side-effect.
llvm-svn: 25485
2006-01-20 18:57:03 +00:00
335b46dd20
LowerReturn now doesn't have to handle f32 returns.
...
llvm-svn: 25484
2006-01-20 18:41:25 +00:00
4026e12e85
fix sext breakage: now we correctly deal with functions that return
...
int vs uint
llvm-svn: 25478
2006-01-20 16:10:05 +00:00
9a8fb20689
fix storing bools! eek!
...
llvm-svn: 25476
2006-01-20 03:40:25 +00:00
0c5de2864f
Stop doing that accidental commit.
...
llvm-svn: 25474
2006-01-20 01:14:05 +00:00
cce748d316
A few more SH{L|R}D peepholes.
...
llvm-svn: 25473
2006-01-20 01:13:30 +00:00
9c30bd5e25
Didn't mean to commit the last one.
...
llvm-svn: 25469
2006-01-19 23:27:08 +00:00
8591b9f254
Added i16 SH{L|R}D patterns.
...
llvm-svn: 25468
2006-01-19 23:26:24 +00:00
5df67bcd50
typo
...
llvm-svn: 25464
2006-01-19 21:10:38 +00:00
688ea707d8
nasty nasty patterns
...
llvm-svn: 25463
2006-01-19 20:49:37 +00:00
550d8ec1ad
fix boolean XOR (which fixes up comparisons..)
...
llvm-svn: 25462
2006-01-19 15:18:56 +00:00
4d69a01254
BOOM!
...
llvm-svn: 25460
2006-01-19 14:14:11 +00:00
bcbcfac6ea
click click
...
llvm-svn: 25459
2006-01-19 14:13:11 +00:00
3d2cc7e2e9
Avoid generating a redundant setcc.
...
llvm-svn: 25457
2006-01-19 08:52:46 +00:00
29b9d7cdff
fix calls that return f32
...
llvm-svn: 25455
2006-01-19 08:31:51 +00:00
2efef3d6f1
implement support for f32 arguments past the first 6 words
...
llvm-svn: 25450
2006-01-19 07:22:29 +00:00
91007126c2
adc and sbb need an incoming flag to ensure it reads the carry flag
...
from add / sub.
llvm-svn: 25444
2006-01-19 06:53:20 +00:00
c3c27032d0
add a note
...
llvm-svn: 25439
2006-01-19 02:09:38 +00:00
a7bfbe996e
Two peepholes:
...
(or (x >> c) | (y << (32 - c))) ==> (shrd x, y, c)
(or (x << c) | (y >> (32 - c))) ==> (shld x, y, c)
llvm-svn: 25438
2006-01-19 01:56:29 +00:00
6135a7a546
Didn't mean to check that in.
...
llvm-svn: 25436
2006-01-19 01:52:56 +00:00
267ba5965e
A obvious typo
...
llvm-svn: 25435
2006-01-19 01:46:14 +00:00
ce5066c863
Don't assert on 'select_cc SETUO'
...
llvm-svn: 25423
2006-01-18 19:42:35 +00:00
36eba3a49b
fix out of date comment
...
llvm-svn: 25422
2006-01-18 19:37:44 +00:00
15e7642ab1
Fix Regression/CodeGen/PowerPC/2006-01-18-InvalidBranchOpcodeAssert.ll
...
llvm-svn: 25421
2006-01-18 19:35:21 +00:00
194a5268cb
Added minimum Dwarf aranges. Cleaned up some section headers. Line number
...
support now works in gdb.
llvm-svn: 25417
2006-01-18 16:54:26 +00:00
621674a19d
SRA shift amount must be in i8
...
llvm-svn: 25416
2006-01-18 09:26:46 +00:00
4b3774e0a2
If a call return type is i1, insert a truncate from X86::AL to i1.
...
llvm-svn: 25415
2006-01-18 08:08:38 +00:00
feaed4d107
Fix lowering of calls which return f32 values.
...
llvm-svn: 25413
2006-01-17 21:58:21 +00:00
cc9dfecf81
Add frame work for additional dwarf sections. Comments will improve as code
...
is added.
llvm-svn: 25410
2006-01-17 20:41:40 +00:00
b9966029fe
Adding basic support for Dwarf line number debug information.
...
I promise to keep future commits smaller.
llvm-svn: 25396
2006-01-17 17:31:53 +00:00
14417ed99c
Zero extending load from i1 to i8.
...
llvm-svn: 25391
2006-01-17 07:02:46 +00:00
e08a95d3c1
oops, this shouldn't have gotten in
...
llvm-svn: 25388
2006-01-17 03:09:48 +00:00
0d5b69f734
SSE does not support i64 SINT_TO_FP (FP stack doesn't either, but we custom
...
expand it), so ask legalizer to expand i32 UINT_TO_FP.
llvm-svn: 25386
2006-01-17 02:32:49 +00:00
266ff6056a
use proper (82-bit) spills/fills when spilling FP regs, so that
...
divides don't get broken. this fixes obsequi, smg2000, and probably
a bunch of other stuff (tm)
llvm-svn: 25385
2006-01-17 02:04:52 +00:00
c261469ad9
fixing divides
...
llvm-svn: 25383
2006-01-17 01:19:49 +00:00
561881f30a
Added a FIXME comment about why FST is currently flagged to fpGETRESULT.
...
llvm-svn: 25381
2006-01-17 00:37:42 +00:00
bec9d720b0
Bug fixes: fpGETRESULT should produces a flag result and X86ISD::FST should
...
read a flag.
llvm-svn: 25378
2006-01-17 00:19:47 +00:00
c14bb1026b
More typo's
...
llvm-svn: 25375
2006-01-16 23:26:53 +00:00
64eeed27d9
Some typo's
...
llvm-svn: 25374
2006-01-16 22:48:46 +00:00
cfd9c6e526
fix short immediate loads
...
llvm-svn: 25371
2006-01-16 21:41:39 +00:00
34380b7675
stack and rpcc
...
llvm-svn: 25369
2006-01-16 21:22:38 +00:00
911c68d7a8
Fix FP_TO_INT**_IN_MEM lowering.
...
llvm-svn: 25368
2006-01-16 21:21:29 +00:00
81b108c54d
Friendly names
...
llvm-svn: 25364
2006-01-16 19:53:25 +00:00
7c76290038
add notes from my *other* email acct.
...
llvm-svn: 25362
2006-01-16 17:58:54 +00:00
b2eacf48aa
transfer some notes from my email to somewhere useful.
...
llvm-svn: 25361
2006-01-16 17:53:00 +00:00
e995910e64
fixing divides: FP should now be 100%, and integers are fine too
...
unless you try to div/mod 0 by anything, in which case you will
get some cute number, and not 0, which is bad.
llvm-svn: 25358
2006-01-16 14:33:04 +00:00
ba187774fe
fix division! again!! pattern isel, prepare to die.
...
llvm-svn: 25353
2006-01-16 06:33:38 +00:00
e636ba84b5
Silly Sparc is big endian. If we have to load args out of incoming stack slots
...
that are smaller than an int, make sure to adjust the frame pointer to take
this into consideration.
llvm-svn: 25351
2006-01-16 01:40:00 +00:00
9d41ecc95b
Make sure that bool,byte and short arguments are the right type when loaded
...
from memory.
llvm-svn: 25346
2006-01-15 22:22:01 +00:00
53312c6342
Disable a broken optimization
...
llvm-svn: 25340
2006-01-15 19:15:46 +00:00
2494ce49f0
Added patterns for 8-bit multiply
...
llvm-svn: 25338
2006-01-15 10:05:20 +00:00
c8817d2857
explain that r12 is the stack pointer reg
...
llvm-svn: 25336
2006-01-15 09:45:23 +00:00
e96523474b
Don't print a label for the first MBB in a function.
...
Compile this:
%_2E_str_8 = external global [75 x sbyte]
implementation ; Functions:
declare int %printf(sbyte*, ...)
void %test()
%tmp.101 = call int (sbyte*, ...)* %printf( sbyte* getelementptr ([75 x sbyte]* %_2E_str_8, int 0, int 0) ) ; <int> [#uses=0]
unreachable
}
to this:
main_endif_2E_8:
save -96, %o6, %o6
sethi %hi(_2E_str_8), %l0
add %l0, %lo(_2E_str_8), %o0
call printf
nop
instead of this:
main_endif_2E_8:
save -96, %o6, %o6
sethi %hi(_2E_str_8), %l0
or %g0, %lo(_2E_str_8), %l1 ;; extra instruction
add %l1, %l0, %o0
call printf
nop
llvm-svn: 25335
2006-01-15 09:26:27 +00:00
5bd514d7b0
Use the default impl of DYNAMIC_STACKALLOC, allowing us to delete some code.
...
llvm-svn: 25334
2006-01-15 09:02:48 +00:00
78c358d1ad
Use the default lowering of ISD::DYNAMIC_STACKALLOC, delete now dead code.
...
llvm-svn: 25333
2006-01-15 09:00:21 +00:00
aea3cccd55
Have legalize take care of DYNAMIC_STACKALLOC for us, implement llvm.stacksave/stackrestore.
...
llvm-svn: 25332
2006-01-15 08:55:25 +00:00
c5101b4ffa
Implement DYNAMIC_STACKALLOC for V8
...
llvm-svn: 25330
2006-01-15 08:43:57 +00:00
e5ca28b74d
reorder passes
...
llvm-svn: 25326
2006-01-15 07:19:53 +00:00
c17b41c3ba
Cleanup IA64ISD, tell the graph drawer what the symbolic names for the enums are.
...
llvm-svn: 25324
2006-01-14 22:27:21 +00:00
8869c6f782
silence a warning
...
llvm-svn: 25322
2006-01-14 20:11:13 +00:00
2fba8a3aaa
bswap implementation
...
llvm-svn: 25312
2006-01-14 03:14:10 +00:00
f2b38dbdc7
Remove some redundant stuff out of the readme.
...
llvm-svn: 25308
2006-01-14 01:24:22 +00:00
3bc25e8a54
A typo.
...
llvm-svn: 25307
2006-01-14 01:18:49 +00:00
a4de9baf40
Implement a new InvalidateStructLayoutInfo method and add some comments
...
llvm-svn: 25304
2006-01-14 00:07:34 +00:00
392c7d2779
Add truncstore i1 patterns.
...
llvm-svn: 25296
2006-01-13 21:45:19 +00:00
5f9c134bac
Fix a bug in my last X86 checkin, pointed out by cozmic
...
llvm-svn: 25293
2006-01-13 20:19:44 +00:00
dba84bbc1e
LHS = X86ISD::CMOVcc LHS, RHS means LHS = RHS if cc. So the operands must be
...
flipped around.
llvm-svn: 25290
2006-01-13 19:51:46 +00:00
045371a744
make DAG isel the default
...
llvm-svn: 25282
2006-01-13 18:49:47 +00:00
1a8d918ef1
Enable X86 support for savestack/restorestack
...
llvm-svn: 25278
2006-01-13 18:00:54 +00:00
776c326c96
implement stacksave/stackrestore on PPC
...
llvm-svn: 25277
2006-01-13 17:52:03 +00:00
0b94324c5e
don't be a doofus - this fixes storing bools
...
llvm-svn: 25274
2006-01-13 10:28:25 +00:00
8e2f52e645
expand unsupported stacksave/stackrestore nodes
...
llvm-svn: 25272
2006-01-13 02:42:53 +00:00
fdc6d1ea69
new nodes
...
llvm-svn: 25271
2006-01-13 02:40:58 +00:00
f00374e4a8
Minor update.
...
llvm-svn: 25263
2006-01-13 01:20:42 +00:00
d7faa4bae1
More typo's. I need new eye glasses...
...
llvm-svn: 25261
2006-01-13 01:17:24 +00:00
731423f36a
Oops. Typo.
...
llvm-svn: 25260
2006-01-13 01:06:49 +00:00
fb22e86c4d
Fix a SETCC / BRCOND folding bug.
...
llvm-svn: 25259
2006-01-13 01:03:02 +00:00
6305e50ee1
Fix sint_to_fp (fild*) support.
...
llvm-svn: 25257
2006-01-12 22:54:21 +00:00
c993d4522d
Specify transformation from GlobalAddress to TargetGlobalAddress and
...
ExternalSymbol to TargetExternalSymbol.
llvm-svn: 25253
2006-01-12 19:36:31 +00:00
556f14a6cb
Fix branches on FP compares
...
llvm-svn: 25249
2006-01-12 17:05:32 +00:00
84dc9b55f0
X86ISD::SETCC (e.g. SETEr) produces a flag (so multiple SETCC can be
...
linked together).
llvm-svn: 25247
2006-01-12 08:27:59 +00:00
b94db9e9a4
* Materialize GlobalAddress and ExternalSym with MOV32ri rather than
...
LEA32r.
* Do not lower GlobalAddress to TargetGlobalAddress. Let isel does it.
llvm-svn: 25246
2006-01-12 07:56:47 +00:00
fd41d94486
fix a bug in my previous checkin
...
llvm-svn: 25244
2006-01-12 07:38:04 +00:00
071c9637c3
Give V8ISD nodes symbolic names in dumps
...
llvm-svn: 25243
2006-01-12 07:31:15 +00:00
84be729a56
sabre's (correct) fix means these guys need to be flagged as well (else
...
the scheduler will complain)
llvm-svn: 25241
2006-01-12 03:28:40 +00:00
268d3584fc
ahem :)
...
llvm-svn: 25239
2006-01-12 02:05:36 +00:00
1014b38404
these cases are autogenerated
...
llvm-svn: 25238
2006-01-12 02:01:45 +00:00
44416f92f1
remove dead code
...
llvm-svn: 25237
2006-01-12 01:54:15 +00:00
33792a483a
Goodbye PPC pattern isel. You have served us well, but it is now time for
...
you to ride off into the sunset.
llvm-svn: 25236
2006-01-12 01:46:07 +00:00
9d5e4e8f3c
Fix an itanium call lowering bug for duraid
...
llvm-svn: 25235
2006-01-12 01:33:08 +00:00
504b63c873
invert the sense of this switch and its name
...
llvm-svn: 25234
2006-01-12 01:28:56 +00:00
6b9e00dedc
Missed a spot.
...
llvm-svn: 25233
2006-01-11 23:20:28 +00:00
6d2ab04463
Added ROTL and ROTR.
...
llvm-svn: 25232
2006-01-11 23:20:05 +00:00
2812e79c23
Fix an off-by-one error that Nate's eagle eyes caught
...
llvm-svn: 25231
2006-01-11 23:16:29 +00:00
dc43a3f237
Use the auto-insert BuildMI constructor to avoid an explicit insert. No
...
functionality change, just code cleanup.
llvm-svn: 25230
2006-01-11 23:07:57 +00:00
3280da3cda
If a function has a non-zero sized frame, use an add to adjust the stack
...
pointer in the epilog, not a load.
llvm-svn: 25229
2006-01-11 23:03:54 +00:00
ae986f1f1e
Support for MEMCPY and MEMSET.
...
llvm-svn: 25226
2006-01-11 22:15:48 +00:00
2ae799aff0
Select DYNAMIC_STACKALLOC
...
llvm-svn: 25225
2006-01-11 22:15:18 +00:00
1b8121b227
Add bswap, rotl, and rotr nodes
...
Add dag combiner code to recognize rotl, rotr
Add ppc code to match rotl
Targets should add rotl/rotr patterns if they have them
llvm-svn: 25222
2006-01-11 21:21:00 +00:00
602dfea79c
Fix calls that need to store values in stack slots, to not copy the stack
...
pointer. This allows us to emit stuff like this:
li r10, 0
stw r10, 56(r1)
or r3, r10, r10
or r4, r10, r10
or r5, r10, r10
or r6, r10, r10
or r7, r10, r10
or r8, r10, r10
or r9, r10, r10
bl L_bar$stub
instead of this:
or r2, r1, r1 ;; Extraneous copy.
li r10, 0
stw r10, 56(r2)
or r3, r10, r10
or r4, r10, r10
or r5, r10, r10
or r6, r10, r10
or r7, r10, r10
or r8, r10, r10
or r9, r10, r10
bl L_bar$stub
wowness.
llvm-svn: 25221
2006-01-11 19:55:07 +00:00
eaf94a8d2e
tblgen does this now
...
llvm-svn: 25220
2006-01-11 19:53:22 +00:00
b41e92b04c
This is no longer needed
...
llvm-svn: 25219
2006-01-11 19:52:46 +00:00
66f63f72f3
Dead FP arguments still use an incoming FP reg. This fixes
...
Regression/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll, which was
distilled from a miscompilation in 252.eon.
llvm-svn: 25217
2006-01-11 18:21:25 +00:00
41c7f4a9ce
Use Evan's outflag stuff to implement V8cmpicc. This allows us to write a
...
pattern for SUBCCrr, and makes it trivial to add support for SUBCCri, eliminating
an instruction in the common "setcc X, imm" case.
llvm-svn: 25212
2006-01-11 07:49:38 +00:00
caf4d92f85
Fix a bug in i32->f64 conversion lowering
...
llvm-svn: 25211
2006-01-11 07:27:40 +00:00
d3839c74d6
Unbreak ret void :-/
...
llvm-svn: 25210
2006-01-11 07:15:43 +00:00
8e0bee11e3
Write this pattern in canonical form, allowing more patterns to match.
...
This implements Regression/CodeGen/SparcV8/xnor.ll
llvm-svn: 25209
2006-01-11 07:14:01 +00:00
bc7a0f44bd
* Add special entry code main() (to set x87 to 64-bit precision).
...
* Allow a register node as SelectAddr() base.
* ExternalSymbol -> TargetExternalSymbol as direct function callee.
* Use X86::ESP register rather than CopyFromReg(X86::ESP) as stack ptr for
call parmater passing.
llvm-svn: 25207
2006-01-11 06:09:51 +00:00
0302e62296
cleanup GETFD
...
llvm-svn: 25198
2006-01-11 03:50:40 +00:00
91eda00a7a
this pattern was bogus
...
llvm-svn: 25197
2006-01-11 03:33:06 +00:00
c712fd6b4e
this just might work
...
llvm-svn: 25195
2006-01-11 01:38:07 +00:00
0d5d08b26e
add support for selecting bools
...
FIXME: this is commented out because it makes tblgen go a bit fruity
llvm-svn: 25193
2006-01-11 01:21:12 +00:00
7c551268d0
implement FP_REG_KILL insertion for the dag-dag instruction selector
...
llvm-svn: 25192
2006-01-11 01:15:34 +00:00
29852a58b0
Fit into 80 cols
...
llvm-svn: 25191
2006-01-11 00:46:55 +00:00
339edad775
SSE cmov support.
...
llvm-svn: 25190
2006-01-11 00:33:36 +00:00
efaf5c56fd
* fp to sint patterns.
...
* fiadd, fisub, etc.
llvm-svn: 25189
2006-01-10 22:22:02 +00:00
73a1ad975e
FP_TO_INT*_IN_MEM and x87 FP Select support.
...
llvm-svn: 25188
2006-01-10 20:26:56 +00:00
0fb2ae7d17
silence a bogus warning
...
llvm-svn: 25185
2006-01-10 19:45:18 +00:00
599e73f21c
Int immediate loading fix
...
llvm-svn: 25182
2006-01-10 19:12:47 +00:00
014e8ee806
heh, 'sif it'd be a legalizer bug.
...
llvm-svn: 25172
2006-01-10 05:26:01 +00:00
e977a93bd5
support functions that return bool (this "should" work but doesn't,
...
*maybe* due to a legalizer bug.)
llvm-svn: 25171
2006-01-10 05:08:25 +00:00
477933cfbd
Remove a comment that no longer applies.
...
llvm-svn: 25167
2006-01-10 00:15:59 +00:00
347ed8a581
Give PPCISD:: nodes legible names in dumps.
...
llvm-svn: 25166
2006-01-09 23:52:17 +00:00
bfb2de9030
add ret void support back
...
llvm-svn: 25164
2006-01-09 23:20:37 +00:00
7c4486215f
* Added undef patterns.
...
* Some reorg.
llvm-svn: 25163
2006-01-09 23:10:28 +00:00
12181af0c7
More typos
...
llvm-svn: 25162
2006-01-09 22:29:54 +00:00
77fa9195cd
typo
...
llvm-svn: 25160
2006-01-09 20:49:21 +00:00
32e7d1ed4a
proper branch not equal sequence
...
llvm-svn: 25159
2006-01-09 19:49:58 +00:00
9c249c37f8
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS.
...
llvm-svn: 25158
2006-01-09 18:33:28 +00:00
7785e5b3a4
New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace
...
hasInFlag, hasOutFlag.
llvm-svn: 25155
2006-01-09 18:28:21 +00:00
1185e73cc9
Fix the PPC JIT failures last night, which were due to mishandling of linkonce globals
...
llvm-svn: 25141
2006-01-07 06:22:16 +00:00
Chris Lattner