0eafbc3593
Get JIT/Interpreter working on Windows again.
...
llvm-svn: 27037
2006-03-24 02:53:49 +00:00
a4f6805a86
legalize vbit_convert nodes whose result is a legal type.
...
Legalize intrinsic nodes.
llvm-svn: 27036
2006-03-24 02:26:29 +00:00
d96b09a7b9
Lower target intrinsics into an INTRINSIC node
...
llvm-svn: 27035
2006-03-24 02:22:33 +00:00
f9c3dcfdc1
Ignore the burg output files.
...
llvm-svn: 27033
2006-03-24 02:21:35 +00:00
6b05290922
fix some bogus assertions: noop bitconverts are legal
...
llvm-svn: 27032
2006-03-24 02:20:47 +00:00
d27fb3e85e
Handle more shuffle cases with SHUFP* instructions.
...
llvm-svn: 27024
2006-03-24 01:18:28 +00:00
1d2e995fc1
Lower BUILD_VECTOR to VECTOR_SHUFFLE if there are two distinct nodes (and if
...
the target can handle it). Issue two SCALAR_TO_VECTOR ops followed by a
VECTOR_SHUFFLE to select from the two vectors.
llvm-svn: 27023
2006-03-24 01:17:21 +00:00
ebac9a4adf
Identify the INTRINSIC node
...
llvm-svn: 27020
2006-03-24 01:04:30 +00:00
78eaa10f1a
Add new generated files.
...
llvm-svn: 27013
2006-03-23 23:48:12 +00:00
4b5b4e373b
Typo
...
llvm-svn: 27008
2006-03-23 23:24:51 +00:00
fb39d2a7f7
Unneeded forward.
...
llvm-svn: 27004
2006-03-23 23:05:52 +00:00
f7cfa52e7a
Make sure types are allocated in the scope of their use.
...
llvm-svn: 27002
2006-03-23 23:02:34 +00:00
cbcfe46556
add a note
...
llvm-svn: 27000
2006-03-23 21:28:44 +00:00
d7c4e7d255
add support for splitting casts. This implements
...
CodeGen/Generic/vector.ll:test_cast_2.
llvm-svn: 26999
2006-03-23 21:16:34 +00:00
f842ea57bb
Typo
...
llvm-svn: 26997
2006-03-23 20:26:04 +00:00
b119990289
Add some more bulletproofing to auto upgrade of llvm.dbg intrinsics.
...
llvm-svn: 26996
2006-03-23 20:13:25 +00:00
81137629e0
Add PPC vector bit-convert support
...
llvm-svn: 26995
2006-03-23 19:54:27 +00:00
3c43609f1f
Add support to locate local variables in frames (early version.)
...
llvm-svn: 26994
2006-03-23 18:12:57 +00:00
8f64426f5c
Strip changes to llvm.dbg intrinsics.
...
llvm-svn: 26993
2006-03-23 18:11:33 +00:00
83f99115db
Can't combine anymore - we don't have a chain through llvm.dbg intrinsics.
...
llvm-svn: 26992
2006-03-23 18:10:42 +00:00
cf0166fbeb
Change interface to DwarfWriter.
...
llvm-svn: 26991
2006-03-23 18:09:44 +00:00
267d39d128
Modify how CBE handles #lines.
...
llvm-svn: 26990
2006-03-23 18:08:29 +00:00
2b74656f25
Generate local variable and scope information and equivalent dwarf forms.
...
llvm-svn: 26989
2006-03-23 18:07:55 +00:00
a8bdac875d
Handle new forms of llvm.dbg intrinsics.
...
llvm-svn: 26988
2006-03-23 18:06:46 +00:00
0cf8ed61cc
Simplify handling of llvm.dbg intrinsic operands to one spot.
...
llvm-svn: 26987
2006-03-23 18:05:12 +00:00
01bd749537
Change the argument types of llvm.dbg intrinsics.
...
llvm-svn: 26985
2006-03-23 18:03:20 +00:00
ce0206e119
Fix the encodings of these new instructions, hopefully fixing the JIT
...
failures from last night
llvm-svn: 26981
2006-03-23 16:13:50 +00:00
82ed4a42f9
Following icc's lead: use movdqa to load / store 128-bit integer vectors
...
llvm-svn: 26980
2006-03-23 07:44:07 +00:00
a011ba8a76
prune #includes
...
llvm-svn: 26975
2006-03-23 05:43:58 +00:00
6f95ab7abb
Eliminate IntrinsicLowering from TargetMachine.
...
Make the CBE and V9 backends create their own, since they're the only ones that use it.
llvm-svn: 26974
2006-03-23 05:43:16 +00:00
9ea1b3f9fd
simplify some code
...
llvm-svn: 26972
2006-03-23 05:29:04 +00:00
811dd8d009
remove always-null IntrinsicLowering argument.
...
llvm-svn: 26971
2006-03-23 05:28:02 +00:00
0b2de9f2d4
remove the intrinsiclowering hook
...
llvm-svn: 26970
2006-03-23 05:22:51 +00:00
7055878170
Add v4i32 <-> v4f32 bitconvert patterns.
...
llvm-svn: 26969
2006-03-23 02:36:37 +00:00
b9b0550dc6
Add 128-bit integer vector load and add (for testing).
...
llvm-svn: 26967
2006-03-23 01:57:24 +00:00
fb6e02931c
Add support for 8 bit immediates with 16/32 bit cmp instructions
...
llvm-svn: 26966
2006-03-23 01:29:48 +00:00
b893d04a67
Fix a typo
...
llvm-svn: 26965
2006-03-22 22:20:49 +00:00
021bb7c956
Added a ValueType operand to isShuffleMaskLegal(). For now, x86 will not do
...
64-bit vector shuffle.
llvm-svn: 26964
2006-03-22 22:07:06 +00:00
2f4119a608
Implement simple support for vector casting. This can currently only handle
...
casts between legal vector types.
llvm-svn: 26961
2006-03-22 20:09:35 +00:00
ed794cd27b
SHUFP* are two address code.
...
llvm-svn: 26959
2006-03-22 20:08:18 +00:00
bc04722860
Some clean up.
...
llvm-svn: 26957
2006-03-22 19:22:18 +00:00
d4e1557941
- Supposely movlhps is faster / better than unpcklpd.
...
- Don't forget pshufd is only available with sse2.
llvm-svn: 26956
2006-03-22 19:16:21 +00:00
68ad48bd1a
- Implement X86ISelLowering::isShuffleMaskLegal(). We currently only support
...
splat and PSHUFD cases.
- Clean up shuffle / splat matching code.
llvm-svn: 26954
2006-03-22 18:59:22 +00:00
7d80b4f366
silence a bogus gcc warning
...
llvm-svn: 26953
2006-03-22 17:27:24 +00:00
8fdbdf20cd
- VECTOR_SHUFFLE of v4i32 / v4f32 with undef second vector always matches
...
PSHUFD. We can make permutes entries which point to the undef pointing
anything we want.
- Change some names to appease Chris.
llvm-svn: 26951
2006-03-22 08:01:21 +00:00
e24cf9dfa1
add a note
...
llvm-svn: 26950
2006-03-22 07:33:46 +00:00
3617caf526
Fix PSHUF* and SHUF* jit code emission problems
...
llvm-svn: 26949
2006-03-22 07:10:28 +00:00
2d52c1b8b9
Eliminate the dependency of ExecutionEngine on the JIT/Interpreter libraries.
...
Now you can build a tool with just the JIT or just the interpreter.
llvm-svn: 26946
2006-03-22 06:07:50 +00:00
eccf46950c
This has been implemented. Tweak it into another note
...
llvm-svn: 26944
2006-03-22 05:33:23 +00:00
4a66d69433
When possible, custom lower 32-bit SINT_TO_FP to this:
...
_foo2:
extsw r2, r3
std r2, -8(r1)
lfd f0, -8(r1)
fcfid f0, f0
frsp f1, f0
blr
instead of this:
_foo2:
lis r2, ha16(LCPI2_0)
lis r4, 17200
xoris r3, r3, 32768
stw r3, -4(r1)
stw r4, -8(r1)
lfs f0, lo16(LCPI2_0)(r2)
lfd f1, -8(r1)
fsub f0, f1, f0
frsp f1, f0
blr
This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).
llvm-svn: 26943
2006-03-22 05:30:33 +00:00
77373d1bea
Add support for "ri" addressing modes where the immediate is a 14-bit field
...
which is shifted left two bits before use. Instructions like STD use this
addressing mode.
llvm-svn: 26942
2006-03-22 05:26:03 +00:00
f5e36c8bc0
fix a warning
...
llvm-svn: 26941
2006-03-22 04:18:34 +00:00
d097e67544
Some splat and shuffle support.
...
llvm-svn: 26940
2006-03-22 02:53:00 +00:00
b1d3c64d1f
Add a couple more pseudo instructions.
...
llvm-svn: 26939
2006-03-22 02:52:03 +00:00
8fa445a89d
Endianness does not affect the order of vector fields. This fixes
...
SingleSource/UnitTests/Vector/build.c
llvm-svn: 26936
2006-03-22 01:46:54 +00:00
4e7371758f
Fix the JIT encoding of the VAForm_1 instructions, including vmaddfp
...
llvm-svn: 26935
2006-03-22 01:44:36 +00:00
5be4352124
Enclose some variables in a scope to avoid error with some gcc versions
...
llvm-svn: 26934
2006-03-22 00:12:37 +00:00
baea59c61c
Didn't mean to check this in. No MMX support yet.
...
llvm-svn: 26933
2006-03-21 23:04:23 +00:00
d5e905d762
- Use movaps to store 128-bit vector integers.
...
- Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd.
llvm-svn: 26932
2006-03-21 23:01:21 +00:00
340a6b5c26
add expand support for extractelement
...
llvm-svn: 26931
2006-03-21 21:02:03 +00:00
00f4683bf6
These targets don't support EXTRACT_VECTOR_ELT, though, in time, X86 will.
...
llvm-svn: 26930
2006-03-21 20:51:05 +00:00
7c0cd8cafc
add some trivial support for extractelement.
...
llvm-svn: 26928
2006-03-21 20:44:12 +00:00
3a2ae6ad3c
Don't emit pseudo instructions!
...
llvm-svn: 26926
2006-03-21 20:19:37 +00:00
672a42d731
Add a hacky workaround for crashes due to vectors live across blocks.
...
Note that this code won't work for vectors that aren't legal on the
target. Improvements coming.
llvm-svn: 26925
2006-03-21 19:20:37 +00:00
013127981a
Update readme
...
llvm-svn: 26924
2006-03-21 18:58:20 +00:00
139eac5b71
Print absolute memory references like this:
...
lwz r2, 8(0)
instead of this:
lwz r2, 8(r0)
This fixes the llc/llc-beta failures on PPC last night.
llvm-svn: 26922
2006-03-21 17:21:13 +00:00
2d819f5fa4
Combine 2 entries
...
llvm-svn: 26921
2006-03-21 07:18:26 +00:00
aeebc96099
Add a note about x86 register coallescing
...
llvm-svn: 26920
2006-03-21 07:12:57 +00:00
1208d9179a
- Remove scalar to vector pseudo ops. They are just wrong.
...
- Handle FR32 to VR128:v4f32 and FR64 to VR128:v2f64 with aliases of MOVAPS
and MOVAPD. Mark them as move instructions and *hope* they will be deleted.
llvm-svn: 26919
2006-03-21 07:09:35 +00:00
bda7310ef7
With Evan's latest tblgen patch, this code is obsolete, thanks Evan!
...
llvm-svn: 26917
2006-03-21 06:37:40 +00:00
d2132f87d7
When codegen'ing vector MUL using VFMADD, *add* the 0, don't *mul* the 0.
...
llvm-svn: 26913
2006-03-21 00:51:38 +00:00
f194834161
minor note
...
llvm-svn: 26912
2006-03-21 00:47:09 +00:00
e4d1416239
x86 ISD::SCALAR_TO_VECTOR support.
...
llvm-svn: 26911
2006-03-21 00:33:35 +00:00
fb872b41c0
Junk unused vector register classes.
...
llvm-svn: 26910
2006-03-21 00:30:59 +00:00
c8b16d00b9
Handle constant addresses more efficiently, folding the low bits into the
...
disp field of the load/store if possible. This compiles
CodeGen/PowerPC/load-constant-addr.ll to:
_test:
lis r2, 2838
lfs f1, 26848(r2)
blr
instead of:
_test:
lis r2, 2838
ori r2, r2, 26848
lfs f1, 0(r2)
blr
llvm-svn: 26908
2006-03-20 22:38:22 +00:00
6d74b09da7
remove dead variable
...
llvm-svn: 26907
2006-03-20 22:37:23 +00:00
a1bc294f0c
Fix a couple of bugs in permute/splat generate, thanks to Nate for actually
...
figuring these out! :)
llvm-svn: 26904
2006-03-20 18:26:51 +00:00
eda030da04
reenable this hack, the tblgen version isn't quite ready
...
llvm-svn: 26902
2006-03-20 17:54:43 +00:00
f96d523b8f
Fix the pattern for VADDUWM, add i32 splat
...
llvm-svn: 26901
2006-03-20 17:51:58 +00:00
89f3cff0f5
Use tblgen'd VECTOR_SHUFFLE selection code.
...
llvm-svn: 26900
2006-03-20 08:14:16 +00:00
a9a1313386
Add support for generating vspltw, instead of a vperm instruction with a
...
constant pool load. This generates significantly nicer code for splats.
When tblgen gets bugfixed, we can remove the custom selection code.
llvm-svn: 26898
2006-03-20 06:51:10 +00:00
a8fbb6dd3d
Implement PPC::isSplatShuffleMask and PPC::getVSPLTImmediate.
...
llvm-svn: 26897
2006-03-20 06:37:44 +00:00
ffc475689b
fix duplicate definition errors
...
llvm-svn: 26896
2006-03-20 06:33:01 +00:00
80b6bd2746
Add a build_vector node
...
llvm-svn: 26895
2006-03-20 06:18:01 +00:00
382f356bd9
Check in some intermediate code that adds a skeleton for matching vsplt*
...
instructions
llvm-svn: 26894
2006-03-20 06:15:45 +00:00
e6448448c2
Move a few things around.
...
llvm-svn: 26893
2006-03-20 06:04:52 +00:00
e4e1ac37ba
add vector_shuffle
...
llvm-svn: 26891
2006-03-20 05:40:45 +00:00
93d99f9928
fix typo
...
llvm-svn: 26889
2006-03-20 05:05:55 +00:00
366b2514fa
add vsplat instructions, fix sched description for vperm
...
llvm-svn: 26888
2006-03-20 04:47:33 +00:00
a8713b1ee6
Custom lower arbitrary VECTOR_SHUFFLE's to VPERM.
...
TODO: leave specific ones as VECTOR_SHUFFLE's and turn them into specialized
operations like vsplt*
llvm-svn: 26887
2006-03-20 01:53:53 +00:00
0a8b4eaee9
Claim to have v16i8 for perm masks
...
llvm-svn: 26886
2006-03-20 01:53:02 +00:00
21e68c8001
If a target supports splatting with SHUFFLE_VECTOR, lower to it from BUILD_VECTOR(x,x,x,x)
...
llvm-svn: 26885
2006-03-20 01:52:29 +00:00
6b20104410
TargetData doesn't know the alignment of vectors :(
...
llvm-svn: 26884
2006-03-20 01:51:46 +00:00
e7a058de7d
add the vperm instruction
...
llvm-svn: 26883
2006-03-20 01:00:56 +00:00
00f0589bc0
Add very basic support for VECTOR_SHUFFLE
...
llvm-svn: 26880
2006-03-19 23:56:04 +00:00
d16f6fdd49
add a note with a testcase
...
llvm-svn: 26877
2006-03-19 22:27:41 +00:00
169e6238ad
Add a note about the MUL -> FMADD vector bug.
...
llvm-svn: 26874
2006-03-19 22:08:08 +00:00
d783c76c18
Teach cee to propagate through switch statements. This implements
...
Transforms/CorrelatedExprs/switch.ll
Patch contributed by Eric Kidd!
llvm-svn: 26872
2006-03-19 19:37:24 +00:00
f7c2e3628b
Vector undef's
...
llvm-svn: 26870
2006-03-19 09:38:54 +00:00
7e9440a4fc
Custom lower SCALAR_TO_VECTOR into lve*x.
...
llvm-svn: 26868
2006-03-19 06:55:52 +00:00
79fb91cc69
Allow SCALAR_TO_VECTOR to be custom lowered.
...
llvm-svn: 26867
2006-03-19 06:47:21 +00:00
9cdc5a0ce7
Add SCALAR_TO_VECTOR support
...
llvm-svn: 26866
2006-03-19 06:31:19 +00:00
b1ee9c7e24
PPC doesn't have SCALAR_TO_VECTOR
...
llvm-svn: 26865
2006-03-19 06:17:19 +00:00
5b595af956
add support for vector undef
...
llvm-svn: 26863
2006-03-19 06:10:09 +00:00
0a03f789c2
Remind us of exit value substitution
...
llvm-svn: 26862
2006-03-19 06:09:23 +00:00
5111c81a3c
Turning on LSR by default
...
llvm-svn: 26861
2006-03-19 06:08:49 +00:00
66a9c0dea7
Remember which tests are hurt by LSR.
...
llvm-svn: 26860
2006-03-19 06:08:11 +00:00
eb5b2e705c
Don't bother storing undef elements of BUILD_VECTOR's
...
llvm-svn: 26858
2006-03-19 05:46:04 +00:00
0c9eb670bb
minor fixes
...
llvm-svn: 26857
2006-03-19 05:43:01 +00:00
ea6468758d
notes
...
llvm-svn: 26856
2006-03-19 05:33:30 +00:00
431c90c9fa
we don't use lmw/stmw. When we want them they are easy enough to add
...
llvm-svn: 26853
2006-03-19 04:33:37 +00:00
5d3ff12c8f
Implement expand of BUILD_VECTOR containing variable elements.
...
This implements CodeGen/Generic/vector.ll:test_variable_buildvector
llvm-svn: 26852
2006-03-19 04:18:56 +00:00
5336a59e4b
fold insertelement(buildvector) -> buildvector if the inserted element # is
...
a constant. This implements test_constant_insert in CodeGen/Generic/vector.ll
llvm-svn: 26851
2006-03-19 01:27:56 +00:00
29b2301460
implement basic support for INSERT_VECTOR_ELT.
...
llvm-svn: 26849
2006-03-19 01:17:20 +00:00
f7b6e7212f
rename these nodes
...
llvm-svn: 26848
2006-03-19 01:13:28 +00:00
f4e1a53647
Rename ConstantVec -> BUILD_VECTOR and VConstant -> VBUILD_VECTOR. Allow*BUILD_VECTOR to take variable inputs.
...
llvm-svn: 26847
2006-03-19 00:52:58 +00:00
c16b05e67d
implement vector.ll:test_undef
...
llvm-svn: 26845
2006-03-19 00:20:20 +00:00
93640543a9
Fix the remaining bugs in the vector expansion rework I commited yesterday.
...
This fixes CodeGen/Generic/vector.ll
llvm-svn: 26843
2006-03-19 00:07:49 +00:00
c28282bd87
- Fixed a bogus if condition.
...
- Added more debugging info.
- Allow reuse of IV of negative stride. e.g. -4 stride == 2 * iv of -2 stride.
llvm-svn: 26841
2006-03-18 08:03:12 +00:00
32206f54c6
Change the structure of lowering vector stuff. Note: This breaks some
...
things.
llvm-svn: 26840
2006-03-18 01:44:44 +00:00
9bf978dc20
Use the generic vector register classes VR64 / VR128 rather than V4F32,
...
V8I16, etc.
llvm-svn: 26838
2006-03-18 01:23:20 +00:00
f09f0ebd48
Sort StrideOrder so we can process the smallest strides first. This allows
...
for more IV reuses.
llvm-svn: 26837
2006-03-18 00:44:49 +00:00
21f87d0e4c
Fix subfic to match subc by default instead of sub so that it is correctly
...
cost-modeled as producing a flag. This fixes the test I just added for neg
llvm-svn: 26835
2006-03-17 22:41:37 +00:00
b09a56f3a4
Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
...
llvm-svn: 26833
2006-03-17 20:31:41 +00:00
4f674921d6
Move some pattern fragments to the right files.
...
llvm-svn: 26831
2006-03-17 19:55:52 +00:00
98931bc381
add a couple enum values
...
llvm-svn: 26830
2006-03-17 19:53:59 +00:00
4520698820
Allow users of iv / stride to be rewritten with expression that is a multiply
...
of a smaller stride even if they have a common loop invariant expression part.
llvm-svn: 26828
2006-03-17 19:52:23 +00:00
388fc4d9fb
Disable x86 fastcc from passing args in registers
...
llvm-svn: 26824
2006-03-17 17:27:47 +00:00
779c10818c
Fix use of LEVEL.
...
llvm-svn: 26822
2006-03-17 07:39:44 +00:00
ee4b4f55ee
Two fixes:
...
1. Allow building of Intrinsics.gen to work for srcdir != objdir
2. Add a rule for installation of Intrinsics.gen.
llvm-svn: 26819
2006-03-17 06:27:06 +00:00
43798850f9
Parameterize the number of integer arguments to pass in registers
...
llvm-svn: 26818
2006-03-17 05:10:20 +00:00
bfc2e97383
Also fold MOV8r0, MOV16r0, MOV32r0 + store to MOV8mi, MOV16mi, and MOV32mi.
...
llvm-svn: 26817
2006-03-17 02:36:22 +00:00
aca7915b70
Add some missing entries to X86RegisterInfo::foldMemoryOperand(). e.g.
...
ADD32ri8.
llvm-svn: 26816
2006-03-17 02:25:01 +00:00
27750f3287
- Nuke 16-bit SBB instructions. We'll never use them.
...
- Nuke a bogus comment.
llvm-svn: 26815
2006-03-17 02:24:04 +00:00
bb01d4f272
Remove BRTWOWAY*
...
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
llvm-svn: 26814
2006-03-17 01:40:33 +00:00
8bf1c59e7f
remove dead variable
...
llvm-svn: 26813
2006-03-16 23:52:08 +00:00
7ececaad83
Fix a problem fully scalarizing values.
...
llvm-svn: 26811
2006-03-16 23:05:19 +00:00
c11fcceec5
A new entry.
...
llvm-svn: 26810
2006-03-16 22:44:22 +00:00
fb0e36fa56
Notes on how to kill the eeevil brtwoway, and make ppc branch selector
...
more target independant, generate better code, and be less conservative.
llvm-svn: 26809
2006-03-16 22:37:48 +00:00
1e6dfa4c1f
Strangely, calls clobber call-clobbered vector regs. Whodathoughtit?
...
llvm-svn: 26808
2006-03-16 22:35:59 +00:00
325bb46315
add a note
...
llvm-svn: 26807
2006-03-16 22:25:55 +00:00
91400bd413
teach the ppc backend how to spill/reload vector regs
...
llvm-svn: 26806
2006-03-16 22:24:02 +00:00
6e90062416
add callee saved vector regs
...
llvm-svn: 26805
2006-03-16 22:07:06 +00:00
f75555feb9
Bug fix: condition inverted.
...
llvm-svn: 26804
2006-03-16 22:02:48 +00:00
3df447d354
For each loop, keep track of all the IV expressions inserted indexed by
...
stride. For a set of uses of the IV of a stride which is a multiple
of another stride, do not insert a new IV expression. Rather, reuse the
previous IV and rewrite the uses as uses of IV expression multiplied by
the factor.
e.g.
x = 0 ...; x ++
y = 0 ...; y += 4
then use of y can be rewritten as use of 4*x for x86.
llvm-svn: 26803
2006-03-16 21:53:05 +00:00
20931a798e
Added a way for TargetLowering to specify what values can be used as the
...
scale component of the target addressing mode.
llvm-svn: 26802
2006-03-16 21:47:42 +00:00
0b27047a6c
in functions that use a lot of callee saved regs, this can be more than
...
5 instructions away.
llvm-svn: 26801
2006-03-16 21:31:45 +00:00
fd9f3e8ed3
Add support for copying registers. still needed: spilling and reloading them
...
llvm-svn: 26800
2006-03-16 20:03:58 +00:00
8471b15706
Add support for CopyFromReg from vector values. Note: this doesn't support
...
illegal vector types yet!
llvm-svn: 26799
2006-03-16 19:57:50 +00:00
49409cb925
Teach CreateRegForValue how to handle vector types.
...
llvm-svn: 26798
2006-03-16 19:51:18 +00:00
ad74844bfa
set TransformToType correctly for vector types.
...
llvm-svn: 26797
2006-03-16 19:50:01 +00:00
32e73f9881
Another case we could do better on.
...
llvm-svn: 26795
2006-03-16 18:50:44 +00:00
1678a6c477
Save/restore VRSAVE once per function, not once per block.
...
llvm-svn: 26793
2006-03-16 18:25:23 +00:00
4b41e40621
add support for the bitconvert node
...
llvm-svn: 26789
2006-03-16 01:29:53 +00:00
4024c00ce7
add support for vector->vector casts
...
llvm-svn: 26788
2006-03-15 22:19:46 +00:00
cad70c3e46
Add a note, this code should be moved to the dag combiner.
...
llvm-svn: 26787
2006-03-15 22:19:18 +00:00
6d6084fd04
Teach the strip pass to strip type names in addition to value names. This
...
is fallout from the type/value split in the symtab long long ago :)
llvm-svn: 26785
2006-03-15 19:22:41 +00:00
71050ba709
Expand subprogram and added block descriptor.
...
llvm-svn: 26782
2006-03-15 19:09:58 +00:00
b3dae7cfa9
no heap is happening here
...
llvm-svn: 26781
2006-03-15 19:03:16 +00:00
c0b65305f1
remove qsort for now
...
llvm-svn: 26779
2006-03-15 18:32:18 +00:00
fb4df2055f
allow field sensitivity to be a tunable parameter
...
llvm-svn: 26777
2006-03-15 05:43:41 +00:00
2e1fde7c5c
Update scheduling info for vrsave instruction
...
llvm-svn: 26776
2006-03-15 05:25:05 +00:00
3196422df0
Handle one offset with growth case seen in povray. Namely, if we have an offset,
...
and the offset lands at a field boundary in the old type, construct a new type,
copying the fields masked by the offset from the old type, and unify with that.
llvm-svn: 26775
2006-03-15 04:04:21 +00:00
c254e5b180
improve mem intrinsics and add a few things povray uses
...
llvm-svn: 26774
2006-03-15 03:43:59 +00:00
6995470323
Bugfix, unbreaking CodeGen/PowerPC/cttz.ll
...
llvm-svn: 26764
2006-03-14 19:49:57 +00:00
6d4a221d80
Fix an et-forest memory leak. Patch by Daniel Berlin.
...
llvm-svn: 26763
2006-03-14 19:41:45 +00:00
5271a1f9b5
add a note
...
llvm-svn: 26762
2006-03-14 19:31:24 +00:00
b8e155567a
1. Use null for serialized empty strings.
...
2. Allow for user defined debug descriptors.
3. Allow for user augmented fields on debug descriptors.
llvm-svn: 26760
2006-03-14 18:37:57 +00:00
ab1ed2aa96
Fix an off by one error that caused PPC LLC failures last night.
...
llvm-svn: 26758
2006-03-14 17:56:49 +00:00
c5f866bb4a
Implement a FIXME, recusively reassociating
...
A*A*B + A*A*C --> A*(A*B+A*C) --> A*(A*(B+C))
This implements Reassociate/mul-factor3.ll
llvm-svn: 26757
2006-03-14 16:04:29 +00:00
2fc319d444
extract some code into a method, no functionality change
...
llvm-svn: 26755
2006-03-14 07:11:11 +00:00
30402be175
transformation implemented
...
llvm-svn: 26754
2006-03-14 06:57:34 +00:00
d6bde46d85
Promote shifts by a constant to multiplies so that we can reassociate
...
(x<<1)+(y<<1) -> (X+Y)<<1. This implements
Transforms/Reassociate/shift-factor.ll
llvm-svn: 26753
2006-03-14 06:55:18 +00:00
c67a060a51
Convert llvm.cs.uiuc.edu -> llvm.org
...
llvm-svn: 26748
2006-03-14 05:54:52 +00:00
cf0bdffe6d
1. Handle removal of all arguments for a morphed intrinsic.
...
2. Remove the declaration of llvm.dbg.declare.
llvm-svn: 26745
2006-03-14 02:00:35 +00:00
0f9d6534f5
PPC LSR pass should use target lowering hooks.
...
llvm-svn: 26743
2006-03-13 23:56:51 +00:00
2dd2c652b2
Added getTargetLowering() to TargetMachine. Refactored targets to support this.
...
llvm-svn: 26742
2006-03-13 23:20:37 +00:00
60f495100a
Update
...
llvm-svn: 26741
2006-03-13 23:19:10 +00:00
af598d2461
Add LSR hooks.
...
llvm-svn: 26740
2006-03-13 23:18:16 +00:00
c567c4efbb
Added target lowering hooks which LSR consults to make more intelligent
...
transformation decisions.
llvm-svn: 26738
2006-03-13 23:14:23 +00:00
2b8eb375d7
Handle builtins that directly correspond to GCC builtins.
...
llvm-svn: 26737
2006-03-13 23:09:05 +00:00
02e2c18c9c
For functions that use vector registers, save VRSAVE, mark used
...
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
llvm-svn: 26733
2006-03-13 21:52:10 +00:00
68ac09d5cb
make sure dead token factor nodes are removed by the dag combiner.
...
llvm-svn: 26731
2006-03-13 18:37:30 +00:00
611f965820
Bring makefile back into compliance with standard by using
...
$(Echo) instead of @echo
llvm-svn: 26730
2006-03-13 17:57:31 +00:00
acb6e34277
Handle the removal of the debug chain.
...
llvm-svn: 26729
2006-03-13 13:07:37 +00:00
fe4c7fb7ae
remove two implemented items
...
llvm-svn: 26728
2006-03-13 06:52:22 +00:00
d8c2a48d58
Fold X+Y -> X|Y when safe. This implements:
...
Regression/CodeGen/PowerPC/and_add.ll
a case that occurs with dynamic allocas of constant size.
llvm-svn: 26727
2006-03-13 06:51:27 +00:00
3d761b6211
I can't convince myself that this is safe, remove the recursive call.
...
llvm-svn: 26725
2006-03-13 06:42:16 +00:00
8bb6cb7d7b
add a couple of missing folds
...
llvm-svn: 26724
2006-03-13 06:26:26 +00:00
994d8e6bd4
For targets with FABS/FNEG support, lower copysign to an integer load,
...
a select and FABS/FNEG.
This speeds up a trivial (aka stupid) copysign benchmark I wrote from 6.73s
to 2.64s, woo.
llvm-svn: 26723
2006-03-13 06:08:38 +00:00
ec9d0bc3ec
Fix a couple of bugs that broke the alpha tester build
...
llvm-svn: 26722
2006-03-13 05:23:59 +00:00
4fbb612685
Handle cracked instructions in dispatch group formation.
...
llvm-svn: 26721
2006-03-13 05:20:04 +00:00
7579cfb1a0
Mark instructions that are cracked by the PPC970 decoder as such.
...
llvm-svn: 26720
2006-03-13 05:15:10 +00:00
51348c5f27
Several big changes:
...
1. Use flags on the instructions in the .td file to indicate the PPC970 unit
type instead of a table in the .cpp file. Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
accurately.
llvm-svn: 26719
2006-03-12 09:13:49 +00:00
a767dbf197
Don't advance the hazard recognizer when there are no hazards and no instructions
...
to be emitted.
Don't add one to the latency of a completed instruction if the latency of the
op is 0.
llvm-svn: 26718
2006-03-12 09:01:41 +00:00
86a9b60a25
Chain operands aren't real uses: they don't require the full latency of the
...
predecessor to finish before they can start.
llvm-svn: 26717
2006-03-12 03:52:09 +00:00
572003ca15
As a pending queue data structure to keep track of instructions whose
...
operands have all issued, but whose results are not yet available. This
allows us to compile:
int G;
int test(int A, int B, int* P) {
return (G+A)*(B+1);
}
to:
_test:
lis r2, ha16(L_G$non_lazy_ptr)
addi r4, r4, 1
lwz r2, lo16(L_G$non_lazy_ptr)(r2)
lwz r2, 0(r2)
add r2, r2, r3
mullw r3, r2, r4
blr
instead of this, which has a stall between the lis/lwz:
_test:
lis r2, ha16(L_G$non_lazy_ptr)
lwz r2, lo16(L_G$non_lazy_ptr)(r2)
addi r4, r4, 1
lwz r2, 0(r2)
add r2, r2, r3
mullw r3, r2, r4
blr
llvm-svn: 26716
2006-03-12 00:38:57 +00:00
356183d91e
rename priorityqueue -> availablequeue. When a node is scheduled, remember
...
which cycle it lands on.
llvm-svn: 26714
2006-03-11 22:44:37 +00:00
063086b0f4
Make CurrCycle a local var instead of an instance var
...
llvm-svn: 26713
2006-03-11 22:34:41 +00:00
9995a0c019
Move some methods around so that BU specific code is together, TD specific code
...
is together, and direction independent code is together.
llvm-svn: 26712
2006-03-11 22:28:35 +00:00
578d8fcb59
merge preds/chainpreds -> preds set
...
merge succs/chainsuccs -> succs set
This has no functionality change, simplifies the code, and reduces the size
of sunits.
llvm-svn: 26711
2006-03-11 22:24:20 +00:00
d03132a409
blr is a branch too
...
llvm-svn: 26710
2006-03-11 21:49:49 +00:00
4e56b686f1
add an example
...
llvm-svn: 26709
2006-03-11 20:20:40 +00:00
003f633036
add a note
...
llvm-svn: 26708
2006-03-11 20:17:08 +00:00
d5811b965d
Fix PR681 by using the standard Lengauer and Tarjan algorithm for dominator
...
set construction, rather than intersecting various std::sets. This reduces
the memory usage for the testcase in PR681 from 496 to 26MB of ram on my
darwin system, and reduces the runtime from 32.8 to 0.8 seconds on a
2.5GHz G5. This also enables future code sharing between Dom and PostDom
now that they share near-identical implementations.
llvm-svn: 26707
2006-03-11 02:20:46 +00:00
2c5e530430
Doh!
...
llvm-svn: 26705
2006-03-11 00:13:10 +00:00
38280c0020
Added a parameter to control whether Constant::getStringValue() would chop
...
off the result string at the first null terminator.
llvm-svn: 26704
2006-03-10 23:52:03 +00:00
8a18a823a0
remove some dead code
...
llvm-svn: 26703
2006-03-10 23:14:22 +00:00
d3ef6c290a
scrape out bits of llvm-db
...
llvm-svn: 26701
2006-03-10 22:48:19 +00:00
7d587f37ec
Remove UnixLocalInferiorProcess: debugging via the JIT isn't a good idea.
...
Perhaps llvm-db will turn into a read debugger someday.
llvm-svn: 26700
2006-03-10 22:39:48 +00:00
c2447e8b59
teach the JIT to encode vector registers
...
llvm-svn: 26697
2006-03-10 20:19:50 +00:00
f918e15362
Move simple-selector-specific types to the simple selector.
...
llvm-svn: 26693
2006-03-10 07:51:18 +00:00
5255d04357
Simplify the interface to the schedulers, to not pass the selected heuristicin.
...
llvm-svn: 26692
2006-03-10 07:49:12 +00:00
a5b93b8c6d
Move some simple-sched-specific instance vars to the simple scheduler.
...
llvm-svn: 26690
2006-03-10 07:42:02 +00:00
e015178de1
prune #includes
...
llvm-svn: 26689
2006-03-10 07:37:35 +00:00
4b70ff7876
move some simple scheduler methods into the simple scheduler
...
llvm-svn: 26688
2006-03-10 07:35:21 +00:00
dc2f135f5c
Make EmitNode take a SDNode instead of a NodeInfo*
...
llvm-svn: 26687
2006-03-10 07:28:36 +00:00
b9d8fa0342
Move the VRBase field from NodeInfo to being a separate, explicit, map.
...
llvm-svn: 26686
2006-03-10 07:25:12 +00:00
c48cfba44b
no need to build groups anymore
...
llvm-svn: 26684
2006-03-10 07:15:58 +00:00
6f82fe8106
Create SUnits directly from the SelectionDAG.
...
llvm-svn: 26683
2006-03-10 07:13:32 +00:00
2f8c7c3d55
Push PrepareNodeInfo/IdentifyGroups down the inheritance hierarchy
...
llvm-svn: 26682
2006-03-10 06:34:51 +00:00
349e9ddccc
Teach the latency scheduler some new tricks. In particular, to break ties,
...
keep track of a sense of "mobility", i.e. how many other nodes scheduling one
node will free up. For something like this:
float testadd(float *X, float *Y, float *Z, float *W, float *V) {
return (*X+*Y)*(*Z+*W)+*V;
}
For example, this makes us schedule *X then *Y, not *X then *Z. The former
allows us to issue the add, the later only lets us issue other loads.
This turns the above code from this:
_testadd:
lfs f0, 0(r3)
lfs f1, 0(r6)
lfs f2, 0(r4)
lfs f3, 0(r5)
fadds f0, f0, f2
fadds f1, f3, f1
lfs f2, 0(r7)
fmadds f1, f0, f1, f2
blr
into this:
_testadd:
lfs f0, 0(r6)
lfs f1, 0(r5)
fadds f0, f1, f0
lfs f1, 0(r4)
lfs f2, 0(r3)
fadds f1, f2, f1
lfs f2, 0(r7)
fmadds f1, f1, f0, f2
blr
llvm-svn: 26680
2006-03-10 05:51:05 +00:00
25e2556b71
add an aggregate method for reinserting scheduled nodes, add a callback for
...
priority impls that want to be notified when a node is scheduled
llvm-svn: 26678
2006-03-10 04:32:49 +00:00
6ce97687f7
Fix VC++ build breakage.
...
llvm-svn: 26676
2006-03-10 03:57:45 +00:00
60f6833376
use autogenerated side-effect information
...
llvm-svn: 26673
2006-03-09 22:38:10 +00:00
bb40a9fa58
Use autogenerated mod/ref info for intrinsics.
...
llvm-svn: 26670
2006-03-09 22:31:29 +00:00
591693f3bf
Use the autogenerated intrinsic verifier
...
llvm-svn: 26667
2006-03-09 22:06:04 +00:00
306c13a8fb
Add option -enable-x86-lsr to enable x86 loop strength reduction pass.
...
llvm-svn: 26665
2006-03-09 21:51:28 +00:00
ff4d4ee163
Use the function name matcher autogenerated from the .td file.
...
llvm-svn: 26664
2006-03-09 20:35:01 +00:00
285c95d7eb
This rule also depends on tblgen
...
llvm-svn: 26662
2006-03-09 20:29:41 +00:00
f136299635
add a note
...
llvm-svn: 26661
2006-03-09 20:13:21 +00:00
213209a248
remove dbg_declare, it's not used yet.
...
llvm-svn: 26659
2006-03-09 20:02:42 +00:00
ea0aa2868f
silly case insensitive file systems...
...
llvm-svn: 26658
2006-03-09 19:55:06 +00:00
83e6e19936
Build intrinsics.gen from intrinsics.td
...
llvm-svn: 26657
2006-03-09 19:53:27 +00:00
ab8d2ba046
autoupgrade memcpy/memmove/memset with signed counts.
...
CVS: ----------------------------------------------------------------------
llvm-svn: 26654
2006-03-09 18:42:10 +00:00
43e569c95f
these are copies too
...
llvm-svn: 26653
2006-03-09 18:18:51 +00:00
7e7dccd3ab
remove some now-dead code
...
llvm-svn: 26652
2006-03-09 18:07:49 +00:00
70236fc12f
fcopysign for mixed mode
...
llvm-svn: 26651
2006-03-09 17:56:33 +00:00
f0fc6bbaf3
back out my previous hack
...
llvm-svn: 26650
2006-03-09 17:48:46 +00:00
ebfd94fa1d
relax fcopysign
...
llvm-svn: 26649
2006-03-09 17:47:22 +00:00
4a87e7d9a3
alpha and llvm have different oppinions on which arg is the sign bit
...
llvm-svn: 26647
2006-03-09 17:41:50 +00:00
c6c9e65301
remove temporary option
...
llvm-svn: 26646
2006-03-09 17:31:22 +00:00
16b96d2cb4
Alpha Scheduling classes
...
llvm-svn: 26643
2006-03-09 17:16:45 +00:00
c44be2c4ef
temporary hack to get the build working again, apparently a header
...
commit was forgotten
llvm-svn: 26642
2006-03-09 17:11:08 +00:00
ed7a293b44
fcopysign and get rid of dsnode cruft. custom PA runtimes make this better in some senses
...
llvm-svn: 26641
2006-03-09 14:58:25 +00:00
b8a06a7c6c
fcopysign support
...
llvm-svn: 26640
2006-03-09 14:57:36 +00:00
4b0e1d9e6c
Move bit field endianness to backend.
...
llvm-svn: 26639
2006-03-09 13:28:47 +00:00
d17d77aa1d
yes yes, enabled debug output is bad
...
llvm-svn: 26637
2006-03-09 07:39:25 +00:00
6398c13128
switch the t-d scheduler to use a really dumb and trivial critical path
...
latency priority function.
llvm-svn: 26636
2006-03-09 07:38:27 +00:00
d4130375c0
Pull latency information for target instructions out of the latency tables. :)
...
Only enable this with -use-sched-latencies, I'll enable it by default with a
clean nightly tester run tonight.
PPC is the only target that provides latency info currently.
llvm-svn: 26634
2006-03-09 07:15:18 +00:00
da6aafeef4
don't copy all itinerary data
...
llvm-svn: 26633
2006-03-09 07:13:00 +00:00
399bee27f0
PriorityQueue is an instance var, use it.
...
llvm-svn: 26632
2006-03-09 06:48:37 +00:00
9e95accf4e
add some comments
...
llvm-svn: 26631
2006-03-09 06:37:29 +00:00
9df647539d
Refactor the priority mechanism one step further: now that it is a separate
...
class, sever its implementation from the interface. Now we can provide new
implementations of the same interface (priority computation) without touching
the scheduler itself.
llvm-svn: 26630
2006-03-09 06:35:14 +00:00
e363fdf318
Add support for 'special' llvm globals like debug info and static ctors/dtors.
...
llvm-svn: 26628
2006-03-09 06:14:35 +00:00
6b7847a5bc
fix a pasto
...
llvm-svn: 26627
2006-03-09 06:09:41 +00:00
920e661e50
a couple of miscellaneous things.
...
llvm-svn: 26625
2006-03-09 01:39:46 +00:00
8f0a95f664
Add #line support for CBE.
...
llvm-svn: 26621
2006-03-08 19:31:15 +00:00
faae50b66b
Add a helper method for running static ctors/dtors in the module.
...
llvm-svn: 26619
2006-03-08 18:42:46 +00:00
48a8e09ad0
add a new helper method.
...
llvm-svn: 26618
2006-03-08 18:39:13 +00:00
2698f0de7a
Get rid of the multiple copies of getStringValue. Now a Constant:: method.
...
llvm-svn: 26616
2006-03-08 18:11:07 +00:00
5005b01c20
doo de doo
...
llvm-svn: 26614
2006-03-08 06:18:46 +00:00
fd22d42945
Split the priority function computation and priority queue management out
...
of the ScheduleDAGList class into a new SchedulingPriorityQueue class.
llvm-svn: 26613
2006-03-08 05:18:27 +00:00
42e2026cb0
switch from an explicitly managed list of SUnits to a simple vector of sunits
...
llvm-svn: 26612
2006-03-08 04:54:34 +00:00
12c6d89204
Shrinkify some fields, fit to 80 columns
...
llvm-svn: 26611
2006-03-08 04:41:06 +00:00
3fe975b846
revert the previous patch, didn't mean to check it in yet
...
llvm-svn: 26610
2006-03-08 04:39:05 +00:00
af5e26c980
remove "Slot", it is dead
...
llvm-svn: 26609
2006-03-08 04:37:58 +00:00
543832d39d
Change the interface for getting a target HazardRecognizer to be more clean.
...
llvm-svn: 26608
2006-03-08 04:25:59 +00:00
2370265550
libstdc++-v3 was failing to build. Needed to handle composite types with empty
...
members (running into a zero initializer.)
llvm-svn: 26607
2006-03-08 02:07:02 +00:00
fc34f8bb48
Fix a miscompilation of 188.ammp with the new CFE. 188.ammp is accessing
...
arrays out of range in a horrible way, but we shouldn't break it anyway.
Details in the comments.
llvm-svn: 26606
2006-03-08 01:05:29 +00:00
a8dd636192
add a note
...
llvm-svn: 26605
2006-03-08 00:25:47 +00:00
70b25efa57
X86ISD::REP_STOS and X86ISD::REP_MOVS now produces a flag.
...
llvm-svn: 26604
2006-03-07 23:34:23 +00:00
adc7093fc1
Use rep/stosl; and Count 0x3; rep/stosb for memset with 4 byte aligned dest.
...
and variable value.
Similarly for memcpy.
llvm-svn: 26603
2006-03-07 23:29:39 +00:00
207291fd1a
Two things:
...
1. Don't emit debug info, or other llvm.metadata to the .cbe.c file.
2. Mark static ctors/dtors as such, so that bugpoint works on C++ code
compiled with the new CFE.
llvm-svn: 26602
2006-03-07 22:58:23 +00:00
313570fb17
Use "llvm.metadata" section for debug globals. Filter out these globals in the
...
asm printer.
llvm-svn: 26599
2006-03-07 22:00:35 +00:00
69effa2325
Switch to using a numeric id for anchors.
...
llvm-svn: 26598
2006-03-07 20:53:47 +00:00
7b87fd53f9
Fix ConstantMerge/2006-03-07-DontMergeDiffSections.ll, a problem Jim
...
hypotheticalized about, where we would incorrectly merge two globals in
different sections.
llvm-svn: 26597
2006-03-07 17:56:59 +00:00
907e13c742
add another missing store.
...
llvm-svn: 26595
2006-03-07 16:26:48 +00:00
8c73d80b08
add a couple more load/store instrs, add a newline to the end of file.
...
llvm-svn: 26594
2006-03-07 16:19:46 +00:00
3bad199894
Bitfield support.
...
llvm-svn: 26593
2006-03-07 15:51:33 +00:00
3e3219cc0a
This kinda sorta implements "things that have to lead a dispatch group".
...
llvm-svn: 26591
2006-03-07 08:30:27 +00:00
675567f77c
add some new instructions to the classifier. With this, we correctly insert
...
a nop into Freebench/neural, which speeds it up from 136->129s (~5.4%).
llvm-svn: 26590
2006-03-07 07:14:55 +00:00
05ad128dca
add some comments that describe what we model
...
llvm-svn: 26588
2006-03-07 06:44:19 +00:00
2cab13573c
Implement a very very simple hazard recognizer for LSU rejects and ctr set/read
...
flushes
llvm-svn: 26587
2006-03-07 06:32:48 +00:00
0c801bd1cf
Fix some formatting, when looking for hazards, prefer target nodes over
...
things like copyfromreg.
llvm-svn: 26586
2006-03-07 05:40:43 +00:00
883cefc656
add a note
...
llvm-svn: 26585
2006-03-07 04:42:59 +00:00
bccb0e07f0
add a note
...
llvm-svn: 26583
2006-03-07 02:46:26 +00:00
a4a4ceb478
- Emit subsections_via_symbols for Darwin.
...
- Conditionalize Dwarf debugging output (Darwin only for now).
llvm-svn: 26582
2006-03-07 02:23:26 +00:00
30d7b70b73
Enable Dwarf debugging info.
...
llvm-svn: 26581
2006-03-07 02:02:57 +00:00
53ef5a032c
Teach the alignment handling code to look through constant expr casts and GEPs
...
llvm-svn: 26580
2006-03-07 01:28:57 +00:00
82f2ef20b6
Teach instcombine to increase the alignment of memset/memcpy/memmove when
...
the pointer is known to come from either a global variable, alloca or
malloc. This allows us to compile this:
P = malloc(28);
memset(P, 0, 28);
into explicit stores on PPC instead of a memset call.
llvm-svn: 26577
2006-03-06 20:18:44 +00:00
01aa752a36
update file comment
...
llvm-svn: 26573
2006-03-06 17:58:04 +00:00
a00c61932d
Remove some code that doesn't make sense
...
llvm-svn: 26572
2006-03-06 07:31:44 +00:00
c5c0658aa6
Remove SUnit::Priority1: it is re-calculated on demand as number of live
...
range to be generated.
llvm-svn: 26570
2006-03-06 06:08:54 +00:00
47639dbb93
Hoist the HazardRecognizer out of the ScheduleDAGList.cpp file to where
...
targets can implement them. Make the top-down scheduler non-g5-specific.
Remove the old testing hazard recognizer.
llvm-svn: 26569
2006-03-06 00:22:00 +00:00
00b52ea8f9
Comment fixes
...
llvm-svn: 26567
2006-03-05 23:59:20 +00:00
80268aaeed
Don't depend on the C99 copysign function, implement it ourselves.
...
llvm-svn: 26566
2006-03-05 23:57:58 +00:00
2d945ba4c7
When a hazard recognizer needs noops to be inserted, do so. This represents
...
noops as null pointers in the instruction sequence.
llvm-svn: 26564
2006-03-05 23:51:47 +00:00
ea79d9fd73
implement TII::insertNoop
...
llvm-svn: 26562
2006-03-05 23:49:55 +00:00
fa5e1c9c26
Implement G5HazardRecognizer as a trivial thing that wants 5 cycles between
...
copyfromreg nodes. Clearly useful!
llvm-svn: 26559
2006-03-05 23:13:56 +00:00
e50c092b7c
Add basic hazard recognizer support. noop insertion isn't complete yet though.
...
llvm-svn: 26558
2006-03-05 22:45:01 +00:00
55e2aac24b
Fix VC++ compilation error.
...
llvm-svn: 26554
2006-03-05 21:43:37 +00:00
98ecb8ec61
Split the list scheduler into top-down and bottom-up pieces. The priority
...
function of the top-down scheduler are completely bogus currently, and
having (future) PPC specific in this file is also wrong, but this is a
small incremental step.
llvm-svn: 26552
2006-03-05 21:10:33 +00:00
7a36d97518
Move the available queue to being inside the ListSchedule method, since it
...
bounds its lifetime.
llvm-svn: 26550
2006-03-05 20:21:55 +00:00
5032c32d30
add a note
...
llvm-svn: 26549
2006-03-05 20:00:08 +00:00
bdaf4f38b5
Reinstate this now that the offending opposite xform has been removed.
...
llvm-svn: 26548
2006-03-05 19:53:55 +00:00
c726a5c31f
Do not fold (add (shl x, c1), (shl c2, c1)) -> (shl (add x, c2), c1),
...
we want to canonicalize the other way.
llvm-svn: 26547
2006-03-05 19:52:57 +00:00
c610e62e46
print arbitrary constant pool entries
...
llvm-svn: 26545
2006-03-05 09:38:03 +00:00
d428e22c07
Back out fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2) for now.
...
It's causing an infinite loop compiling ldecod on x86 / Darwin.
llvm-svn: 26544
2006-03-05 07:30:16 +00:00
3bc4050217
Add some simple copysign folds
...
llvm-svn: 26543
2006-03-05 05:30:57 +00:00
5c1ba2ac08
Codegen copysign[f] into a FCOPYSIGN node
...
llvm-svn: 26542
2006-03-05 05:09:38 +00:00
9c7f50376a
Copysign needs to be expanded everywhere. Note that Alpha and IA64 should
...
implement copysign as a native op if they have it.
llvm-svn: 26541
2006-03-05 05:08:37 +00:00
c2dd7aae71
add a note for something evan noticed
...
llvm-svn: 26539
2006-03-05 01:15:18 +00:00
6bc98653c2
Make vector narrowing more effective, implementing
...
Transforms/InstCombine/vec_narrow.ll. This add support for narrowing
extract_element(insertelement) also.
llvm-svn: 26538
2006-03-05 00:22:33 +00:00
8d8b4cf63d
Implemented.
...
llvm-svn: 26536
2006-03-04 23:33:44 +00:00
f29f5204cc
fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
...
fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
This allows us to compile CodeGen/PowerPC/addi-reassoc.ll into:
_test1:
slwi r2, r4, 4
add r2, r2, r3
lwz r3, 36(r2)
blr
_test2:
mulli r2, r4, 5
add r2, r2, r3
lbz r2, 11(r2)
extsb r3, r2
blr
instead of:
_test1:
addi r2, r4, 2
slwi r2, r2, 4
add r2, r3, r2
lwz r3, 4(r2)
blr
_test2:
addi r2, r4, 2
mulli r2, r2, 5
add r2, r3, r2
lbz r2, 1(r2)
extsb r3, r2
blr
llvm-svn: 26535
2006-03-04 23:33:26 +00:00
3e19c23765
Fix a crash compiling Obsequi
...
llvm-svn: 26529
2006-03-04 21:48:01 +00:00
4c065091d8
Add factoring of multiplications, e.g. turning A*A+A*B into A*(A+B).
...
Testcase here: Transforms/Reassociate/mulfactor.ll
llvm-svn: 26524
2006-03-04 09:31:13 +00:00
c9a318d8fa
Add a note
...
llvm-svn: 26523
2006-03-04 08:44:51 +00:00
adf5ec6f96
Regenerate
...
llvm-svn: 26522
2006-03-04 07:53:41 +00:00
a33bcff313
Don't use invalidated iterators!
...
llvm-svn: 26521
2006-03-04 07:53:16 +00:00
c66fd44541
Add an entry
...
llvm-svn: 26520
2006-03-04 07:49:50 +00:00
32c01df299
Canonicalize (X+C1)*C2 -> X*C2+C1*C2
...
This implements Transforms/InstCombine/add.ll:test31
llvm-svn: 26519
2006-03-04 06:04:02 +00:00
6dc73297c3
MEMSET / MEMCPY lowering bugs: we can't issue a single WORD / DWORD version of
...
rep/stos and rep/mov if the count is not a constant. We could do
rep/stosl; and $count, 3; rep/stosb
For now, I will lower them to memset / memcpy calls. We will revisit this after
a little bit experiment.
Also need to take care of the trailing bytes even if the count is a constant.
Since the max. number of trailing bytes are 3, we will simply issue loads /
stores.
llvm-svn: 26517
2006-03-04 02:48:56 +00:00
071faf25e0
Be more conservative with our symbolic alias analysis. In particular,
...
don't assume that A[1][0] and A[0][i] can't alias. "i" might be out of
range, or even negative. This fixes a miscompilation of 188.ammp (which
does bad pointer tricks) with the new CFE.
Testcase here: Analysis/BasicAA/2006-03-03-BadArraySubscript.ll
llvm-svn: 26515
2006-03-04 02:06:34 +00:00
e43e5c0697
add a note
...
llvm-svn: 26513
2006-03-04 01:19:34 +00:00
084a102b17
Typo
...
llvm-svn: 26512
2006-03-04 01:12:00 +00:00
c44f05d624
Added support for dwarf block data entries.
...
llvm-svn: 26509
2006-03-03 21:00:14 +00:00
c2de4f3dc1
Unbreak autouprade of llvm.sqrt, simplify some code.
...
llvm-svn: 26506
2006-03-03 16:31:22 +00:00
88f0fe15a2
Adding basic structure support.
...
llvm-svn: 26505
2006-03-03 15:06:57 +00:00
3bf916ddd9
Add more vector NodeTypes: VSDIV, VUDIV, VAND, VOR, and VXOR.
...
llvm-svn: 26504
2006-03-03 07:01:07 +00:00
a7fb285c60
Number of NodeTypes now exceeds 128.
...
llvm-svn: 26503
2006-03-03 06:58:59 +00:00
23e75f5b49
SDOperand::isOperand should not be a forwarding. It must check *this against N's operands.
...
llvm-svn: 26502
2006-03-03 06:42:32 +00:00
6b08ae8497
Added isOperand(N): true if this is an operand of N
...
llvm-svn: 26501
2006-03-03 06:24:54 +00:00
5e9a695026
A bit more tweaking
...
llvm-svn: 26500
2006-03-03 06:23:43 +00:00
55c1173a6c
Fix VC++ compilation errors.
...
llvm-svn: 26498
2006-03-03 03:25:07 +00:00
993e9cf26e
Move #include "llvm/CodeGen/AsmPrinter.h" to top since it's the interface.
...
llvm-svn: 26493
2006-03-03 02:04:29 +00:00
b203355298
Split the valuetypes out of Target.td into ValueTypes.td
...
llvm-svn: 26490
2006-03-03 01:55:26 +00:00
681ef2f083
Change this to work with renamed intrinsics.
...
llvm-svn: 26484
2006-03-03 01:34:17 +00:00
ea7986aeca
Make this work with renamed intrinsics.
...
llvm-svn: 26482
2006-03-03 01:30:23 +00:00
bce2626d8a
updates for recent changes
...
llvm-svn: 26481
2006-03-03 01:21:36 +00:00
ad3c974a77
remove the read/write port/io intrinsics.
...
llvm-svn: 26479
2006-03-03 00:19:58 +00:00
093c159efb
Split memcpy/memset/memmove intrinsics into i32/i64 versions, resolving
...
PR709, and paving the way for future progress.
llvm-svn: 26476
2006-03-03 00:00:25 +00:00
259d680c15
Simplify the autoupgrade interface
...
llvm-svn: 26475
2006-03-02 23:59:12 +00:00
d124535de1
Split memcpy/memset/memmove intrinsics into i32/i64 versions, resolving
...
PR709, and paving the way for future progress.
Significantly refactor autoupgrading code, to handle the more complex case
(where we upgrade one argument in a function), and fix some bugs in it.
Testcase here: llvm/test/Regression/Bytecode/memcpy.ll
llvm-svn: 26474
2006-03-02 23:58:40 +00:00
9067500e2e
add a note
...
llvm-svn: 26472
2006-03-02 22:34:38 +00:00
4e3904f637
- Fixed some priority calculation bugs that were causing bug 478. Among them:
...
a predecessor appearing more than once in the operand list was counted as
multiple predecessor; priority1 should be updated during scheduling;
CycleBound was updated after the node is inserted into priority queue; one
of the tie breaking condition was flipped.
- Take into consideration of two address opcodes. If a predecessor is a def&use
operand, it should have a higher priority.
- Scheduler should also favor floaters, i.e. nodes that do not have real
predecessors such as MOV32ri.
- The scheduling fixes / tweaks fixed bug 478:
.text
.align 4
.globl _f
_f:
movl 4(%esp), %eax
movl 8(%esp), %ecx
movl %eax, %edx
imull %ecx, %edx
imull %eax, %eax
imull %ecx, %ecx
addl %eax, %ecx
leal (%ecx,%edx,2), %eax
ret
It is also a slight performance win (1% - 3%) for most tests.
llvm-svn: 26470
2006-03-02 21:38:29 +00:00
85dda9a2bd
Generalize the REM folding code to handle another case Nick Lewycky
...
pointed out: realize the AND can provide factors and look through Casts.
llvm-svn: 26469
2006-03-02 06:50:58 +00:00
862001ad75
Support for enumerations.
...
llvm-svn: 26466
2006-03-01 23:52:37 +00:00
38d5e768b2
Don't print llvm constant in assmebly file. Assembler won't like comments that
...
span multiple lines.
llvm-svn: 26463
2006-03-01 22:18:09 +00:00
5b19a80321
Back out my last check-in. Wrong place to fix it.
...
llvm-svn: 26462
2006-03-01 22:17:00 +00:00
302bdb586f
AsmWriter should not print LLVM constant in comment. Assembler won't like
...
multi-line comments.
llvm-svn: 26461
2006-03-01 22:00:59 +00:00
0db2f2c689
Fix CodeGen/Generic/2006-03-01-dagcombineinfloop.ll, an infinite loop
...
in the dag combiner on 176.gcc on x86.
llvm-svn: 26459
2006-03-01 21:47:21 +00:00
4e71db13d6
Switch back to using actual dwarf tags. Simplifies code without loss to other
...
debug forms.
llvm-svn: 26455
2006-03-01 20:39:36 +00:00
232024edb8
Fix a typo evan noticed
...
llvm-svn: 26454
2006-03-01 19:55:35 +00:00
f770cf5b90
Use context and not compile unit.
...
llvm-svn: 26453
2006-03-01 18:20:30 +00:00
1246d5c054
I guess I can handle large type sizes.
...
llvm-svn: 26452
2006-03-01 18:13:05 +00:00
b9ac4cba66
Basic array support.
...
llvm-svn: 26451
2006-03-01 17:53:02 +00:00
60a60f4b1e
Implement CodeGen/PowerPC/or-addressing-mode.ll, which is also PR668.
...
llvm-svn: 26450
2006-03-01 07:14:48 +00:00
3cb349a068
add a note
...
llvm-svn: 26448
2006-03-01 06:36:20 +00:00
27f5345b1f
Compile this:
...
void foo(float a, int *b) { *b = a; }
to this:
_foo:
fctiwz f0, f1
stfiwx f0, 0, r4
blr
instead of this:
_foo:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
stw r2, 0(r4)
blr
This implements CodeGen/PowerPC/stfiwx.ll, and also incidentally does the
right thing for GCC bugzilla 26505.
llvm-svn: 26447
2006-03-01 05:50:56 +00:00
f418435819
Use a target-specific dag-combine to implement CodeGen/PowerPC/fp-int-fp.ll.
...
llvm-svn: 26445
2006-03-01 04:57:39 +00:00
bc1c85beea
Add support for target-specific dag combines
...
llvm-svn: 26443
2006-03-01 04:53:38 +00:00
4a2eeea671
Add interfaces for targets to provide target-specific dag combiner optimizations.
...
llvm-svn: 26442
2006-03-01 04:52:55 +00:00
fbcd62d3bb
Add a new AddToWorkList method, start using it
...
llvm-svn: 26441
2006-03-01 04:03:14 +00:00
324871ef1a
Pull shifts by a constant through multiplies (a form of reassociation),
...
implementing Regression/CodeGen/X86/mul-shift-reassoc.ll
llvm-svn: 26440
2006-03-01 03:44:24 +00:00
1926427351
Vector op lowering.
...
llvm-svn: 26438
2006-03-01 01:11:20 +00:00
b97aab4371
Vector ops lowering.
...
llvm-svn: 26436
2006-03-01 01:09:54 +00:00
91c574b642
New type v2f32.
...
llvm-svn: 26435
2006-03-01 01:06:22 +00:00
be85e89ec4
- Added VConstant as an abstract version of ConstantVec.
...
- All abstrct vector nodes must have # of elements and element type as their
first two operands.
llvm-svn: 26432
2006-03-01 00:51:13 +00:00
0e69f45b07
Another entry.
...
llvm-svn: 26430
2006-02-28 23:38:49 +00:00
990c3602bd
Don't match x << 1 to LEAL. It's better to emit x + x.
...
llvm-svn: 26429
2006-02-28 21:13:57 +00:00
716edb9754
Add const, volatile, restrict support.
...
Add array of debug descriptor support.
llvm-svn: 26428
2006-02-28 20:15:07 +00:00
c5b6c9a12a
Fix a regression in a patch from a couple of days ago. This fixes
...
Transforms/InstCombine/2006-02-28-Crash.ll
llvm-svn: 26427
2006-02-28 19:47:20 +00:00
b9f35f06bc
Add a subtarget feature for the stfiwx instruction. I know the G5 has it,
...
but I don't know what other PPC impls do. If someone could update the proc
table, I would appreciate it :)
llvm-svn: 26421
2006-02-28 07:08:22 +00:00
f0032b350c
Compile:
...
unsigned foo4(unsigned short *P) { return *P & 255; }
unsigned foo5(short *P) { return *P & 255; }
to:
_foo4:
lbz r3,1(r3)
blr
_foo5:
lbz r3,1(r3)
blr
not:
_foo4:
lhz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
_foo5:
lhz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
llvm-svn: 26419
2006-02-28 06:49:37 +00:00
872810da6c
remove implemented item
...
llvm-svn: 26418
2006-02-28 06:36:04 +00:00
bdbc4476d9
Fold "and (LOAD P), 255" -> zextload. This allows us to compile:
...
unsigned foo3(unsigned *P) { return *P & 255; }
as:
_foo3:
lbz r3, 3(r3)
blr
instead of:
_foo3:
lwz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
and:
unsigned short foo2(float a) { return a; }
as:
_foo2:
fctiwz f0, f1
stfd f0, -8(r1)
lhz r3, -2(r1)
blr
instead of:
_foo2:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
rlwinm r3, r2, 0, 16, 31
blr
llvm-svn: 26417
2006-02-28 06:35:35 +00:00
0f8a727c49
fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
...
llvm-svn: 26416
2006-02-28 06:23:04 +00:00
b70f141893
Implement rem.ll:test[7-9] and PR712
...
llvm-svn: 26415
2006-02-28 05:49:21 +00:00
2a7c7b8bab
Simplify some code now that the RHS of a rem can't be 0
...
llvm-svn: 26413
2006-02-28 05:40:55 +00:00
0de4a8d7b7
Rearrange some code, fold "rem X, 0", implementing rem.ll:test6
...
llvm-svn: 26411
2006-02-28 05:30:45 +00:00
9fed5b6122
Add support for output memory constraints.
...
llvm-svn: 26410
2006-02-27 23:45:39 +00:00
6d5c2a0156
Qualify dwarf namespace inside llvm namespace.
...
llvm-svn: 26409
2006-02-27 22:37:23 +00:00
f918ed2e33
readme updates
...
llvm-svn: 26405
2006-02-27 22:08:36 +00:00
bc7a3832e8
Partial enabling of functions.
...
llvm-svn: 26404
2006-02-27 20:37:42 +00:00
ec185f7843
Don't print constant initializers, they may span lines now.
...
llvm-svn: 26403
2006-02-27 20:09:23 +00:00
72b66d6d8a
Supporting multiple compile units.
...
llvm-svn: 26402
2006-02-27 17:27:12 +00:00
22e47b9f4e
Re-orging file.
...
llvm-svn: 26401
2006-02-27 12:43:29 +00:00
6be3d8e0df
Pretty print large struct constants.
...
llvm-svn: 26400
2006-02-27 10:33:53 +00:00
8f2c1021b4
Removed dependency on how operands are printed (want multi-line.)
...
llvm-svn: 26399
2006-02-27 10:29:04 +00:00
c7bfed0f7b
Merge two almost-identical pieces of code.
...
Make this code more powerful by using ComputeMaskedBits instead of looking
for an AND operand. This lets us fold this:
int %test23(int %a) {
%tmp.1 = and int %a, 1
%tmp.2 = seteq int %tmp.1, 0
%tmp.3 = cast bool %tmp.2 to int ;; xor tmp1, 1
ret int %tmp.3
}
into: xor (and a, 1), 1
llvm-svn: 26396
2006-02-27 02:38:23 +00:00
f5c8a0b83f
Fold (A^B) == A -> B == 0
...
and (A-B) == A -> B == 0
llvm-svn: 26394
2006-02-27 01:44:11 +00:00
ab8164042a
Implement bit propagation through sub nodes, this (re)implements
...
PowerPC/div-2.ll
llvm-svn: 26392
2006-02-27 01:00:42 +00:00
47ee42829d
remove some completed notes
...
llvm-svn: 26390
2006-02-27 00:39:31 +00:00
a60751dd43
Check RHS simplification before LHS simplification to avoid infinitely looping
...
on PowerPC/small-arguments.ll
llvm-svn: 26389
2006-02-27 00:36:27 +00:00
27220f8958
Just like we use the RHS of an AND to simplify the LHS, use the LHS to
...
simplify the RHS. This allows for the elimination of many thousands of
ands from multisource, and compiles CodeGen/PowerPC/and-elim.ll:test2
into this:
_test2:
srwi r2, r3, 1
xori r3, r2, 40961
blr
instead of this:
_test2:
rlwinm r2, r3, 31, 17, 31
xori r2, r2, 40961
rlwinm r3, r2, 0, 16, 31
blr
llvm-svn: 26388
2006-02-27 00:22:28 +00:00
118ddba929
Add a bunch of missed cases. Perhaps the most significant of which is that
...
assertzext produces zero bits.
llvm-svn: 26386
2006-02-26 23:36:02 +00:00
f78df7c14d
Fold (X|C1)^C2 -> X^(C1|C2) when possible. This implements
...
InstCombine/or.ll:test23.
llvm-svn: 26385
2006-02-26 19:57:54 +00:00
702c1d11b5
Reverting. Didn't realize some developers were embedding constants in their
...
target assembler code gen.
llvm-svn: 26383
2006-02-26 10:16:05 +00:00
877ab55e06
ConstantPoolIndex is now the displacement portion of the address (rather
...
than base).
llvm-svn: 26382
2006-02-26 09:12:34 +00:00
9f9662b86e
Print ConstantPoolSDNode offset field.
...
llvm-svn: 26381
2006-02-26 08:36:57 +00:00
75b8783aaf
Fixed ConstantPoolIndex operand asm print bug. This fixed 2005-07-17-INT-To-FP
...
and 2005-05-12-Int64ToFP.
llvm-svn: 26380
2006-02-26 08:28:12 +00:00
3bb7874dd3
Format large struct constants for readability.
...
llvm-svn: 26379
2006-02-25 12:27:03 +00:00
77d86ff8fc
* Cleaned up addressing mode matching code.
...
* Cleaned up and tweaked LEA cost analysis code. Removed some hacks.
* Handle ADD $X, c to MOV32ri $X+c. These patterns cannot be autogen'd and
they need to be matched before LEA.
llvm-svn: 26376
2006-02-25 10:09:08 +00:00
1c557bfeb5
Updates.
...
llvm-svn: 26375
2006-02-25 10:04:07 +00:00
1fac3b3360
* Allow mul, shl nodes to be codegen'd as LEA (if appropriate).
...
* Add patterns to handle GlobalAddress, ConstantPool, etc.
MOV32ri to materialize these nodes in registers.
ADD32ri to handle %reg + GA, etc.
MOV32mi to handle store GA, etc. to memory.
llvm-svn: 26374
2006-02-25 10:02:21 +00:00
e4a8b74e4f
ConstantPoolIndex is now the displacement field of addressing mode.
...
llvm-svn: 26373
2006-02-25 09:56:50 +00:00
994700101e
Added a common about the need for X86ISD::Wrapper.
...
llvm-svn: 26372
2006-02-25 09:55:19 +00:00
ed169db8a5
Added an offset field to ConstantPoolSDNode.
...
llvm-svn: 26371
2006-02-25 09:54:52 +00:00
7d01f95a57
Fix a bug that Evan exposed with some changes he's making, and that was
...
exposed with a fastcc problem (breaking pcompress2 on x86 with -enable-x86-fastcc).
When reloading a reused reg, make sure to invalidate the reloaded reg, and
check to see if there are any other pending uses of the same register.
llvm-svn: 26369
2006-02-25 02:17:31 +00:00
28a0b8bec7
Remove debugging printout :)
...
Add a minor compile time win, no codegen change.
llvm-svn: 26368
2006-02-25 02:03:40 +00:00
525522e429
Refactor some code from being inline to being out in a new class with methods.
...
This gets rid of two gotos, which is always nice, and also adds some comments.
No functionality change, this is just a refactor.
llvm-svn: 26367
2006-02-25 01:51:33 +00:00
42d5ac557c
Fix an obvious bug exposed when we are doing
...
ADD X, 4
==>
MOV32ri $X+4, ...
llvm-svn: 26366
2006-02-25 01:37:02 +00:00
7674d90fa1
Add memory printing support for PPC. Input memory operands now work with
...
inline asms! :)
llvm-svn: 26365
2006-02-24 20:27:40 +00:00
1d08c6534c
Use the PrintAsmMemoryOperand to print addressing modes.
...
llvm-svn: 26364
2006-02-24 20:21:58 +00:00
5af3fdec12
Pass all the flags to the asm printer, not just the # operands.
...
llvm-svn: 26362
2006-02-24 19:50:58 +00:00
2f8a794b13
rename NumOps -> NumVals to avoid shadowing a NumOps var in an outer scope.
...
Add support for addressing modes.
llvm-svn: 26361
2006-02-24 19:18:20 +00:00
86c51000db
Refactor operand adding out to a new AddOperand method
...
llvm-svn: 26358
2006-02-24 18:54:03 +00:00
b580d26e7d
Fix a problem that Nate noticed that boils down to an over conservative check
...
in the code that does "select C, (X+Y), (X-Y) --> (X+(select C, Y, (-Y)))".
We now compile this loop:
LBB1_1: ; no_exit
add r6, r2, r3
subf r3, r2, r3
cmpwi cr0, r2, 0
addi r7, r5, 4
lwz r2, 0(r5)
addi r4, r4, 1
blt cr0, LBB1_4 ; no_exit
LBB1_3: ; no_exit
mr r3, r6
LBB1_4: ; no_exit
cmpwi cr0, r4, 16
mr r5, r7
bne cr0, LBB1_1 ; no_exit
into this instead:
LBB1_1: ; no_exit
srawi r6, r2, 31
add r2, r2, r6
xor r6, r2, r6
addi r7, r5, 4
lwz r2, 0(r5)
addi r4, r4, 1
add r3, r3, r6
cmpwi cr0, r4, 16
mr r5, r7
bne cr0, LBB1_1 ; no_exit
llvm-svn: 26356
2006-02-24 18:05:58 +00:00
723d3e0746
Add pointer and reference types. Added short-term code to ignore NULL types
...
(to allow llvm-gcc4 to build.)
llvm-svn: 26355
2006-02-24 16:46:40 +00:00
83c22e0d75
Get VC++ building again.
...
llvm-svn: 26351
2006-02-24 02:52:40 +00:00
dcf785bf46
Implement (most of) selection of inline asm memory operands.
...
llvm-svn: 26350
2006-02-24 02:13:54 +00:00
a1ec1ddd59
Implement selection of inline asm memory operands
...
llvm-svn: 26348
2006-02-24 02:13:12 +00:00
7ef7a64ebb
Lower C_Memory operands.
...
llvm-svn: 26346
2006-02-24 01:11:24 +00:00
2a9e1e3e74
Recognize memory operand codes
...
llvm-svn: 26345
2006-02-24 01:10:46 +00:00
de5a9f4517
Parse the %*# constraint modifiers
...
llvm-svn: 26341
2006-02-23 23:36:53 +00:00
e5386d4d98
Added basic support for typedefs.
...
llvm-svn: 26339
2006-02-23 22:37:30 +00:00
0ed48fe601
PPC JIT relocation model should be DynamicNoPIC.
...
llvm-svn: 26338
2006-02-23 22:18:07 +00:00
e0ed6ec13f
- Clean up the lowering and selection code of ConstantPool, GlobalAddress,
...
and ExternalSymbol.
- Use C++ code (rather than tblgen'd selection code) to match the above
mentioned leaf nodes. Do not mutate and nodes and do not record the
selection in CodeGenMap. These nodes should be safe to duplicate. This is
a performance win.
llvm-svn: 26335
2006-02-23 20:41:18 +00:00
e7c0ffb3a0
Fix an endianness problem on big-endian targets with expanded operands
...
to inline asms. Mark some methods const.
llvm-svn: 26334
2006-02-23 20:06:57 +00:00
1bad2546d0
Implement the PPC inline asm "L" modifier. This allows us to compile:
...
long long test(long long X) {
__asm__("foo %0 %L0 %1 %L1" : "=r"(X): "r"(X));
return X;
}
to:
foo r2 r3 r2 r3
llvm-svn: 26333
2006-02-23 19:31:10 +00:00
571d9647c6
Record all of the expanded registers in the DAG and machine instr, fixing
...
several bugs in inline asm expanded operands.
llvm-svn: 26332
2006-02-23 19:21:04 +00:00
69b9e26186
DwarfWriter reading basic type information from llvm-gcc4 code.
...
llvm-svn: 26331
2006-02-23 16:58:18 +00:00
2988921dc4
Code cleanups, no functionality change
...
llvm-svn: 26328
2006-02-23 06:44:17 +00:00
16f08f53b1
"." isn't enough to get a private label on linux, use ".L".
...
llvm-svn: 26327
2006-02-23 05:25:02 +00:00
2bacf981bf
add a small and simple case.
...
llvm-svn: 26326
2006-02-23 05:17:43 +00:00
f4448cee66
A couple of new entries.
...
llvm-svn: 26325
2006-02-23 02:50:21 +00:00
1f342c2884
PIC related bug fixes.
...
1. Various asm printer bug.
2. Lowering bug. Now TargetGlobalAddress is wrapped in X86ISD::TGAWrapper.
llvm-svn: 26324
2006-02-23 02:43:52 +00:00
7eabbfd618
X86 codegen tweak to use lea in another case:
...
Suppose base == %eax and it has multiple uses, then instead of
movl %eax, %ecx
addl $8, %ecx
use
leal 8(%eax), %ecx.
llvm-svn: 26323
2006-02-23 00:13:58 +00:00
7714a59d91
Missing .globl for weak / link-once .text symbols.
...
llvm-svn: 26321
2006-02-22 23:59:57 +00:00
e5521db5bc
Fix Regression/Transforms/LoopUnswitch/2006-02-22-UnswitchCrash.ll, which
...
caused SPASS to fail building last night.
We can't trivially unswitch a loop if the exit block has phi nodes in it,
because we don't know which predecessor to use.
llvm-svn: 26320
2006-02-22 23:55:00 +00:00
b1124f3c76
This fixes a couple of problems with expansion
...
llvm-svn: 26318
2006-02-22 23:09:03 +00:00
2e124af406
Don't return registers from register classes that aren't legal.
...
llvm-svn: 26317
2006-02-22 23:00:51 +00:00
6f87d18be9
Change a whole bunch of code to be built around RegsForValue instead of
...
a single register number. This fully implements promotion for inline asms,
expand is close but not quite right yet.
llvm-svn: 26316
2006-02-22 22:37:12 +00:00
73136dfecc
- Added option -relocation-model to set relocation model. Valid values include static, pic,
...
dynamic-no-pic, and default.
PPC and x86 default is dynamic-no-pic for Darwin, pic for others.
- Removed options -enable-pic and -ppc-static.
llvm-svn: 26315
2006-02-22 20:19:42 +00:00
2fa33a989d
Coordinate activities with llvm-gcc4 and dwarf.
...
llvm-svn: 26314
2006-02-22 19:02:11 +00:00
8a5a324dac
Add some comments, simplify some code, and fix a bug that caused rewriting
...
to rewrite with the wrong value.
llvm-svn: 26311
2006-02-22 06:37:14 +00:00
9e252e3bcf
Added MMX, SSE1, and SSE2 vector instructions and some simple patterns.
...
Fixed some existing bugs (wrong predicates, prefixes) at the same time.
llvm-svn: 26310
2006-02-22 02:26:30 +00:00
7ad77dfc2a
split register class handling from explicit physreg handling.
...
llvm-svn: 26308
2006-02-22 00:56:39 +00:00
5c79f98f15
Adjust to changes in getRegForInlineAsmConstraint prototype
...
llvm-svn: 26306
2006-02-21 23:12:12 +00:00
7bb4696dc3
Updates to match change of getRegForInlineAsmConstraint prototype
...
llvm-svn: 26305
2006-02-21 23:11:00 +00:00
d58478161f
One more round of reorg so sabre doesn't freak out. :-)
...
llvm-svn: 26303
2006-02-21 20:00:20 +00:00
6fc1162855
A big more cleaning up.
...
llvm-svn: 26302
2006-02-21 19:30:30 +00:00
8711b6bff3
Moving things to their proper places.
...
llvm-svn: 26301
2006-02-21 19:26:52 +00:00
6e595b9fd8
Split instruction info into multiple files, one for each of x87, MMX, and SSE.
...
llvm-svn: 26300
2006-02-21 19:13:53 +00:00
0a08f44704
missed optzn
...
llvm-svn: 26299
2006-02-21 18:29:44 +00:00
747cf60696
The HasNoV9 hack isn't needed here, now that tblgen knows that CustomDAGSchedInserter
...
instructions are expensive.
llvm-svn: 26298
2006-02-21 18:04:32 +00:00
d57203c0a1
Added separate alias instructions for SSE logical ops that operate on non-packed types.
...
llvm-svn: 26297
2006-02-21 02:24:38 +00:00
afffe63fc1
Added MMX and XMM packed integer move instructions, movd and movq.
...
llvm-svn: 26296
2006-02-21 01:39:57 +00:00
fa57a0add9
Added SSE2 128-bit integer packed types: V16I8, V8I16, V4I32, and V2I64.
...
Added generic vector types: VR64 and VR128.
llvm-svn: 26295
2006-02-21 01:38:21 +00:00
43070b7541
Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit
...
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).
llvm-svn: 26294
2006-02-20 22:34:53 +00:00
4547400ae2
Some updates
...
llvm-svn: 26292
2006-02-20 19:58:27 +00:00
301f45cf6f
Fix a problem Nate and Duraid reported where simplifying nodes can cause
...
them to get ressurected, in which case, deleting the undead nodes is
unfriendly.
llvm-svn: 26291
2006-02-20 06:51:04 +00:00
486d1bc5ed
Fix a problem on itanium with memset. The value to set has been promoted to
...
i64 before this code, so zero_ext doesn't work.
llvm-svn: 26290
2006-02-20 06:38:35 +00:00
c2e3a7a4ce
improved support for branch folding, still not enabled.
...
llvm-svn: 26289
2006-02-18 07:57:38 +00:00
d13778eb30
If SSE3 is available, promote FP_TO_UINT i32 to FP_TO_SINT i64 to take
...
advantage of fisttpll.
llvm-svn: 26288
2006-02-18 07:26:17 +00:00
0add83e969
Fix bugs identified by VC++.
...
llvm-svn: 26287
2006-02-18 03:20:33 +00:00
983ca89714
Add a fold for add that exchanges it with a constant shift if possible, so
...
that the shift may be more easily folded into other operations.
llvm-svn: 26286
2006-02-18 02:43:25 +00:00
19fa8ac938
Implement deletion of dead blocks, currently disabled.
...
llvm-svn: 26285
2006-02-18 02:42:34 +00:00
abac61603f
Add checks to make sure we don't create bogus extend nodes, and fix a bug
...
where we were doing exactly that which was causing failures on x86 and
alpha.
llvm-svn: 26284
2006-02-18 02:40:58 +00:00
70af620709
Added fisttp for fp to int conversion.
...
llvm-svn: 26283
2006-02-18 02:36:28 +00:00
06c2e6d1b3
Disable PIC for JIT.
...
llvm-svn: 26281
2006-02-18 01:49:25 +00:00
cb853de534
a previous patch completely disabled trivial unswitching, this fixees it.
...
Thanks to nate for pointing this out :)
llvm-svn: 26280
2006-02-18 01:32:04 +00:00
29f771ba21
initial trivial support for folding branches that have now-constant destinations.
...
llvm-svn: 26279
2006-02-18 01:27:45 +00:00
5caed8a231
Jit does not support PIC yet.
...
llvm-svn: 26278
2006-02-18 00:57:10 +00:00
8e44ff50b0
When unswitching a loop, make sure to update loop info with exit blocks in
...
the right loop.
llvm-svn: 26277
2006-02-18 00:55:32 +00:00
d95665188b
Fix Transforms/SimplifyCFG/2006-02-17-InfiniteUnroll.ll
...
llvm-svn: 26275
2006-02-18 00:33:17 +00:00
5588de9415
x86 / Darwin PIC support.
...
llvm-svn: 26273
2006-02-18 00:15:05 +00:00
5f99760ae7
Moved PICEnabled to include/llvm/Target/TargetOptions.h
...
llvm-svn: 26272
2006-02-18 00:08:58 +00:00
375e1a71cc
Fix a tricky issue in the SimplifyDemandedBits code where CombineTo wasn't
...
exactly the API we wanted to call into. This fixes the crash on crafty last
night.
llvm-svn: 26269
2006-02-17 21:58:01 +00:00
fb5dbadf15
Clean up DemandedBitsAreZero interface
...
Make more use of the new mask helpers in valuetypes.h
Combine (sra (srl x, c1), c1) -> sext_inreg if legal
llvm-svn: 26263
2006-02-17 19:54:08 +00:00
57b3567552
Don't expand sdiv by power of two before legalize, since it will likely
...
generate illegal nodes.
llvm-svn: 26261
2006-02-17 07:26:20 +00:00
07a2677e43
unbreak the build
...
llvm-svn: 26260
2006-02-17 07:09:27 +00:00
593bea73ba
Unbreak x86 be
...
llvm-svn: 26259
2006-02-17 07:01:52 +00:00
baddba41c7
Fix loops where the header has an exit, fixing a loop-unswitch crash on crafty
...
llvm-svn: 26258
2006-02-17 06:39:56 +00:00
5965bd19f8
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
...
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
llvm-svn: 26255
2006-02-17 05:43:56 +00:00
9ec392b2aa
Fix another miscompilation exposed by lencode, where we lowered i64->f32
...
conversions to __floatdidf instead of __floatdisf on targets that support
f32 but not i64 (e.g. sparc).
llvm-svn: 26254
2006-02-17 04:32:33 +00:00
67c21b6c46
add note about div by power of 2
...
llvm-svn: 26253
2006-02-17 04:20:13 +00:00
0d62ebd13f
Fix bug noticed by VC++.
...
llvm-svn: 26252
2006-02-17 02:12:18 +00:00
3920ce4d8d
Whoops, didn't mean to check this in yet.
...
llvm-svn: 26250
2006-02-17 00:56:19 +00:00
4a0dc0c8f6
Add a missing and useful pat frag
...
llvm-svn: 26249
2006-02-17 00:51:06 +00:00
6fd136239b
start of some new simplification code, not thoroughly tested, use at your own
...
risk :)
llvm-svn: 26248
2006-02-17 00:31:07 +00:00
b590d3a72b
Remind ourselves to revisit the "pxor vs. xorps/xorpd to clear XMM registers"
...
issue. Need to do more experiments.
llvm-svn: 26247
2006-02-17 00:04:28 +00:00
7e5496d5fe
Kill the x86 pattern isel. boom.
...
llvm-svn: 26246
2006-02-17 00:03:04 +00:00
db1dbbe8d6
Remove the entry about using movapd for SSE reg-reg moves.
...
llvm-svn: 26245
2006-02-17 00:00:58 +00:00
eb7b3380fd
pxor (for FLD0SS) encoding was missing the OpSize prefix.
...
llvm-svn: 26244
2006-02-16 23:59:30 +00:00
936cc9fe53
Remove the skeleton target, it doesn't produce useful code and there are
...
other small targets that do that can be learned from. They also have
the added advantage of being tested :)
llvm-svn: 26243
2006-02-16 23:14:50 +00:00
c3dcf5a4d7
Dumb bug. Code sees a memcpy from X+c so it increments src offset. But it
...
turns out not to point to a constant string but it forgot change the offset
back.
llvm-svn: 26242
2006-02-16 23:11:42 +00:00
24c461b51e
1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. This
...
proves to be worth 20% on Ptrdist/ks. Might be related to dependency
breaking support.
2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These
are used for FR32 / FR64 reg-to-reg copies.
3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to
spill / restore FsMOVAPSrr and FsMOVAPDrr.
llvm-svn: 26241
2006-02-16 22:45:17 +00:00
Jeff Cohen