da6aafeef4
don't copy all itinerary data
...
llvm-svn: 26633
2006-03-09 07:13:00 +00:00
399bee27f0
PriorityQueue is an instance var, use it.
...
llvm-svn: 26632
2006-03-09 06:48:37 +00:00
9e95accf4e
add some comments
...
llvm-svn: 26631
2006-03-09 06:37:29 +00:00
9df647539d
Refactor the priority mechanism one step further: now that it is a separate
...
class, sever its implementation from the interface. Now we can provide new
implementations of the same interface (priority computation) without touching
the scheduler itself.
llvm-svn: 26630
2006-03-09 06:35:14 +00:00
e363fdf318
Add support for 'special' llvm globals like debug info and static ctors/dtors.
...
llvm-svn: 26628
2006-03-09 06:14:35 +00:00
6b7847a5bc
fix a pasto
...
llvm-svn: 26627
2006-03-09 06:09:41 +00:00
920e661e50
a couple of miscellaneous things.
...
llvm-svn: 26625
2006-03-09 01:39:46 +00:00
8f0a95f664
Add #line support for CBE.
...
llvm-svn: 26621
2006-03-08 19:31:15 +00:00
faae50b66b
Add a helper method for running static ctors/dtors in the module.
...
llvm-svn: 26619
2006-03-08 18:42:46 +00:00
48a8e09ad0
add a new helper method.
...
llvm-svn: 26618
2006-03-08 18:39:13 +00:00
2698f0de7a
Get rid of the multiple copies of getStringValue. Now a Constant:: method.
...
llvm-svn: 26616
2006-03-08 18:11:07 +00:00
5005b01c20
doo de doo
...
llvm-svn: 26614
2006-03-08 06:18:46 +00:00
fd22d42945
Split the priority function computation and priority queue management out
...
of the ScheduleDAGList class into a new SchedulingPriorityQueue class.
llvm-svn: 26613
2006-03-08 05:18:27 +00:00
42e2026cb0
switch from an explicitly managed list of SUnits to a simple vector of sunits
...
llvm-svn: 26612
2006-03-08 04:54:34 +00:00
12c6d89204
Shrinkify some fields, fit to 80 columns
...
llvm-svn: 26611
2006-03-08 04:41:06 +00:00
3fe975b846
revert the previous patch, didn't mean to check it in yet
...
llvm-svn: 26610
2006-03-08 04:39:05 +00:00
af5e26c980
remove "Slot", it is dead
...
llvm-svn: 26609
2006-03-08 04:37:58 +00:00
543832d39d
Change the interface for getting a target HazardRecognizer to be more clean.
...
llvm-svn: 26608
2006-03-08 04:25:59 +00:00
2370265550
libstdc++-v3 was failing to build. Needed to handle composite types with empty
...
members (running into a zero initializer.)
llvm-svn: 26607
2006-03-08 02:07:02 +00:00
fc34f8bb48
Fix a miscompilation of 188.ammp with the new CFE. 188.ammp is accessing
...
arrays out of range in a horrible way, but we shouldn't break it anyway.
Details in the comments.
llvm-svn: 26606
2006-03-08 01:05:29 +00:00
a8dd636192
add a note
...
llvm-svn: 26605
2006-03-08 00:25:47 +00:00
70b25efa57
X86ISD::REP_STOS and X86ISD::REP_MOVS now produces a flag.
...
llvm-svn: 26604
2006-03-07 23:34:23 +00:00
adc7093fc1
Use rep/stosl; and Count 0x3; rep/stosb for memset with 4 byte aligned dest.
...
and variable value.
Similarly for memcpy.
llvm-svn: 26603
2006-03-07 23:29:39 +00:00
207291fd1a
Two things:
...
1. Don't emit debug info, or other llvm.metadata to the .cbe.c file.
2. Mark static ctors/dtors as such, so that bugpoint works on C++ code
compiled with the new CFE.
llvm-svn: 26602
2006-03-07 22:58:23 +00:00
313570fb17
Use "llvm.metadata" section for debug globals. Filter out these globals in the
...
asm printer.
llvm-svn: 26599
2006-03-07 22:00:35 +00:00
69effa2325
Switch to using a numeric id for anchors.
...
llvm-svn: 26598
2006-03-07 20:53:47 +00:00
7b87fd53f9
Fix ConstantMerge/2006-03-07-DontMergeDiffSections.ll, a problem Jim
...
hypotheticalized about, where we would incorrectly merge two globals in
different sections.
llvm-svn: 26597
2006-03-07 17:56:59 +00:00
907e13c742
add another missing store.
...
llvm-svn: 26595
2006-03-07 16:26:48 +00:00
8c73d80b08
add a couple more load/store instrs, add a newline to the end of file.
...
llvm-svn: 26594
2006-03-07 16:19:46 +00:00
3bad199894
Bitfield support.
...
llvm-svn: 26593
2006-03-07 15:51:33 +00:00
3e3219cc0a
This kinda sorta implements "things that have to lead a dispatch group".
...
llvm-svn: 26591
2006-03-07 08:30:27 +00:00
675567f77c
add some new instructions to the classifier. With this, we correctly insert
...
a nop into Freebench/neural, which speeds it up from 136->129s (~5.4%).
llvm-svn: 26590
2006-03-07 07:14:55 +00:00
05ad128dca
add some comments that describe what we model
...
llvm-svn: 26588
2006-03-07 06:44:19 +00:00
2cab13573c
Implement a very very simple hazard recognizer for LSU rejects and ctr set/read
...
flushes
llvm-svn: 26587
2006-03-07 06:32:48 +00:00
0c801bd1cf
Fix some formatting, when looking for hazards, prefer target nodes over
...
things like copyfromreg.
llvm-svn: 26586
2006-03-07 05:40:43 +00:00
883cefc656
add a note
...
llvm-svn: 26585
2006-03-07 04:42:59 +00:00
bccb0e07f0
add a note
...
llvm-svn: 26583
2006-03-07 02:46:26 +00:00
a4a4ceb478
- Emit subsections_via_symbols for Darwin.
...
- Conditionalize Dwarf debugging output (Darwin only for now).
llvm-svn: 26582
2006-03-07 02:23:26 +00:00
30d7b70b73
Enable Dwarf debugging info.
...
llvm-svn: 26581
2006-03-07 02:02:57 +00:00
53ef5a032c
Teach the alignment handling code to look through constant expr casts and GEPs
...
llvm-svn: 26580
2006-03-07 01:28:57 +00:00
82f2ef20b6
Teach instcombine to increase the alignment of memset/memcpy/memmove when
...
the pointer is known to come from either a global variable, alloca or
malloc. This allows us to compile this:
P = malloc(28);
memset(P, 0, 28);
into explicit stores on PPC instead of a memset call.
llvm-svn: 26577
2006-03-06 20:18:44 +00:00
01aa752a36
update file comment
...
llvm-svn: 26573
2006-03-06 17:58:04 +00:00
a00c61932d
Remove some code that doesn't make sense
...
llvm-svn: 26572
2006-03-06 07:31:44 +00:00
c5c0658aa6
Remove SUnit::Priority1: it is re-calculated on demand as number of live
...
range to be generated.
llvm-svn: 26570
2006-03-06 06:08:54 +00:00
47639dbb93
Hoist the HazardRecognizer out of the ScheduleDAGList.cpp file to where
...
targets can implement them. Make the top-down scheduler non-g5-specific.
Remove the old testing hazard recognizer.
llvm-svn: 26569
2006-03-06 00:22:00 +00:00
00b52ea8f9
Comment fixes
...
llvm-svn: 26567
2006-03-05 23:59:20 +00:00
80268aaeed
Don't depend on the C99 copysign function, implement it ourselves.
...
llvm-svn: 26566
2006-03-05 23:57:58 +00:00
2d945ba4c7
When a hazard recognizer needs noops to be inserted, do so. This represents
...
noops as null pointers in the instruction sequence.
llvm-svn: 26564
2006-03-05 23:51:47 +00:00
ea79d9fd73
implement TII::insertNoop
...
llvm-svn: 26562
2006-03-05 23:49:55 +00:00
fa5e1c9c26
Implement G5HazardRecognizer as a trivial thing that wants 5 cycles between
...
copyfromreg nodes. Clearly useful!
llvm-svn: 26559
2006-03-05 23:13:56 +00:00
e50c092b7c
Add basic hazard recognizer support. noop insertion isn't complete yet though.
...
llvm-svn: 26558
2006-03-05 22:45:01 +00:00
55e2aac24b
Fix VC++ compilation error.
...
llvm-svn: 26554
2006-03-05 21:43:37 +00:00
98ecb8ec61
Split the list scheduler into top-down and bottom-up pieces. The priority
...
function of the top-down scheduler are completely bogus currently, and
having (future) PPC specific in this file is also wrong, but this is a
small incremental step.
llvm-svn: 26552
2006-03-05 21:10:33 +00:00
7a36d97518
Move the available queue to being inside the ListSchedule method, since it
...
bounds its lifetime.
llvm-svn: 26550
2006-03-05 20:21:55 +00:00
5032c32d30
add a note
...
llvm-svn: 26549
2006-03-05 20:00:08 +00:00
bdaf4f38b5
Reinstate this now that the offending opposite xform has been removed.
...
llvm-svn: 26548
2006-03-05 19:53:55 +00:00
c726a5c31f
Do not fold (add (shl x, c1), (shl c2, c1)) -> (shl (add x, c2), c1),
...
we want to canonicalize the other way.
llvm-svn: 26547
2006-03-05 19:52:57 +00:00
c610e62e46
print arbitrary constant pool entries
...
llvm-svn: 26545
2006-03-05 09:38:03 +00:00
d428e22c07
Back out fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2) for now.
...
It's causing an infinite loop compiling ldecod on x86 / Darwin.
llvm-svn: 26544
2006-03-05 07:30:16 +00:00
3bc4050217
Add some simple copysign folds
...
llvm-svn: 26543
2006-03-05 05:30:57 +00:00
5c1ba2ac08
Codegen copysign[f] into a FCOPYSIGN node
...
llvm-svn: 26542
2006-03-05 05:09:38 +00:00
9c7f50376a
Copysign needs to be expanded everywhere. Note that Alpha and IA64 should
...
implement copysign as a native op if they have it.
llvm-svn: 26541
2006-03-05 05:08:37 +00:00
c2dd7aae71
add a note for something evan noticed
...
llvm-svn: 26539
2006-03-05 01:15:18 +00:00
6bc98653c2
Make vector narrowing more effective, implementing
...
Transforms/InstCombine/vec_narrow.ll. This add support for narrowing
extract_element(insertelement) also.
llvm-svn: 26538
2006-03-05 00:22:33 +00:00
8d8b4cf63d
Implemented.
...
llvm-svn: 26536
2006-03-04 23:33:44 +00:00
f29f5204cc
fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
...
fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
This allows us to compile CodeGen/PowerPC/addi-reassoc.ll into:
_test1:
slwi r2, r4, 4
add r2, r2, r3
lwz r3, 36(r2)
blr
_test2:
mulli r2, r4, 5
add r2, r2, r3
lbz r2, 11(r2)
extsb r3, r2
blr
instead of:
_test1:
addi r2, r4, 2
slwi r2, r2, 4
add r2, r3, r2
lwz r3, 4(r2)
blr
_test2:
addi r2, r4, 2
mulli r2, r2, 5
add r2, r3, r2
lbz r2, 1(r2)
extsb r3, r2
blr
llvm-svn: 26535
2006-03-04 23:33:26 +00:00
3e19c23765
Fix a crash compiling Obsequi
...
llvm-svn: 26529
2006-03-04 21:48:01 +00:00
4c065091d8
Add factoring of multiplications, e.g. turning A*A+A*B into A*(A+B).
...
Testcase here: Transforms/Reassociate/mulfactor.ll
llvm-svn: 26524
2006-03-04 09:31:13 +00:00
c9a318d8fa
Add a note
...
llvm-svn: 26523
2006-03-04 08:44:51 +00:00
adf5ec6f96
Regenerate
...
llvm-svn: 26522
2006-03-04 07:53:41 +00:00
a33bcff313
Don't use invalidated iterators!
...
llvm-svn: 26521
2006-03-04 07:53:16 +00:00
c66fd44541
Add an entry
...
llvm-svn: 26520
2006-03-04 07:49:50 +00:00
32c01df299
Canonicalize (X+C1)*C2 -> X*C2+C1*C2
...
This implements Transforms/InstCombine/add.ll:test31
llvm-svn: 26519
2006-03-04 06:04:02 +00:00
6dc73297c3
MEMSET / MEMCPY lowering bugs: we can't issue a single WORD / DWORD version of
...
rep/stos and rep/mov if the count is not a constant. We could do
rep/stosl; and $count, 3; rep/stosb
For now, I will lower them to memset / memcpy calls. We will revisit this after
a little bit experiment.
Also need to take care of the trailing bytes even if the count is a constant.
Since the max. number of trailing bytes are 3, we will simply issue loads /
stores.
llvm-svn: 26517
2006-03-04 02:48:56 +00:00
071faf25e0
Be more conservative with our symbolic alias analysis. In particular,
...
don't assume that A[1][0] and A[0][i] can't alias. "i" might be out of
range, or even negative. This fixes a miscompilation of 188.ammp (which
does bad pointer tricks) with the new CFE.
Testcase here: Analysis/BasicAA/2006-03-03-BadArraySubscript.ll
llvm-svn: 26515
2006-03-04 02:06:34 +00:00
e43e5c0697
add a note
...
llvm-svn: 26513
2006-03-04 01:19:34 +00:00
084a102b17
Typo
...
llvm-svn: 26512
2006-03-04 01:12:00 +00:00
c44f05d624
Added support for dwarf block data entries.
...
llvm-svn: 26509
2006-03-03 21:00:14 +00:00
c2de4f3dc1
Unbreak autouprade of llvm.sqrt, simplify some code.
...
llvm-svn: 26506
2006-03-03 16:31:22 +00:00
88f0fe15a2
Adding basic structure support.
...
llvm-svn: 26505
2006-03-03 15:06:57 +00:00
3bf916ddd9
Add more vector NodeTypes: VSDIV, VUDIV, VAND, VOR, and VXOR.
...
llvm-svn: 26504
2006-03-03 07:01:07 +00:00
a7fb285c60
Number of NodeTypes now exceeds 128.
...
llvm-svn: 26503
2006-03-03 06:58:59 +00:00
23e75f5b49
SDOperand::isOperand should not be a forwarding. It must check *this against N's operands.
...
llvm-svn: 26502
2006-03-03 06:42:32 +00:00
6b08ae8497
Added isOperand(N): true if this is an operand of N
...
llvm-svn: 26501
2006-03-03 06:24:54 +00:00
5e9a695026
A bit more tweaking
...
llvm-svn: 26500
2006-03-03 06:23:43 +00:00
55c1173a6c
Fix VC++ compilation errors.
...
llvm-svn: 26498
2006-03-03 03:25:07 +00:00
993e9cf26e
Move #include "llvm/CodeGen/AsmPrinter.h" to top since it's the interface.
...
llvm-svn: 26493
2006-03-03 02:04:29 +00:00
b203355298
Split the valuetypes out of Target.td into ValueTypes.td
...
llvm-svn: 26490
2006-03-03 01:55:26 +00:00
681ef2f083
Change this to work with renamed intrinsics.
...
llvm-svn: 26484
2006-03-03 01:34:17 +00:00
ea7986aeca
Make this work with renamed intrinsics.
...
llvm-svn: 26482
2006-03-03 01:30:23 +00:00
bce2626d8a
updates for recent changes
...
llvm-svn: 26481
2006-03-03 01:21:36 +00:00
ad3c974a77
remove the read/write port/io intrinsics.
...
llvm-svn: 26479
2006-03-03 00:19:58 +00:00
093c159efb
Split memcpy/memset/memmove intrinsics into i32/i64 versions, resolving
...
PR709, and paving the way for future progress.
llvm-svn: 26476
2006-03-03 00:00:25 +00:00
259d680c15
Simplify the autoupgrade interface
...
llvm-svn: 26475
2006-03-02 23:59:12 +00:00
d124535de1
Split memcpy/memset/memmove intrinsics into i32/i64 versions, resolving
...
PR709, and paving the way for future progress.
Significantly refactor autoupgrading code, to handle the more complex case
(where we upgrade one argument in a function), and fix some bugs in it.
Testcase here: llvm/test/Regression/Bytecode/memcpy.ll
llvm-svn: 26474
2006-03-02 23:58:40 +00:00
9067500e2e
add a note
...
llvm-svn: 26472
2006-03-02 22:34:38 +00:00
4e3904f637
- Fixed some priority calculation bugs that were causing bug 478. Among them:
...
a predecessor appearing more than once in the operand list was counted as
multiple predecessor; priority1 should be updated during scheduling;
CycleBound was updated after the node is inserted into priority queue; one
of the tie breaking condition was flipped.
- Take into consideration of two address opcodes. If a predecessor is a def&use
operand, it should have a higher priority.
- Scheduler should also favor floaters, i.e. nodes that do not have real
predecessors such as MOV32ri.
- The scheduling fixes / tweaks fixed bug 478:
.text
.align 4
.globl _f
_f:
movl 4(%esp), %eax
movl 8(%esp), %ecx
movl %eax, %edx
imull %ecx, %edx
imull %eax, %eax
imull %ecx, %ecx
addl %eax, %ecx
leal (%ecx,%edx,2), %eax
ret
It is also a slight performance win (1% - 3%) for most tests.
llvm-svn: 26470
2006-03-02 21:38:29 +00:00
85dda9a2bd
Generalize the REM folding code to handle another case Nick Lewycky
...
pointed out: realize the AND can provide factors and look through Casts.
llvm-svn: 26469
2006-03-02 06:50:58 +00:00
862001ad75
Support for enumerations.
...
llvm-svn: 26466
2006-03-01 23:52:37 +00:00
38d5e768b2
Don't print llvm constant in assmebly file. Assembler won't like comments that
...
span multiple lines.
llvm-svn: 26463
2006-03-01 22:18:09 +00:00
5b19a80321
Back out my last check-in. Wrong place to fix it.
...
llvm-svn: 26462
2006-03-01 22:17:00 +00:00
302bdb586f
AsmWriter should not print LLVM constant in comment. Assembler won't like
...
multi-line comments.
llvm-svn: 26461
2006-03-01 22:00:59 +00:00
0db2f2c689
Fix CodeGen/Generic/2006-03-01-dagcombineinfloop.ll, an infinite loop
...
in the dag combiner on 176.gcc on x86.
llvm-svn: 26459
2006-03-01 21:47:21 +00:00
4e71db13d6
Switch back to using actual dwarf tags. Simplifies code without loss to other
...
debug forms.
llvm-svn: 26455
2006-03-01 20:39:36 +00:00
232024edb8
Fix a typo evan noticed
...
llvm-svn: 26454
2006-03-01 19:55:35 +00:00
f770cf5b90
Use context and not compile unit.
...
llvm-svn: 26453
2006-03-01 18:20:30 +00:00
1246d5c054
I guess I can handle large type sizes.
...
llvm-svn: 26452
2006-03-01 18:13:05 +00:00
b9ac4cba66
Basic array support.
...
llvm-svn: 26451
2006-03-01 17:53:02 +00:00
60a60f4b1e
Implement CodeGen/PowerPC/or-addressing-mode.ll, which is also PR668.
...
llvm-svn: 26450
2006-03-01 07:14:48 +00:00
3cb349a068
add a note
...
llvm-svn: 26448
2006-03-01 06:36:20 +00:00
27f5345b1f
Compile this:
...
void foo(float a, int *b) { *b = a; }
to this:
_foo:
fctiwz f0, f1
stfiwx f0, 0, r4
blr
instead of this:
_foo:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
stw r2, 0(r4)
blr
This implements CodeGen/PowerPC/stfiwx.ll, and also incidentally does the
right thing for GCC bugzilla 26505.
llvm-svn: 26447
2006-03-01 05:50:56 +00:00
f418435819
Use a target-specific dag-combine to implement CodeGen/PowerPC/fp-int-fp.ll.
...
llvm-svn: 26445
2006-03-01 04:57:39 +00:00
bc1c85beea
Add support for target-specific dag combines
...
llvm-svn: 26443
2006-03-01 04:53:38 +00:00
4a2eeea671
Add interfaces for targets to provide target-specific dag combiner optimizations.
...
llvm-svn: 26442
2006-03-01 04:52:55 +00:00
fbcd62d3bb
Add a new AddToWorkList method, start using it
...
llvm-svn: 26441
2006-03-01 04:03:14 +00:00
324871ef1a
Pull shifts by a constant through multiplies (a form of reassociation),
...
implementing Regression/CodeGen/X86/mul-shift-reassoc.ll
llvm-svn: 26440
2006-03-01 03:44:24 +00:00
1926427351
Vector op lowering.
...
llvm-svn: 26438
2006-03-01 01:11:20 +00:00
b97aab4371
Vector ops lowering.
...
llvm-svn: 26436
2006-03-01 01:09:54 +00:00
91c574b642
New type v2f32.
...
llvm-svn: 26435
2006-03-01 01:06:22 +00:00
be85e89ec4
- Added VConstant as an abstract version of ConstantVec.
...
- All abstrct vector nodes must have # of elements and element type as their
first two operands.
llvm-svn: 26432
2006-03-01 00:51:13 +00:00
0e69f45b07
Another entry.
...
llvm-svn: 26430
2006-02-28 23:38:49 +00:00
990c3602bd
Don't match x << 1 to LEAL. It's better to emit x + x.
...
llvm-svn: 26429
2006-02-28 21:13:57 +00:00
716edb9754
Add const, volatile, restrict support.
...
Add array of debug descriptor support.
llvm-svn: 26428
2006-02-28 20:15:07 +00:00
c5b6c9a12a
Fix a regression in a patch from a couple of days ago. This fixes
...
Transforms/InstCombine/2006-02-28-Crash.ll
llvm-svn: 26427
2006-02-28 19:47:20 +00:00
b9f35f06bc
Add a subtarget feature for the stfiwx instruction. I know the G5 has it,
...
but I don't know what other PPC impls do. If someone could update the proc
table, I would appreciate it :)
llvm-svn: 26421
2006-02-28 07:08:22 +00:00
f0032b350c
Compile:
...
unsigned foo4(unsigned short *P) { return *P & 255; }
unsigned foo5(short *P) { return *P & 255; }
to:
_foo4:
lbz r3,1(r3)
blr
_foo5:
lbz r3,1(r3)
blr
not:
_foo4:
lhz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
_foo5:
lhz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
llvm-svn: 26419
2006-02-28 06:49:37 +00:00
872810da6c
remove implemented item
...
llvm-svn: 26418
2006-02-28 06:36:04 +00:00
bdbc4476d9
Fold "and (LOAD P), 255" -> zextload. This allows us to compile:
...
unsigned foo3(unsigned *P) { return *P & 255; }
as:
_foo3:
lbz r3, 3(r3)
blr
instead of:
_foo3:
lwz r2, 0(r3)
rlwinm r3, r2, 0, 24, 31
blr
and:
unsigned short foo2(float a) { return a; }
as:
_foo2:
fctiwz f0, f1
stfd f0, -8(r1)
lhz r3, -2(r1)
blr
instead of:
_foo2:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
rlwinm r3, r2, 0, 16, 31
blr
llvm-svn: 26417
2006-02-28 06:35:35 +00:00
0f8a727c49
fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
...
llvm-svn: 26416
2006-02-28 06:23:04 +00:00
b70f141893
Implement rem.ll:test[7-9] and PR712
...
llvm-svn: 26415
2006-02-28 05:49:21 +00:00
2a7c7b8bab
Simplify some code now that the RHS of a rem can't be 0
...
llvm-svn: 26413
2006-02-28 05:40:55 +00:00
0de4a8d7b7
Rearrange some code, fold "rem X, 0", implementing rem.ll:test6
...
llvm-svn: 26411
2006-02-28 05:30:45 +00:00
9fed5b6122
Add support for output memory constraints.
...
llvm-svn: 26410
2006-02-27 23:45:39 +00:00
6d5c2a0156
Qualify dwarf namespace inside llvm namespace.
...
llvm-svn: 26409
2006-02-27 22:37:23 +00:00
f918ed2e33
readme updates
...
llvm-svn: 26405
2006-02-27 22:08:36 +00:00
bc7a3832e8
Partial enabling of functions.
...
llvm-svn: 26404
2006-02-27 20:37:42 +00:00
ec185f7843
Don't print constant initializers, they may span lines now.
...
llvm-svn: 26403
2006-02-27 20:09:23 +00:00
72b66d6d8a
Supporting multiple compile units.
...
llvm-svn: 26402
2006-02-27 17:27:12 +00:00
22e47b9f4e
Re-orging file.
...
llvm-svn: 26401
2006-02-27 12:43:29 +00:00
6be3d8e0df
Pretty print large struct constants.
...
llvm-svn: 26400
2006-02-27 10:33:53 +00:00
8f2c1021b4
Removed dependency on how operands are printed (want multi-line.)
...
llvm-svn: 26399
2006-02-27 10:29:04 +00:00
c7bfed0f7b
Merge two almost-identical pieces of code.
...
Make this code more powerful by using ComputeMaskedBits instead of looking
for an AND operand. This lets us fold this:
int %test23(int %a) {
%tmp.1 = and int %a, 1
%tmp.2 = seteq int %tmp.1, 0
%tmp.3 = cast bool %tmp.2 to int ;; xor tmp1, 1
ret int %tmp.3
}
into: xor (and a, 1), 1
llvm-svn: 26396
2006-02-27 02:38:23 +00:00
f5c8a0b83f
Fold (A^B) == A -> B == 0
...
and (A-B) == A -> B == 0
llvm-svn: 26394
2006-02-27 01:44:11 +00:00
ab8164042a
Implement bit propagation through sub nodes, this (re)implements
...
PowerPC/div-2.ll
llvm-svn: 26392
2006-02-27 01:00:42 +00:00
47ee42829d
remove some completed notes
...
llvm-svn: 26390
2006-02-27 00:39:31 +00:00
a60751dd43
Check RHS simplification before LHS simplification to avoid infinitely looping
...
on PowerPC/small-arguments.ll
llvm-svn: 26389
2006-02-27 00:36:27 +00:00
27220f8958
Just like we use the RHS of an AND to simplify the LHS, use the LHS to
...
simplify the RHS. This allows for the elimination of many thousands of
ands from multisource, and compiles CodeGen/PowerPC/and-elim.ll:test2
into this:
_test2:
srwi r2, r3, 1
xori r3, r2, 40961
blr
instead of this:
_test2:
rlwinm r2, r3, 31, 17, 31
xori r2, r2, 40961
rlwinm r3, r2, 0, 16, 31
blr
llvm-svn: 26388
2006-02-27 00:22:28 +00:00
118ddba929
Add a bunch of missed cases. Perhaps the most significant of which is that
...
assertzext produces zero bits.
llvm-svn: 26386
2006-02-26 23:36:02 +00:00
f78df7c14d
Fold (X|C1)^C2 -> X^(C1|C2) when possible. This implements
...
InstCombine/or.ll:test23.
llvm-svn: 26385
2006-02-26 19:57:54 +00:00
702c1d11b5
Reverting. Didn't realize some developers were embedding constants in their
...
target assembler code gen.
llvm-svn: 26383
2006-02-26 10:16:05 +00:00
877ab55e06
ConstantPoolIndex is now the displacement portion of the address (rather
...
than base).
llvm-svn: 26382
2006-02-26 09:12:34 +00:00
9f9662b86e
Print ConstantPoolSDNode offset field.
...
llvm-svn: 26381
2006-02-26 08:36:57 +00:00
75b8783aaf
Fixed ConstantPoolIndex operand asm print bug. This fixed 2005-07-17-INT-To-FP
...
and 2005-05-12-Int64ToFP.
llvm-svn: 26380
2006-02-26 08:28:12 +00:00
3bb7874dd3
Format large struct constants for readability.
...
llvm-svn: 26379
2006-02-25 12:27:03 +00:00
77d86ff8fc
* Cleaned up addressing mode matching code.
...
* Cleaned up and tweaked LEA cost analysis code. Removed some hacks.
* Handle ADD $X, c to MOV32ri $X+c. These patterns cannot be autogen'd and
they need to be matched before LEA.
llvm-svn: 26376
2006-02-25 10:09:08 +00:00
1c557bfeb5
Updates.
...
llvm-svn: 26375
2006-02-25 10:04:07 +00:00
1fac3b3360
* Allow mul, shl nodes to be codegen'd as LEA (if appropriate).
...
* Add patterns to handle GlobalAddress, ConstantPool, etc.
MOV32ri to materialize these nodes in registers.
ADD32ri to handle %reg + GA, etc.
MOV32mi to handle store GA, etc. to memory.
llvm-svn: 26374
2006-02-25 10:02:21 +00:00
e4a8b74e4f
ConstantPoolIndex is now the displacement field of addressing mode.
...
llvm-svn: 26373
2006-02-25 09:56:50 +00:00
994700101e
Added a common about the need for X86ISD::Wrapper.
...
llvm-svn: 26372
2006-02-25 09:55:19 +00:00
ed169db8a5
Added an offset field to ConstantPoolSDNode.
...
llvm-svn: 26371
2006-02-25 09:54:52 +00:00
7d01f95a57
Fix a bug that Evan exposed with some changes he's making, and that was
...
exposed with a fastcc problem (breaking pcompress2 on x86 with -enable-x86-fastcc).
When reloading a reused reg, make sure to invalidate the reloaded reg, and
check to see if there are any other pending uses of the same register.
llvm-svn: 26369
2006-02-25 02:17:31 +00:00
28a0b8bec7
Remove debugging printout :)
...
Add a minor compile time win, no codegen change.
llvm-svn: 26368
2006-02-25 02:03:40 +00:00
525522e429
Refactor some code from being inline to being out in a new class with methods.
...
This gets rid of two gotos, which is always nice, and also adds some comments.
No functionality change, this is just a refactor.
llvm-svn: 26367
2006-02-25 01:51:33 +00:00
42d5ac557c
Fix an obvious bug exposed when we are doing
...
ADD X, 4
==>
MOV32ri $X+4, ...
llvm-svn: 26366
2006-02-25 01:37:02 +00:00
7674d90fa1
Add memory printing support for PPC. Input memory operands now work with
...
inline asms! :)
llvm-svn: 26365
2006-02-24 20:27:40 +00:00
1d08c6534c
Use the PrintAsmMemoryOperand to print addressing modes.
...
llvm-svn: 26364
2006-02-24 20:21:58 +00:00
5af3fdec12
Pass all the flags to the asm printer, not just the # operands.
...
llvm-svn: 26362
2006-02-24 19:50:58 +00:00
2f8a794b13
rename NumOps -> NumVals to avoid shadowing a NumOps var in an outer scope.
...
Add support for addressing modes.
llvm-svn: 26361
2006-02-24 19:18:20 +00:00
86c51000db
Refactor operand adding out to a new AddOperand method
...
llvm-svn: 26358
2006-02-24 18:54:03 +00:00
b580d26e7d
Fix a problem that Nate noticed that boils down to an over conservative check
...
in the code that does "select C, (X+Y), (X-Y) --> (X+(select C, Y, (-Y)))".
We now compile this loop:
LBB1_1: ; no_exit
add r6, r2, r3
subf r3, r2, r3
cmpwi cr0, r2, 0
addi r7, r5, 4
lwz r2, 0(r5)
addi r4, r4, 1
blt cr0, LBB1_4 ; no_exit
LBB1_3: ; no_exit
mr r3, r6
LBB1_4: ; no_exit
cmpwi cr0, r4, 16
mr r5, r7
bne cr0, LBB1_1 ; no_exit
into this instead:
LBB1_1: ; no_exit
srawi r6, r2, 31
add r2, r2, r6
xor r6, r2, r6
addi r7, r5, 4
lwz r2, 0(r5)
addi r4, r4, 1
add r3, r3, r6
cmpwi cr0, r4, 16
mr r5, r7
bne cr0, LBB1_1 ; no_exit
llvm-svn: 26356
2006-02-24 18:05:58 +00:00
723d3e0746
Add pointer and reference types. Added short-term code to ignore NULL types
...
(to allow llvm-gcc4 to build.)
llvm-svn: 26355
2006-02-24 16:46:40 +00:00
83c22e0d75
Get VC++ building again.
...
llvm-svn: 26351
2006-02-24 02:52:40 +00:00
dcf785bf46
Implement (most of) selection of inline asm memory operands.
...
llvm-svn: 26350
2006-02-24 02:13:54 +00:00
a1ec1ddd59
Implement selection of inline asm memory operands
...
llvm-svn: 26348
2006-02-24 02:13:12 +00:00
7ef7a64ebb
Lower C_Memory operands.
...
llvm-svn: 26346
2006-02-24 01:11:24 +00:00
2a9e1e3e74
Recognize memory operand codes
...
llvm-svn: 26345
2006-02-24 01:10:46 +00:00
de5a9f4517
Parse the %*# constraint modifiers
...
llvm-svn: 26341
2006-02-23 23:36:53 +00:00
e5386d4d98
Added basic support for typedefs.
...
llvm-svn: 26339
2006-02-23 22:37:30 +00:00
0ed48fe601
PPC JIT relocation model should be DynamicNoPIC.
...
llvm-svn: 26338
2006-02-23 22:18:07 +00:00
e0ed6ec13f
- Clean up the lowering and selection code of ConstantPool, GlobalAddress,
...
and ExternalSymbol.
- Use C++ code (rather than tblgen'd selection code) to match the above
mentioned leaf nodes. Do not mutate and nodes and do not record the
selection in CodeGenMap. These nodes should be safe to duplicate. This is
a performance win.
llvm-svn: 26335
2006-02-23 20:41:18 +00:00
e7c0ffb3a0
Fix an endianness problem on big-endian targets with expanded operands
...
to inline asms. Mark some methods const.
llvm-svn: 26334
2006-02-23 20:06:57 +00:00
1bad2546d0
Implement the PPC inline asm "L" modifier. This allows us to compile:
...
long long test(long long X) {
__asm__("foo %0 %L0 %1 %L1" : "=r"(X): "r"(X));
return X;
}
to:
foo r2 r3 r2 r3
llvm-svn: 26333
2006-02-23 19:31:10 +00:00
571d9647c6
Record all of the expanded registers in the DAG and machine instr, fixing
...
several bugs in inline asm expanded operands.
llvm-svn: 26332
2006-02-23 19:21:04 +00:00
69b9e26186
DwarfWriter reading basic type information from llvm-gcc4 code.
...
llvm-svn: 26331
2006-02-23 16:58:18 +00:00
2988921dc4
Code cleanups, no functionality change
...
llvm-svn: 26328
2006-02-23 06:44:17 +00:00
16f08f53b1
"." isn't enough to get a private label on linux, use ".L".
...
llvm-svn: 26327
2006-02-23 05:25:02 +00:00
2bacf981bf
add a small and simple case.
...
llvm-svn: 26326
2006-02-23 05:17:43 +00:00
f4448cee66
A couple of new entries.
...
llvm-svn: 26325
2006-02-23 02:50:21 +00:00
1f342c2884
PIC related bug fixes.
...
1. Various asm printer bug.
2. Lowering bug. Now TargetGlobalAddress is wrapped in X86ISD::TGAWrapper.
llvm-svn: 26324
2006-02-23 02:43:52 +00:00
7eabbfd618
X86 codegen tweak to use lea in another case:
...
Suppose base == %eax and it has multiple uses, then instead of
movl %eax, %ecx
addl $8, %ecx
use
leal 8(%eax), %ecx.
llvm-svn: 26323
2006-02-23 00:13:58 +00:00
7714a59d91
Missing .globl for weak / link-once .text symbols.
...
llvm-svn: 26321
2006-02-22 23:59:57 +00:00
e5521db5bc
Fix Regression/Transforms/LoopUnswitch/2006-02-22-UnswitchCrash.ll, which
...
caused SPASS to fail building last night.
We can't trivially unswitch a loop if the exit block has phi nodes in it,
because we don't know which predecessor to use.
llvm-svn: 26320
2006-02-22 23:55:00 +00:00
b1124f3c76
This fixes a couple of problems with expansion
...
llvm-svn: 26318
2006-02-22 23:09:03 +00:00
2e124af406
Don't return registers from register classes that aren't legal.
...
llvm-svn: 26317
2006-02-22 23:00:51 +00:00
6f87d18be9
Change a whole bunch of code to be built around RegsForValue instead of
...
a single register number. This fully implements promotion for inline asms,
expand is close but not quite right yet.
llvm-svn: 26316
2006-02-22 22:37:12 +00:00
73136dfecc
- Added option -relocation-model to set relocation model. Valid values include static, pic,
...
dynamic-no-pic, and default.
PPC and x86 default is dynamic-no-pic for Darwin, pic for others.
- Removed options -enable-pic and -ppc-static.
llvm-svn: 26315
2006-02-22 20:19:42 +00:00
2fa33a989d
Coordinate activities with llvm-gcc4 and dwarf.
...
llvm-svn: 26314
2006-02-22 19:02:11 +00:00
8a5a324dac
Add some comments, simplify some code, and fix a bug that caused rewriting
...
to rewrite with the wrong value.
llvm-svn: 26311
2006-02-22 06:37:14 +00:00
9e252e3bcf
Added MMX, SSE1, and SSE2 vector instructions and some simple patterns.
...
Fixed some existing bugs (wrong predicates, prefixes) at the same time.
llvm-svn: 26310
2006-02-22 02:26:30 +00:00
7ad77dfc2a
split register class handling from explicit physreg handling.
...
llvm-svn: 26308
2006-02-22 00:56:39 +00:00
5c79f98f15
Adjust to changes in getRegForInlineAsmConstraint prototype
...
llvm-svn: 26306
2006-02-21 23:12:12 +00:00
7bb4696dc3
Updates to match change of getRegForInlineAsmConstraint prototype
...
llvm-svn: 26305
2006-02-21 23:11:00 +00:00
d58478161f
One more round of reorg so sabre doesn't freak out. :-)
...
llvm-svn: 26303
2006-02-21 20:00:20 +00:00
6fc1162855
A big more cleaning up.
...
llvm-svn: 26302
2006-02-21 19:30:30 +00:00
8711b6bff3
Moving things to their proper places.
...
llvm-svn: 26301
2006-02-21 19:26:52 +00:00
6e595b9fd8
Split instruction info into multiple files, one for each of x87, MMX, and SSE.
...
llvm-svn: 26300
2006-02-21 19:13:53 +00:00
0a08f44704
missed optzn
...
llvm-svn: 26299
2006-02-21 18:29:44 +00:00
747cf60696
The HasNoV9 hack isn't needed here, now that tblgen knows that CustomDAGSchedInserter
...
instructions are expensive.
llvm-svn: 26298
2006-02-21 18:04:32 +00:00
d57203c0a1
Added separate alias instructions for SSE logical ops that operate on non-packed types.
...
llvm-svn: 26297
2006-02-21 02:24:38 +00:00
afffe63fc1
Added MMX and XMM packed integer move instructions, movd and movq.
...
llvm-svn: 26296
2006-02-21 01:39:57 +00:00
fa57a0add9
Added SSE2 128-bit integer packed types: V16I8, V8I16, V4I32, and V2I64.
...
Added generic vector types: VR64 and VR128.
llvm-svn: 26295
2006-02-21 01:38:21 +00:00
43070b7541
Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit
...
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).
llvm-svn: 26294
2006-02-20 22:34:53 +00:00
4547400ae2
Some updates
...
llvm-svn: 26292
2006-02-20 19:58:27 +00:00
301f45cf6f
Fix a problem Nate and Duraid reported where simplifying nodes can cause
...
them to get ressurected, in which case, deleting the undead nodes is
unfriendly.
llvm-svn: 26291
2006-02-20 06:51:04 +00:00
486d1bc5ed
Fix a problem on itanium with memset. The value to set has been promoted to
...
i64 before this code, so zero_ext doesn't work.
llvm-svn: 26290
2006-02-20 06:38:35 +00:00
c2e3a7a4ce
improved support for branch folding, still not enabled.
...
llvm-svn: 26289
2006-02-18 07:57:38 +00:00
d13778eb30
If SSE3 is available, promote FP_TO_UINT i32 to FP_TO_SINT i64 to take
...
advantage of fisttpll.
llvm-svn: 26288
2006-02-18 07:26:17 +00:00
0add83e969
Fix bugs identified by VC++.
...
llvm-svn: 26287
2006-02-18 03:20:33 +00:00
983ca89714
Add a fold for add that exchanges it with a constant shift if possible, so
...
that the shift may be more easily folded into other operations.
llvm-svn: 26286
2006-02-18 02:43:25 +00:00
19fa8ac938
Implement deletion of dead blocks, currently disabled.
...
llvm-svn: 26285
2006-02-18 02:42:34 +00:00
abac61603f
Add checks to make sure we don't create bogus extend nodes, and fix a bug
...
where we were doing exactly that which was causing failures on x86 and
alpha.
llvm-svn: 26284
2006-02-18 02:40:58 +00:00
70af620709
Added fisttp for fp to int conversion.
...
llvm-svn: 26283
2006-02-18 02:36:28 +00:00
06c2e6d1b3
Disable PIC for JIT.
...
llvm-svn: 26281
2006-02-18 01:49:25 +00:00
cb853de534
a previous patch completely disabled trivial unswitching, this fixees it.
...
Thanks to nate for pointing this out :)
llvm-svn: 26280
2006-02-18 01:32:04 +00:00
29f771ba21
initial trivial support for folding branches that have now-constant destinations.
...
llvm-svn: 26279
2006-02-18 01:27:45 +00:00
5caed8a231
Jit does not support PIC yet.
...
llvm-svn: 26278
2006-02-18 00:57:10 +00:00
8e44ff50b0
When unswitching a loop, make sure to update loop info with exit blocks in
...
the right loop.
llvm-svn: 26277
2006-02-18 00:55:32 +00:00
d95665188b
Fix Transforms/SimplifyCFG/2006-02-17-InfiniteUnroll.ll
...
llvm-svn: 26275
2006-02-18 00:33:17 +00:00
5588de9415
x86 / Darwin PIC support.
...
llvm-svn: 26273
2006-02-18 00:15:05 +00:00
5f99760ae7
Moved PICEnabled to include/llvm/Target/TargetOptions.h
...
llvm-svn: 26272
2006-02-18 00:08:58 +00:00
375e1a71cc
Fix a tricky issue in the SimplifyDemandedBits code where CombineTo wasn't
...
exactly the API we wanted to call into. This fixes the crash on crafty last
night.
llvm-svn: 26269
2006-02-17 21:58:01 +00:00
fb5dbadf15
Clean up DemandedBitsAreZero interface
...
Make more use of the new mask helpers in valuetypes.h
Combine (sra (srl x, c1), c1) -> sext_inreg if legal
llvm-svn: 26263
2006-02-17 19:54:08 +00:00
57b3567552
Don't expand sdiv by power of two before legalize, since it will likely
...
generate illegal nodes.
llvm-svn: 26261
2006-02-17 07:26:20 +00:00
07a2677e43
unbreak the build
...
llvm-svn: 26260
2006-02-17 07:09:27 +00:00
593bea73ba
Unbreak x86 be
...
llvm-svn: 26259
2006-02-17 07:01:52 +00:00
baddba41c7
Fix loops where the header has an exit, fixing a loop-unswitch crash on crafty
...
llvm-svn: 26258
2006-02-17 06:39:56 +00:00
5965bd19f8
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
...
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
llvm-svn: 26255
2006-02-17 05:43:56 +00:00
9ec392b2aa
Fix another miscompilation exposed by lencode, where we lowered i64->f32
...
conversions to __floatdidf instead of __floatdisf on targets that support
f32 but not i64 (e.g. sparc).
llvm-svn: 26254
2006-02-17 04:32:33 +00:00
67c21b6c46
add note about div by power of 2
...
llvm-svn: 26253
2006-02-17 04:20:13 +00:00
0d62ebd13f
Fix bug noticed by VC++.
...
llvm-svn: 26252
2006-02-17 02:12:18 +00:00
3920ce4d8d
Whoops, didn't mean to check this in yet.
...
llvm-svn: 26250
2006-02-17 00:56:19 +00:00
4a0dc0c8f6
Add a missing and useful pat frag
...
llvm-svn: 26249
2006-02-17 00:51:06 +00:00
6fd136239b
start of some new simplification code, not thoroughly tested, use at your own
...
risk :)
llvm-svn: 26248
2006-02-17 00:31:07 +00:00
b590d3a72b
Remind ourselves to revisit the "pxor vs. xorps/xorpd to clear XMM registers"
...
issue. Need to do more experiments.
llvm-svn: 26247
2006-02-17 00:04:28 +00:00
7e5496d5fe
Kill the x86 pattern isel. boom.
...
llvm-svn: 26246
2006-02-17 00:03:04 +00:00
db1dbbe8d6
Remove the entry about using movapd for SSE reg-reg moves.
...
llvm-svn: 26245
2006-02-17 00:00:58 +00:00
eb7b3380fd
pxor (for FLD0SS) encoding was missing the OpSize prefix.
...
llvm-svn: 26244
2006-02-16 23:59:30 +00:00
936cc9fe53
Remove the skeleton target, it doesn't produce useful code and there are
...
other small targets that do that can be learned from. They also have
the added advantage of being tested :)
llvm-svn: 26243
2006-02-16 23:14:50 +00:00
c3dcf5a4d7
Dumb bug. Code sees a memcpy from X+c so it increments src offset. But it
...
turns out not to point to a constant string but it forgot change the offset
back.
llvm-svn: 26242
2006-02-16 23:11:42 +00:00
24c461b51e
1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. This
...
proves to be worth 20% on Ptrdist/ks. Might be related to dependency
breaking support.
2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These
are used for FR32 / FR64 reg-to-reg copies.
3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to
spill / restore FsMOVAPSrr and FsMOVAPDrr.
llvm-svn: 26241
2006-02-16 22:45:17 +00:00
3f99628939
Use movaps / movapd to spill / restore V4F4 / V2F8 registers.
...
llvm-svn: 26240
2006-02-16 21:20:26 +00:00
8a77efe4f7
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
...
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.
llvm-svn: 26238
2006-02-16 21:11:51 +00:00
fa335f6083
Change SplitBlock to increment a BasicBlock::iterator, not an Instruction*. Apparently they do different things :)
...
This fixes a testcase that nate reduced from spass.
Also included are a couple minor code changes that don't affect the generated
code at all.
llvm-svn: 26235
2006-02-16 19:36:22 +00:00
01afec2adb
MOVAPSrr and MOVAPDrr instruction format should be MRMSrcReg.
...
llvm-svn: 26234
2006-02-16 19:34:41 +00:00
36a2ee299e
distinguish between objects and register names, now we can have stuff
...
with names like "f84", "in6" etc etc.
this should fix one or two tests
llvm-svn: 26232
2006-02-16 13:12:57 +00:00
42c01c8d39
If the false case is the current basic block, then this is a self loop.
...
We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra
instruction in the loop. Instead, invert the condition and emit
"Loop: ... br!cond Loop; br Out.
Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering.
llvm-svn: 26231
2006-02-16 08:27:56 +00:00
471627c49d
Lowering of sdiv X, pow2 was broken, this fixes it. This patch is written
...
by Nate, I'm just committing it for him.
llvm-svn: 26230
2006-02-16 08:02:36 +00:00
55f63f1b53
Fix VC++ warning.
...
llvm-svn: 26228
2006-02-16 04:07:37 +00:00
ae82498e81
Use movaps / movapd (instead of movss / movsd) to do FR32 / FR64 reg to reg
...
transfer.
According to the Intel P4 Optimization Manual:
Moves that write a portion of a register can introduce unwanted
dependences. The movsd reg, reg instruction writes only the bottom
64 bits of a register, not to all 128 bits. This introduces a dependence on
the preceding instruction that produces the upper 64 bits (even if those
bits are not longer wanted). The dependence inhibits register renaming,
and thereby reduces parallelism.
Not to mention movaps is shorter than movss.
llvm-svn: 26226
2006-02-16 01:50:02 +00:00
ff42e81028
fix a bug where we unswitched the wrong way
...
llvm-svn: 26225
2006-02-16 01:24:41 +00:00
03c1e6f48e
A bit more memset / memcpy optimization.
...
Turns them into calls to memset / memcpy if 1) buffer(s) are not DWORD aligned,
2) size is not known to be greater or equal to some minimum value (currently 128).
llvm-svn: 26224
2006-02-16 00:21:07 +00:00
fdff0bb43e
Implement trivial unswitching for switch stmts. This allows us to trivial
...
unswitch this loop on 2 before sweating to unswitch on 1/3.
void test4(int N, int i, int C, int*P, int*Q) {
int j;
for (j = 0; j < N; ++j) {
switch (C) { // general unswitching.
default: P[i+j] = 0; break;
case 1: Q[i+j] = 0; break;
case 3: P[i+j] = Q[i+j]; break;
case 2: break; // TRIVIAL UNSWITCH on C==2
}
}
}
llvm-svn: 26223
2006-02-15 22:52:05 +00:00
76a7775ce1
Remove an entry.
...
llvm-svn: 26222
2006-02-15 22:14:34 +00:00
93e4865d4b
Remove an unused function parameter.
...
llvm-svn: 26221
2006-02-15 22:12:35 +00:00
e5cb76d744
make "trivial" unswitching significantly more general. It can now handle
...
this for example:
for (j = 0; j < N; ++j) { // trivial unswitch
if (C)
P[i+j] = 0;
}
turning it into the obvious code without bothering to duplicate an empty loop.
llvm-svn: 26220
2006-02-15 22:03:36 +00:00
6781b6e62e
Turn a memcpy from string constant into a series of stores of constant values.
...
llvm-svn: 26219
2006-02-15 21:59:04 +00:00
47da60130a
fix a bunch of alpha regressions. see bug 709
...
llvm-svn: 26218
2006-02-15 21:13:37 +00:00
6afb5587da
new test
...
llvm-svn: 26217
2006-02-15 19:52:06 +00:00
2eea436192
Should not combine ISD::LOCATIONs until we have scheme to remove from
...
MachineDebugInfo tables.
llvm-svn: 26216
2006-02-15 19:34:44 +00:00
65152d80ec
Checking the wrong value. This caused us to emit silly code like
...
Y = seteq bool X, true
instead of just using X :)
llvm-svn: 26215
2006-02-15 19:05:52 +00:00
f20e61f003
Convert this over to work with the new makefiles
...
llvm-svn: 26206
2006-02-15 07:22:58 +00:00
6db414e8de
Sparc actually *DOES* have a directive for emitting zeros. In fact, it requires
...
it, because this:
.bss
X:
.byte 0
results in the assembler warning: "initialization in bss segment". Annoying.
llvm-svn: 26204
2006-02-15 07:07:14 +00:00
7edc87279c
random lexer change to test the makefile updating stuff
...
llvm-svn: 26203
2006-02-15 07:02:59 +00:00
a9d0b5800a
Fix SingleSource/Regression/C/2004-08-12-InlinerAndAllocas.c on Sparc.
...
The ABI specifies that there is a register save area at the bottom of the
stack, which means the actual used pointer needs to be an offset from
the subtracted value.
llvm-svn: 26202
2006-02-15 06:41:34 +00:00
7a6c21ac26
Remove an entry.
...
llvm-svn: 26197
2006-02-15 01:56:48 +00:00
2d23c9f1ab
Use .zerofill on x86/darwin.
...
llvm-svn: 26196
2006-02-15 01:56:23 +00:00
e2038bdeee
Lower memcpy with small constant size operand into a series of load / store
...
ops.
llvm-svn: 26195
2006-02-15 01:54:51 +00:00
01db04efb0
more refactoring, no functionality change.
...
llvm-svn: 26194
2006-02-15 01:44:42 +00:00
aacc4c3b4c
cvtsd2ss / cvtss2sd encoding bug.
...
llvm-svn: 26193
2006-02-15 00:31:03 +00:00
665c26ab40
movaps, movapd encoding bug.
...
llvm-svn: 26192
2006-02-15 00:11:37 +00:00
b0cbe7106e
pull some code out into a function
...
llvm-svn: 26191
2006-02-15 00:07:43 +00:00
9c5693fb2a
Canonicalize inner loops before outer loops. Inner loop canonicalization
...
can provide work for the outer loop to canonicalize.
This fixes a case that breaks unswitching.
llvm-svn: 26189
2006-02-14 23:06:02 +00:00
0451499b3c
Doh again!
...
llvm-svn: 26188
2006-02-14 23:05:54 +00:00
cffbbee8d1
When splitting exit edges to canonicalize loops, make sure to put the new
...
block in the appropriate loop nest.
Third time is the charm, right?
llvm-svn: 26187
2006-02-14 22:34:08 +00:00
e3c793a71a
new note
...
llvm-svn: 26186
2006-02-14 22:19:54 +00:00
b134520b86
If we have zero initialized data with external linkage, use .zerofill to
...
emit it (instead of .space), saving a bit of space in the .o file.
For example:
int foo[100];
int bar[100] = {};
when compiled with C++ or -fno-common results in shrinkage from 1160 to 360
bytes of space. The X86 backend can also do this on darwin.
llvm-svn: 26185
2006-02-14 22:18:23 +00:00
ebb50a61d2
Using wrong DW_FORM.
...
llvm-svn: 26184
2006-02-14 22:01:57 +00:00
f84774ed46
Don't special case XS, XD prefixes.
...
llvm-svn: 26183
2006-02-14 21:52:51 +00:00
fb7b5ef74b
Bug fix: XS, XD prefixes were being emitted twice.
...
XMM registers were not being handled.
llvm-svn: 26182
2006-02-14 21:45:24 +00:00
84fb09eba4
Make sure that weak functions are aligned properly
...
llvm-svn: 26181
2006-02-14 20:42:33 +00:00
43b72f4421
Duh
...
llvm-svn: 26180
2006-02-14 20:37:37 +00:00
ad8c20cd2b
Remove -disable-x86-sse
...
llvm-svn: 26179
2006-02-14 20:30:14 +00:00
94f936d8ef
add an assert
...
llvm-svn: 26178
2006-02-14 20:14:17 +00:00
db2a7a736a
Keep to < 80 cols
...
llvm-svn: 26177
2006-02-14 20:12:38 +00:00
038521ef76
Missed a break so memcpy cases fell through to memset. Doh.
...
llvm-svn: 26176
2006-02-14 19:45:56 +00:00
d502610604
Fixed a build breakage.
...
llvm-svn: 26175
2006-02-14 09:11:59 +00:00
4b40a42653
Rename maxStoresPerMemSet to maxStoresPerMemset, etc.
...
llvm-svn: 26174
2006-02-14 08:38:30 +00:00
f976d79f78
Add a entry.
...
llvm-svn: 26173
2006-02-14 08:25:32 +00:00
6a37456d73
Set maxStoresPerMemSet to 16. Ditto for maxStoresPerMemCpy and
...
maxStoresPerMemMove. Although the last one is not used.
llvm-svn: 26172
2006-02-14 08:25:08 +00:00
81fcea8aa2
Expand memset dst, c, size to a series of stores if size falls below the
...
target specific theshold, e.g. 16 for x86.
llvm-svn: 26171
2006-02-14 08:22:34 +00:00
40b6eb9973
Enable SSE (for the right subtargets)
...
llvm-svn: 26169
2006-02-14 08:07:58 +00:00
1784a9d267
now that libcalls don't suck, we can remove this hack
...
llvm-svn: 26164
2006-02-14 05:39:35 +00:00
0242688ad8
adjust to new style of handling lexer changes
...
llvm-svn: 26162
2006-02-14 05:14:46 +00:00
0b8ec1a132
Use statistics to keep track of what flavors of loops we are unswitching
...
llvm-svn: 26157
2006-02-14 01:01:41 +00:00
8e2ee7358f
Fix a latent bug in the call sequence handling stuff. Some targets (e.g. x86)
...
create these nodes with flag results. Remember that we legalized them.
llvm-svn: 26156
2006-02-14 00:55:02 +00:00
8b10ab3002
Implement Instcombine/and.ll:test34
...
llvm-svn: 26155
2006-02-13 23:07:23 +00:00
7d8522884b
If any of the sign extended bits are demanded, the input sign bit is demanded
...
for a sign extension.
This fixes InstCombine/2006-02-13-DemandedMiscompile.ll and Ptrdist/bc.
llvm-svn: 26152
2006-02-13 22:41:07 +00:00
d2d174dd0e
Another hack due to allowing multiple symbols with the same name.
...
llvm-svn: 26150
2006-02-13 22:22:42 +00:00
eea0f0198e
Another work around for the 'symbols with different types can have the same
...
name' issue.
llvm-svn: 26149
2006-02-13 21:43:26 +00:00
a438ef0ee7
improved zap discovery
...
llvm-svn: 26148
2006-02-13 18:52:29 +00:00
390c63e9d9
Rename to better reflect usage (current and planned.)
...
llvm-svn: 26145
2006-02-13 12:50:39 +00:00
462505fc5f
Completely rewrite libcall insertion by the legalizer, providing the
...
following handy-dandy properties:
1. it is always correct now
2. it is much faster than before
3. it is easier to understand
This implementation builds off of the recent simplifications of the
legalizer that made it single-pass instead of iterative.
This fixes JM/lencod, JM/ldecod, and
CodeGen/Generic/2006-02-12-InsertLibcall.ll (at least on PPC).
llvm-svn: 26144
2006-02-13 09:18:02 +00:00
62c3484e43
Switch targets over to using SelectionDAG::getCALLSEQ_START to create
...
CALLSEQ_START nodes.
llvm-svn: 26143
2006-02-13 09:00:43 +00:00
3a0ad47b39
Switch to using getCALLSEQ_START instead of using our own creation calls
...
llvm-svn: 26142
2006-02-13 08:55:29 +00:00
68e7475777
Be careful not to request or look at bits shifted in from outside the size
...
of the input. This fixes the mediabench/gsm/toast failure last night.
llvm-svn: 26138
2006-02-13 06:09:08 +00:00
bc3ec1d37b
Add missing patterns for andi. and andis., fixing test/Regression/CodeGen/
...
PowerPC/and-imm.ll
llvm-svn: 26136
2006-02-12 09:09:52 +00:00
f5b4ef7f58
remove some more dead special case code
...
llvm-svn: 26135
2006-02-12 08:07:37 +00:00
5b2edb1fca
Eliminate special case hacks that are superceded by general purpose hacks
...
llvm-svn: 26134
2006-02-12 08:02:11 +00:00
ee0f280743
Three changes:
...
1. Teach GetConstantInType to handle boolean constants.
2. Teach instcombine to fold (compare X, CST) when X has known 0/1 bits.
Testcase here: set.ll:test22
3. Improve the "(X >> c1) & C2 == 0" folding code to allow a noop cast
between the shift and and. More aggressive bitfolding for other reasons
was turning signed shr's into unsigned shr's, leaving the noop cast in
the way.
llvm-svn: 26131
2006-02-12 02:07:56 +00:00
02f53ad3a2
Revert my last patch. It too breaks stuff
...
llvm-svn: 26128
2006-02-12 01:59:10 +00:00
35248e06bc
Fix for my previously reverted patch
...
llvm-svn: 26126
2006-02-11 21:24:54 +00:00
0157e7f55b
Port the recent innovations in ComputeMaskedBits to SimplifyDemandedBits.
...
This allows us to simplify on conditions where bits are not known, but they
are not demanded either! This also fixes a couple of bugs in
ComputeMaskedBits that were exposed during this work.
In the future, swaths of instcombine should be removed, as this code
subsumes a bunch of ad-hockery.
llvm-svn: 26122
2006-02-11 09:31:47 +00:00
b24ce3a2a8
revert my previous change, it exposed other problems.
...
llvm-svn: 26121
2006-02-11 08:47:47 +00:00
4698e4f5fe
fix storing booleans (grawp missed this one)
...
llvm-svn: 26120
2006-02-11 07:33:17 +00:00
0010a92375
now short immediates will get matched (previously constants were all
...
triggering movl 64bit imm fat instructions)
llvm-svn: 26119
2006-02-11 07:32:15 +00:00
05bf90dddf
Make this check stricter. Disallow loop exit blocks from being shared by
...
loops and their subloops.
llvm-svn: 26118
2006-02-11 02:13:17 +00:00
a86ba85dc5
Prevent certain nodes that have already been selected from being folded into
...
X86 addressing mode. Currently we do not allow any node whose target node
produces a chain as well as any node that is at the root of the addressing
mode expression tree.
llvm-svn: 26117
2006-02-11 02:05:36 +00:00
a6ae101afa
remove dead expr
...
llvm-svn: 26116
2006-02-11 01:43:37 +00:00
5995d0160c
Reorg for integration with gcc4. Old style debug info will not be passed though
...
to SelIDAG.
llvm-svn: 26115
2006-02-11 01:01:30 +00:00
fbadd7e1ee
implement unswitching of loops with switch stmts and selects in them
...
llvm-svn: 26114
2006-02-11 00:43:37 +00:00
f1b151684d
Update PHI nodes in successors of exit blocks.
...
llvm-svn: 26113
2006-02-10 23:26:14 +00:00
fe4151efe7
Reform the unswitching code in terms of edge splitting, not block splitting.
...
llvm-svn: 26112
2006-02-10 23:16:39 +00:00
2b6f78b664
Nicer code. :-)
...
llvm-svn: 26111
2006-02-10 22:46:26 +00:00
d49cc3634e
Added X86 isel debugging stuff.
...
llvm-svn: 26110
2006-02-10 22:24:32 +00:00
ec6b40a093
Fix a case where UnswitchTrivialCondition broke critical edges with
...
phi's in the successors
llvm-svn: 26108
2006-02-10 19:08:15 +00:00
fcb8a3aa76
Use the auto-generated call matcher. Remove a broken impl of the frameaddr/returnaddr
...
intrinsics.
Autogen frameindex matcher
llvm-svn: 26107
2006-02-10 07:35:42 +00:00
0c4dea4cb2
Update to new-style flags usage, simplifying the .td file
...
llvm-svn: 26106
2006-02-10 06:58:25 +00:00
907be3e24c
Remove a completed entry; add a new entry about fisttp op
...
llvm-svn: 26105
2006-02-10 05:48:15 +00:00
6e263155a6
add some notes, move some code around. Implement unswitching of loops
...
with branches on partially invariant computations.
llvm-svn: 26104
2006-02-10 02:30:37 +00:00
4935417a84
Move code around to be more logical, no functionality change.
...
llvm-svn: 26103
2006-02-10 02:01:22 +00:00
3fc3148b85
When unswitching a trivial loop, do admit we are doing it! :)
...
llvm-svn: 26102
2006-02-10 01:36:35 +00:00
ed7a67b0de
Implement unconditional unswitching of 'trivial' loops, those loops that contain
...
branches in their entry block that control whether or not the loop is a noop or not.
llvm-svn: 26101
2006-02-10 01:24:09 +00:00
4f0e66df6a
Simplify control flow a bit, note that unswitch preserves canonical loop form
...
llvm-svn: 26098
2006-02-09 22:15:42 +00:00
101e4b916a
Match tblgen change.
...
llvm-svn: 26096
2006-02-09 22:12:53 +00:00
a1ef3ec5b5
Added SelectionDAG::InsertISelMapEntry(). This is used to workaround the gcc
...
problem where it inline the map insertion call too aggressively. Before this
change it was producing a frame size of 24k for Select_store(), now it's down
to 10k (by calling this method rather than calling the map insertion operator).
llvm-svn: 26094
2006-02-09 22:11:03 +00:00
8976219850
Make the threshold a parameter
...
llvm-svn: 26093
2006-02-09 20:15:48 +00:00
4c0bd5bcdf
Done
...
llvm-svn: 26091
2006-02-09 20:00:19 +00:00
5259aa1c86
Enable LSR by default for SPARC: it is a clear win.
...
llvm-svn: 26090
2006-02-09 19:59:55 +00:00
2826e0511b
Simplify the loop-unswitch pass, by not even trying to unswitch loops with
...
uses of loop values outside the loop. We need loop-closed SSA form to do
this right, or to use SSA rewriting if we really care.
llvm-svn: 26089
2006-02-09 19:14:52 +00:00
24cd2fa269
Fix 80-column violations
...
llvm-svn: 26088
2006-02-09 07:41:14 +00:00
4534dd59a3
Enhance MVIZ in three ways:
...
1. Teach it new tricks: in particular how to propagate through signed shr and sexts.
2. Teach it to return a bitset of known-1 and known-0 bits, instead of just zero.
3. Teach instcombine (AND X, C) to fold when we know all C bits of X.
This implements Regression/Transforms/InstCombine/bittest.ll, and allows
future things to be simplified.
llvm-svn: 26087
2006-02-09 07:38:58 +00:00
d1b82d8db0
Match getTargetNode() changes (now return SDNode* instead of SDOperand).
...
llvm-svn: 26085
2006-02-09 07:17:49 +00:00
d3f1db93c1
More changes to reduce frame size.
...
Move all getTargetNode() out of SelectionDAG.h into SelectionDAG.cpp. This
prevents them from being inlined.
Change getTargetNode() so they return SDNode * instead of SDOperand to prevent
copying. It should also help compilation speed.
llvm-svn: 26083
2006-02-09 07:15:23 +00:00
c75d5b093d
add an option to turn on LSR.
...
llvm-svn: 26080
2006-02-09 05:06:36 +00:00
729ffe95c4
simplify this code now that each constant pool entry is not separately allocated
...
llvm-svn: 26079
2006-02-09 04:49:59 +00:00
f6190821da
Adjust to MachineConstantPool interface change: instead of keeping a
...
value/alignment pair for each constant, keep a value/offset pair.
llvm-svn: 26078
2006-02-09 04:46:04 +00:00
ba97264e72
rename fields of constant pool entries
...
llvm-svn: 26076
2006-02-09 04:22:52 +00:00
47f7319f00
Simplify code, alignment must be specified now.
...
llvm-svn: 26074
2006-02-09 02:26:04 +00:00
4576bb74d5
Make MachineConstantPool entries alignments explicit
...
llvm-svn: 26071
2006-02-09 02:23:13 +00:00
832d78d981
Always pass in an alignment.
...
llvm-svn: 26070
2006-02-09 02:19:16 +00:00
d94a3d2c8a
provide an explicit alignment for cp entries
...
llvm-svn: 26069
2006-02-09 02:15:30 +00:00
6dc90ca172
Change Select() from
...
SDOperand Select(SDOperand N);
to
void Select(SDOperand &Result, SDOperand N);
llvm-svn: 26067
2006-02-09 00:37:58 +00:00
2e07d6370a
Darwin doesn't support #APP/#NO_APP
...
llvm-svn: 26066
2006-02-08 23:42:22 +00:00
ed87dcd45f
Add support for assembler directives that wrap inline asm
...
llvm-svn: 26065
2006-02-08 23:41:56 +00:00
26e385a623
Rename BSel -> PPCBSel for the benefit of doxygen users.
...
Move the methods out of line.
Remove unused Debug.h stuff.
Teach getNumBytesForInstruction to know the size of an inline asm.
llvm-svn: 26064
2006-02-08 19:33:26 +00:00
b4fc050f0f
add a simple optimization
...
llvm-svn: 26062
2006-02-08 17:47:22 +00:00
ab2dc4d70d
Simplify some code, reducing calls to MaskedValueIsZero. Implement a minor
...
optimization where we reduce the number of bits in AND masks when possible.
llvm-svn: 26056
2006-02-08 07:34:50 +00:00
b7e074ab9b
more email -> README moving
...
llvm-svn: 26054
2006-02-08 07:12:07 +00:00
f7b962d7d7
Emit the 'mr' pseudoop for easier reading.
...
llvm-svn: 26053
2006-02-08 06:56:40 +00:00
45bb34b715
Add some random notes, not high-prio
...
llvm-svn: 26052
2006-02-08 06:52:06 +00:00
b97142eec0
Move emails from nate into public places
...
llvm-svn: 26051
2006-02-08 06:43:51 +00:00
5997cf9381
Use EraseInstFromFunction in a few cases to put the uses of the removed
...
instruction onto the worklist (in case they are now dead).
Add a really trivial local DSE implementation to help out bitfield code.
We now fold this:
struct S {
unsigned char a : 1, b : 1, c : 1, d : 2, e : 3;
S();
};
S::S() : a(0), b(0), c(1), d(0), e(6) {}
to this:
void %_ZN1SC1Ev(%struct.S* %this) {
entry:
%tmp.1 = getelementptr %struct.S* %this, int 0, uint 0
store ubyte 38, ubyte* %tmp.1
ret void
}
much earlier (in gccas instead of only in gccld after DSE runs).
llvm-svn: 26050
2006-02-08 03:25:32 +00:00
06a0ed1ee0
Implement some more interesting select sccp cases. This implements:
...
test/Regression/Transforms/SCCP/select.ll
llvm-svn: 26049
2006-02-08 02:38:11 +00:00
a10e23c19f
Compile this:
...
xori r6, r2, 1
rlwinm r6, r6, 0, 31, 31
cmpwi cr0, r6, 0
bne cr0, LBB1_3 ; endif
to this:
rlwinm r6, r2, 0, 31, 31
cmpwi cr0, r6, 0
beq cr0, LBB1_3 ; endif
llvm-svn: 26047
2006-02-08 02:13:15 +00:00
ddba3289b5
Fix a problem in my patch yesterday, causing a miscompilation of 176.gcc
...
llvm-svn: 26045
2006-02-08 01:20:23 +00:00
adeb8fb5a2
Fixed a local common symbol bug.
...
llvm-svn: 26044
2006-02-07 23:32:58 +00:00
ec212fb66d
For ELF, .comm takes alignment value as the optional 3rd argument. It must be
...
specified in bytes.
llvm-svn: 26043
2006-02-07 21:54:08 +00:00
203b2f1288
Implement getConstraintType for PPC.
...
llvm-svn: 26042
2006-02-07 20:16:30 +00:00
44314827d6
Fix Transforms/InstCombine/2006-02-07-SextZextCrash.ll
...
llvm-svn: 26040
2006-02-07 19:07:40 +00:00
5a76680de1
Darwin ABI issues: weak, linkonce, etc. dynamic-no-pic support is complete.
...
Also fixed a function stub bug. Added weak and linkonce support for
x86 Linux.
llvm-svn: 26038
2006-02-07 08:38:37 +00:00
227e469c25
Remind myself to add PIC and static asm printer support.
...
llvm-svn: 26037
2006-02-07 08:35:44 +00:00
92a6865321
Generalize MaskedValueIsZero into a ComputeMaskedNonZeroBits function, which
...
is just as efficient as MVIZ and is also more general.
Fix a few minor bugs introduced in recent patches
llvm-svn: 26036
2006-02-07 08:05:22 +00:00
c3ebf40031
Make MaskedValueIsZero take a uint64_t instead of a ConstantIntegral as a
...
mask. This allows the code to be simpler and more efficient.
Also, generalize some of the cases in MVIZ a bit, making it slightly more aggressive.
llvm-svn: 26035
2006-02-07 07:27:52 +00:00
77defbae0a
Use Type::getIntegralTypeMask() to simplify some code
...
llvm-svn: 26034
2006-02-07 07:00:41 +00:00
2590e511d8
Implement the beginnings of a facility for simplifying expressions based on
...
'demanded bits', inspired by Nate's work in the dag combiner. This isn't
complete, but needs to unrelated instcombiner changes to continue.
llvm-svn: 26033
2006-02-07 06:56:34 +00:00
2439669c6f
The interpreter assumes that the caller of runFunction() must be lli, and
...
therefore the function being called must be a main() returning an int. The
consequences when these assumptions are false are not good, so don't assume
them.
llvm-svn: 26031
2006-02-07 05:29:44 +00:00
69e849014c
Teach the interpreter to handle global variables that are added to a module after
...
interpretation has begun. The JIT already handles this situation correctly, and
the interpreter can already handle new functions being added.
llvm-svn: 26030
2006-02-07 05:11:57 +00:00
15a6c4c444
Add the simple PPC integer constraints
...
llvm-svn: 26027
2006-02-07 00:47:13 +00:00
d62a3bfa66
Eliminate the printCallOperand method, using a 'call' modifier on
...
printOperand instead.
llvm-svn: 26025
2006-02-06 23:41:19 +00:00
2bf2c8d7e7
Change prototype
...
llvm-svn: 26022
2006-02-06 22:18:19 +00:00
34f74c180a
Add support for modifier characters to operand printers
...
llvm-svn: 26021
2006-02-06 22:17:23 +00:00
0458fb76fd
Goodbye nasty macro.
...
llvm-svn: 26019
2006-02-06 21:54:05 +00:00
b643ff5546
Edit requests from Sabre.
...
llvm-svn: 26018
2006-02-06 19:12:02 +00:00
f5b7f16259
see what this allignment thing will do
...
llvm-svn: 26017
2006-02-06 17:15:17 +00:00
85263234a8
Changing model for the construction of debug information.
...
llvm-svn: 26016
2006-02-06 15:33:21 +00:00
58d48c8118
We seem to have settled to __DWARF for section name.
...
llvm-svn: 26015
2006-02-06 14:16:15 +00:00
d5f2ba0d6f
- Update load folding checks to match those auto-generated by tblgen.
...
- Manually select SDOperand's returned by TryFoldLoad which make up the
load address.
llvm-svn: 26012
2006-02-06 06:02:33 +00:00
bfa4b7cc75
Complex pattern isel code shouldn't select nodes.
...
llvm-svn: 26010
2006-02-05 08:45:01 +00:00
463fa70eaa
Fix the Sparc backend with Evan's recent tblgen changes
...
llvm-svn: 26009
2006-02-05 08:35:50 +00:00
8467e5d6af
This xform isn't safe
...
llvm-svn: 26007
2006-02-05 08:26:16 +00:00
8c9cd461df
Back out previous commit, it isn't safe.
...
llvm-svn: 26006
2006-02-05 08:23:00 +00:00
3dc8b89493
fold c1 << (x + c2) into (c1 << c2) << x. fix a warning.
...
llvm-svn: 26005
2006-02-05 08:07:24 +00:00
4b8fcc229f
some stuff is done
...
llvm-svn: 26004
2006-02-05 07:54:37 +00:00
2e90b732fa
Turn A % (C << N), where C is 2^k, into A & ((C << N)-1) [urem only].
...
Turn A / (C1 << N), where C1 is "1<<C2" into A >> (N+C2) [udiv only].
Tested with: rem.ll:test5, div.ll:test10
llvm-svn: 26003
2006-02-05 07:54:04 +00:00
c89fdf1eb3
Handle urem by shifted powers of 2.
...
llvm-svn: 26001
2006-02-05 07:36:48 +00:00
25d178bece
handle combining A / (B << N) into A >>u (log2(B)+N) when B is a power of 2
...
llvm-svn: 26000
2006-02-05 07:20:23 +00:00
a28b764886
Use SelectRoot() as the entry to any tblgen based isel.
...
llvm-svn: 25998
2006-02-05 06:51:51 +00:00
54cb1833a4
Use SelectRoot() as entry of any tblgen based isel.
...
llvm-svn: 25997
2006-02-05 06:46:41 +00:00
25777c8c25
Remove the SparcV8 backend. It has been renamed to be the Sparc backend.
...
llvm-svn: 25992
2006-02-05 06:33:29 +00:00
a3e5b2c61c
remove V8 reference
...
llvm-svn: 25991
2006-02-05 06:32:59 +00:00
d37645c07d
* Added SDNode::isOnlyUse().
...
* Fix hasNUsesOfValue(), it should be const.
llvm-svn: 25990
2006-02-05 06:29:23 +00:00
158e1f519c
Rename SPARC V8 target to be the LLVM SPARC target.
...
llvm-svn: 25985
2006-02-05 05:50:24 +00:00
c0e48c6c58
add a note
...
llvm-svn: 25984
2006-02-05 05:27:35 +00:00
d19d51f414
Re-commit the last bit of change that was backed out.
...
llvm-svn: 25983
2006-02-05 05:25:07 +00:00
cbab28414e
make sure that global doubles are aligned to 8 bytes
...
llvm-svn: 25981
2006-02-05 01:46:49 +00:00
c070cb685d
Use getPreferredAlignmentLog.
...
llvm-svn: 25980
2006-02-05 01:45:04 +00:00
1b1a8731c0
Use the asmprinter to find out what the preferred alignment of a global is.
...
This patch speeds up 172.mgrid from 31.81s to 11.39s on darwin/ppc.
Many many thanks to Nate for tracking down the root cause of the issue.
llvm-svn: 25979
2006-02-05 01:30:45 +00:00
a9b2525d3e
Implement the AsmPrinter::getPreferredAlignmentLog method.
...
llvm-svn: 25978
2006-02-05 01:29:18 +00:00
1fcff15f86
linkage fix for weak functions
...
llvm-svn: 25976
2006-02-04 19:13:09 +00:00
95ae171d5b
Fix VC++ warning.
...
llvm-svn: 25975
2006-02-04 16:20:31 +00:00
d30c4991a1
Use SCEVExpander::InsertCastOfTo instead of our own code. This reduces
...
#LLVM LOC, and auto-cse's cast instructions.
llvm-svn: 25974
2006-02-04 09:52:43 +00:00
a6da69cab0
Pull the InsertCastOfTo out of the header, implement CSE'ing of arguments.
...
llvm-svn: 25973
2006-02-04 09:51:53 +00:00
22b4edfb42
Temporarily revert this patch, which probably breaks with the
...
tblgen patch reverted.
llvm-svn: 25971
2006-02-04 09:24:16 +00:00
b6a1865bca
Value# select instructions, allowing -gcse to remove duplicates
...
llvm-svn: 25969
2006-02-04 09:15:29 +00:00
ce87cac555
Complex pattern's custom matcher should not call Select() on any operands.
...
Select them afterwards if it returns true.
llvm-svn: 25968
2006-02-04 08:50:49 +00:00
ab146eae38
Custom lower VAARG for the case when we are doing vaarg(double). In this
...
case, the double being loaded may not be 8-byte aligned, so we have to use
our standard bit_convert game.
llvm-svn: 25967
2006-02-04 08:31:30 +00:00
a1fa8b1c88
Fix a nasty typo that broke functions with big stack frames.
...
llvm-svn: 25966
2006-02-04 08:04:21 +00:00
d096b2f3e0
fix a bug in my last checkin
...
llvm-svn: 25965
2006-02-04 07:48:46 +00:00
2959f0003e
Fix two significant bugs in LSR:
...
1. When rewriting code in outer loops, sometimes we would insert code into
inner loops that is invariant in that loop.
2. Notice that 4*(2+x) is 8+4*x and use that to simplify expressions.
This is a performance neutral change.
llvm-svn: 25964
2006-02-04 07:36:50 +00:00
a1e895cf97
Remove some stuff that now works
...
llvm-svn: 25963
2006-02-04 07:29:35 +00:00
32ed2b45c7
add a note
...
llvm-svn: 25962
2006-02-04 07:07:31 +00:00
2c0956bcea
Two changes:
...
1. Treat FMOVD as a copy instruction, to help with coallescing in V9 mode
2. When in V9 mode, insert FMOVD instead of FpMOVD instructions, as we don't
ever rewrite FpMOVD instructions into FMOVS instructions, thus we just end
up with commented out copies!
This should fix a bunch of failures in V9 mode on sparc.
llvm-svn: 25961
2006-02-04 06:58:46 +00:00
f9adce90bf
Get rid of some memory leaks identified by Valgrind
...
llvm-svn: 25960
2006-02-04 06:49:00 +00:00
2d2e2e3c0e
Let bugpoint work on sparc with v9 instructions enabled.
...
llvm-svn: 25958
2006-02-04 05:02:27 +00:00
57a004abfe
Fix VC++ warning.
...
llvm-svn: 25957
2006-02-04 03:27:39 +00:00
3b48431333
Add initial support for immediates. This allows us to compile this:
...
int %rlwnm(int %A, int %B) {
%C = call int asm "rlwnm $0, $1, $2, $3, $4", "=r,r,r,n,n"(int %A, int %B, int 4, int 17)
ret int %C
}
into:
_rlwnm:
or r2, r3, r3
or r3, r4, r4
rlwnm r2, r2, r3, 4, 17 ;; note the immediates :)
or r3, r2, r2
blr
llvm-svn: 25955
2006-02-04 02:26:14 +00:00
0a977c95aa
Remove an unnecessary predicate.
...
llvm-svn: 25954
2006-02-04 02:23:01 +00:00
11613a5219
Separate FILD and FILD_FLAG, the later is only used for SSE2. It produces a
...
flag so it can be flagged to a FST.
llvm-svn: 25953
2006-02-04 02:20:30 +00:00
65ad53feb3
Initial early support for non-register operands, like immediates
...
llvm-svn: 25952
2006-02-04 02:16:44 +00:00
ee1dadbccf
implementation of some methods for inlineasm
...
llvm-svn: 25951
2006-02-04 02:13:02 +00:00
c93403a7fb
Handle another case exposed on X86.
...
llvm-svn: 25949
2006-02-03 23:50:46 +00:00
71d20c4e18
Fix a nasty problem on two-address machines in the following situation:
...
store EAX -> [ss#0]
[ss#0] += 1
...
use(EAX)
In this case, it is not valid to rewrite this as:
store EAX -> [ss#0]
EAX += 1
store EAX -> [ss#0] ;;; this would also delete the store above
...
use(EAX)
... because EAX is not a dead at that point. Keep track of which registers
we are allowed to clobber, and which ones we aren't, and don't clobber the
ones we're not supposed to. :)
This should resolve the issues on X86 last night.
llvm-svn: 25948
2006-02-03 23:28:46 +00:00
507a3a7bd1
significantly simplify the VirtRegMap code by pulling the SpillSlotsAvailable
...
and PhysRegsAvailable maps out into a new AvailableSpills struct. No
functionality change.
This paves the way for a bugfix, coming up next.
llvm-svn: 25947
2006-02-03 23:13:58 +00:00
20a894282d
Implement some feedback from sabre
...
llvm-svn: 25946
2006-02-03 22:38:07 +00:00
dc7bba9ffe
Add a framework for eliminating instructions that produces undemanded bits.
...
llvm-svn: 25945
2006-02-03 22:24:05 +00:00
81e66abd1e
add a note
...
llvm-svn: 25944
2006-02-03 22:06:45 +00:00
d079dbb9b0
another case Nate came up with
...
llvm-svn: 25943
2006-02-03 22:05:41 +00:00
277462e20f
add a note
...
llvm-svn: 25942
2006-02-03 21:25:23 +00:00
f68fd20286
remove some #ifdef'd out code, which should properly be in the dag combiner anyway.
...
llvm-svn: 25941
2006-02-03 20:13:59 +00:00
a1d312c6ea
remove an old comment
...
llvm-svn: 25940
2006-02-03 18:59:39 +00:00
23d55f2547
Remove the X86PeepholeOptimizerPass, a truly horrible old hack that is now
...
obsolete. yaay :)
llvm-svn: 25939
2006-02-03 18:54:24 +00:00
c408558638
When rewriting frame instructions, emit the appropriate small-immediate
...
instruction when possible.
llvm-svn: 25938
2006-02-03 18:20:04 +00:00
ca76917388
Teach sparc to fold loads/stores into copies.
...
Remove the dead getRegClassForType method
minor formating changes.
llvm-svn: 25936
2006-02-03 07:06:25 +00:00
6091407783
remove dead fn
...
llvm-svn: 25935
2006-02-03 06:51:34 +00:00
22e251abf1
Add common code for reassociating ops in the dag combiner
...
llvm-svn: 25934
2006-02-03 06:46:56 +00:00
d7d98611ca
Implement isLoadFromStackSlot and isStoreToStackSlot
...
llvm-svn: 25932
2006-02-03 06:44:54 +00:00
a23b04acdb
remove some target-indep and implemented notes
...
llvm-svn: 25930
2006-02-03 06:22:11 +00:00
d1aaee03ce
target independent notes
...
llvm-svn: 25929
2006-02-03 06:21:43 +00:00
fc567d85d5
Flesh out a couple of the items in the README
...
llvm-svn: 25928
2006-02-03 05:17:06 +00:00
3276ff7ac6
Fix VC++ compilation error caused by using a std::map iterator variable to receive
...
a std::multimap iterator value. For some reason, GCC doesn't have a problem with this.
llvm-svn: 25927
2006-02-03 03:48:54 +00:00
e18ef0d4a6
Remove move copies and dead stuff by not clobbering the result reg of a noop copy.
...
llvm-svn: 25926
2006-02-03 03:16:14 +00:00
1318240fd0
isStoreToStackSlot
...
llvm-svn: 25925
2006-02-03 03:07:37 +00:00
774d4a190b
Simplify some code
...
llvm-svn: 25924
2006-02-03 03:06:49 +00:00
a1eac9b978
the X86 backend no longer needs to delete its own noop copies
...
llvm-svn: 25923
2006-02-03 02:59:58 +00:00
1ef239afb4
Add code that checks for noop copies, which triggers when either:
...
1. a target doesn't know how to fold load/stores into copies, or
2. the spiller rewrites the input to a copy to the same register as the dest
instead of to the reloaded reg.
This will be moved/improved in the near future, but allows elimination of
some ancient x86 hacks. This eliminates 92 copies from SMG2000 on X86 and
163 copies from 252.eon.
llvm-svn: 25922
2006-02-03 02:02:59 +00:00
f0a2d66d1c
Add a note
...
llvm-svn: 25921
2006-02-03 01:49:49 +00:00
02b5b9cdd6
Added case HANDLENODE to getOperationName().
...
llvm-svn: 25920
2006-02-03 01:33:01 +00:00
b7f24de4c8
Physregs may hold multiple stack slot values at the same time. Keep track
...
of this, and use it to our advantage (bwahahah). This allows us to eliminate another
60 instructions from smg2000 on PPC (probably significantly more on X86). A common
old-new diff looks like this:
stw r2, 3304(r1)
- lwz r2, 3192(r1)
stw r2, 3300(r1)
- lwz r2, 3192(r1)
stw r2, 3296(r1)
- lwz r2, 3192(r1)
stw r2, 3200(r1)
- lwz r2, 3192(r1)
stw r2, 3196(r1)
- lwz r2, 3192(r1)
+ or r2, r2, r2
stw r2, 3188(r1)
and
- lwz r31, 604(r1)
- lwz r13, 604(r1)
- lwz r14, 604(r1)
- lwz r15, 604(r1)
- lwz r16, 604(r1)
- lwz r30, 604(r1)
+ or r31, r30, r30
+ or r13, r30, r30
+ or r14, r30, r30
+ or r15, r30, r30
+ or r16, r30, r30
+ or r30, r30, r30
Removal of the R = R copies is coming next...
llvm-svn: 25919
2006-02-03 00:36:31 +00:00
9b178ce225
update a note
...
llvm-svn: 25918
2006-02-02 23:50:22 +00:00
f3aef1b004
Fix a deficiency in the spiller that Evan noticed. In particular, consider
...
this code:
store [stack slot #0 ], R10
= add R14, [stack slot #0 ]
The spiller didn't know that the store made the value of [stackslot#0] available
in R10 *IF* the store came from a copy instruction with the store folded into it.
This patch teaches VirtRegMap to look at these stores and recognize the values
they make available. In one case Evan provided, this code:
divsd %XMM0, %XMM1
movsd %XMM1, QWORD PTR [%ESP + 40]
1) movsd QWORD PTR [%ESP + 48], %XMM1
2) movsd %XMM1, QWORD PTR [%ESP + 48]
addsd %XMM1, %XMM0
3) movsd QWORD PTR [%ESP + 48], %XMM1
movsd QWORD PTR [%ESP + 4], %XMM0
turns into:
divsd %XMM0, %XMM1
movsd %XMM1, QWORD PTR [%ESP + 40]
addsd %XMM1, %XMM0
3) movsd QWORD PTR [%ESP + 48], %XMM1
movsd QWORD PTR [%ESP + 4], %XMM0
In this case, instruction #2 was removed because of the value made
available by #1 , and inst #1 was later deleted because it is now
never used before the stack slot is redefined by #3 .
This occurs here and there in a lot of code with high spilling, on PPC
most of the removed loads/stores are LSU-reject-causing loads, which is
nice.
On X86, things are much better (because it spills more), where we nuke
about 1% of the instructions from SMG2000 and several hundred from eon.
More improvements to come...
llvm-svn: 25917
2006-02-02 23:29:36 +00:00
4efb328926
add 64b gpr store to the possible list of isStoreToStackSlot opcodes.
...
llvm-svn: 25916
2006-02-02 21:07:50 +00:00
5123346708
fix operand numbers
...
llvm-svn: 25915
2006-02-02 20:38:12 +00:00
c327d71e06
implement isStoreToStackSlot for PPC
...
llvm-svn: 25914
2006-02-02 20:16:12 +00:00
bb53acd03c
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :)
...
llvm-svn: 25913
2006-02-02 20:12:32 +00:00
246ee44c8f
implement isStoreToStackSlot
...
llvm-svn: 25911
2006-02-02 20:00:41 +00:00
0acc90c67e
add a method
...
llvm-svn: 25910
2006-02-02 19:57:16 +00:00
d8208c3665
more notes
...
llvm-svn: 25908
2006-02-02 19:43:28 +00:00
d3f033e8e0
add a note, I have no idea how important this is.
...
llvm-svn: 25907
2006-02-02 19:16:34 +00:00
e10e1024bc
%fcc is not an alias for %fcc0
...
llvm-svn: 25906
2006-02-02 08:02:20 +00:00
cb34968d19
correct an opcode
...
llvm-svn: 25905
2006-02-02 07:56:15 +00:00
9dd7df7ee7
new example
...
llvm-svn: 25903
2006-02-02 07:37:11 +00:00
cd018525f8
Update the README
...
llvm-svn: 25902
2006-02-02 07:27:56 +00:00
49beaf40fc
Turn any_extend nodes into zero_extend nodes when it allows us to remove an
...
and instruction. This allows us to compile stuff like this:
bool %X(int %X) {
%Y = add int %X, 14
%Z = setne int %Y, 12345
ret bool %Z
}
to this:
_X:
cmpl $12331, 4(%esp)
setne %al
movzbl %al, %eax
ret
instead of this:
_X:
cmpl $12331, 4(%esp)
setne %al
movzbl %al, %eax
andl $1, %eax
ret
This occurs quite a bit with the X86 backend. For example, 25 times in
lambda, 30 times in 177.mesa, 14 times in galgel, 70 times in fma3d,
25 times in vpr, several hundred times in gcc, ~45 times in crafty,
~60 times in parser, ~140 times in eon, 110 times in perlbmk, 55 on gap,
16 times on bzip2, 14 times on twolf, and 1-2 times in many other SPEC2K
programs.
llvm-svn: 25901
2006-02-02 07:17:31 +00:00
e0c60d63b1
Implement MaskedValueIsZero for ANY_EXTEND nodes
...
llvm-svn: 25900
2006-02-02 06:43:15 +00:00
4b2ec8af23
implemented, testcase here: test/Regression/CodeGen/X86/compare-add.ll
...
llvm-svn: 25899
2006-02-02 06:36:48 +00:00
49ce35542f
add two dag combines:
...
(C1-X) == C2 --> X == C1-C2
(X+C1) == C2 --> X == C2-C1
This allows us to compile this:
bool %X(int %X) {
%Y = add int %X, 14
%Z = setne int %Y, 12345
ret bool %Z
}
into this:
_X:
cmpl $12331, 4(%esp)
setne %al
movzbl %al, %eax
andl $1, %eax
ret
not this:
_X:
movl $14, %eax
addl 4(%esp), %eax
cmpl $12345, %eax
setne %al
movzbl %al, %eax
andl $1, %eax
ret
Testcase here: Regression/CodeGen/X86/compare-add.ll
nukage of the and coming up next.
llvm-svn: 25898
2006-02-02 06:36:13 +00:00
d3908f79cb
Update.
...
llvm-svn: 25896
2006-02-02 02:40:17 +00:00
0bd74558ae
make -debug output less newliney
...
llvm-svn: 25895
2006-02-02 00:38:08 +00:00
d8fba3a1ee
Fix a erroneous comment.
...
llvm-svn: 25894
2006-02-02 00:28:23 +00:00
7f5880b1c7
Implement matching constraints. We can now say things like this:
...
%C = call int asm "xyz $0, $1, $2, $3", "=r,r,r,0"(int %A, int %B, int 4)
and get:
xyz r2, r3, r4, r2
note that the r2's are pinned together. Yaay for 2-address instructions.
2342 ----------------------------------------------------------------------
llvm-svn: 25893
2006-02-02 00:25:23 +00:00
2f34a9e332
validate matching constraints and remember when we see them.
...
llvm-svn: 25892
2006-02-02 00:23:53 +00:00
6132a87cf4
more notes
...
llvm-svn: 25890
2006-02-01 23:38:08 +00:00
b3ea2677a4
Tell codegen MOVAPSrr and MOVAPDrr are copies.
...
llvm-svn: 25889
2006-02-01 23:03:16 +00:00
f1ed826c2a
Added SSE entries to foldMemoryOperand().
...
llvm-svn: 25888
2006-02-01 23:02:25 +00:00
8b40cde148
Rearrange code to my liking. :)
...
llvm-svn: 25887
2006-02-01 23:01:57 +00:00
aa23fa9f43
Implement smart printing of inline asm strings, handling variants and
...
substituted operands. For this testcase:
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
we now emit:
_test:
or r2, r3, r3
or r3, r4, r4
xyz r2, r2, r3 ;; look here
or r3, r2, r2
blr
... note the substituted operands. :)
llvm-svn: 25886
2006-02-01 22:41:11 +00:00
f7f056751c
add a method
...
llvm-svn: 25884
2006-02-01 22:38:46 +00:00
2f7650f9dc
another note
...
llvm-svn: 25883
2006-02-01 21:44:48 +00:00
4b1c726fbb
Add immediate forms of cmov and remove some cruft
...
llvm-svn: 25882
2006-02-01 19:37:33 +00:00
01bd9d9911
*** empty log message ***
...
llvm-svn: 25879
2006-02-01 19:05:15 +00:00
1558fc64f9
Implement simple register assignment for inline asms. This allows us to compile:
...
int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
llvm-svn: 25878
2006-02-01 18:59:47 +00:00
ba56b5dc35
Finegrainify namespacification
...
llvm-svn: 25877
2006-02-01 18:10:56 +00:00
a983beab37
add a note
...
llvm-svn: 25876
2006-02-01 17:54:23 +00:00
7e7f439f85
Fix some of the stuff in the PPC README file, and clean up legalization
...
of the SELECT_CC, BR_CC, and BRTWOWAY_CC nodes.
llvm-svn: 25875
2006-02-01 07:19:44 +00:00
3da1bb520e
add a note, I'll take care of this after nate commits his big patch
...
llvm-svn: 25873
2006-02-01 06:40:32 +00:00
9e350cd6ad
- Use xor to clear integer registers (set R, 0).
...
- Added a new format for instructions where the source register is implied
and it is same as the destination register. Used for pseudo instructions
that clear the destination register.
llvm-svn: 25872
2006-02-01 06:13:50 +00:00
c404b5748c
Remove another entry.
...
llvm-svn: 25871
2006-02-01 06:08:48 +00:00
b24b66f209
Fix VC++ compilation error.
...
llvm-svn: 25869
2006-02-01 04:37:04 +00:00
b0a76b0981
Another regression from the pattern isel
...
llvm-svn: 25867
2006-02-01 01:44:25 +00:00
7ed3101d14
Beef up the interface to inline asm constraint parsing, making it more general, useful, and easier to use.
...
llvm-svn: 25866
2006-02-01 01:29:47 +00:00
3a5ed55187
adjust to changes in InlineAsm interface. Fix a few minor bugs.
...
llvm-svn: 25865
2006-02-01 01:28:23 +00:00
a24617f5d4
Return's chain should be matching either the chain produced by the
...
value or the chain going into the load.
llvm-svn: 25863
2006-02-01 01:19:32 +00:00
a0527473ac
another testcase.
...
llvm-svn: 25862
2006-02-01 00:28:12 +00:00
e1ce4d7115
When folding a load into a return of SSE value, check the chain to
...
ensure the memory location has not been clobbered.
llvm-svn: 25861
2006-02-01 00:20:21 +00:00
bc1fcd074e
Remove an item. It's done.
...
llvm-svn: 25860
2006-02-01 00:15:53 +00:00
5659ca8f47
Be smarter about whether to store the SSE return value in memory. If
...
it is already available in memory, do a fld directly from there.
llvm-svn: 25859
2006-01-31 23:19:54 +00:00
64387c3e9c
turning these into 'adds' would require extra copies
...
llvm-svn: 25858
2006-01-31 22:59:46 +00:00
72d5c256c9
- Allow XMM load (for scalar use) to be folded into ANDP* and XORP*.
...
- Use XORP* to implement fneg.
llvm-svn: 25857
2006-01-31 22:28:30 +00:00
a91eb48547
Remove entries on fabs and fneg. These are done.
...
llvm-svn: 25856
2006-01-31 22:26:21 +00:00
32be2dc0af
Allow the specification of explicit alignments for constant pool entries.
...
llvm-svn: 25855
2006-01-31 22:23:14 +00:00
c642aa5e1c
* Fix 80-column violations
...
* Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'.
* Add inline asm constraint specification.
llvm-svn: 25854
2006-01-31 19:43:35 +00:00
0151361d21
add info about the inline asm register constraints for PPC
...
llvm-svn: 25853
2006-01-31 19:20:21 +00:00
2443ab932d
Allow custom lowering of fabs. I forgot to check in this change which
...
caused several test failures.
llvm-svn: 25852
2006-01-31 18:14:25 +00:00
0962ffc4a6
add a missing break that caused a lot of failures last night :(
...
llvm-svn: 25851
2006-01-31 17:20:06 +00:00
a162f208ee
Codegen
...
bool %test(int %X) {
%Y = seteq int %X, 13
ret bool %Y
}
as
_test:
addi r2, r3, -13
cntlzw r2, r2
srwi r3, r2, 5
blr
rather than
_test:
cmpwi cr7, r3, 13
mfcr r2
rlwinm r3, r2, 31, 31, 31
blr
This has very little effect on most code, but speeds up analyzer 23% and
mason 11%
llvm-svn: 25848
2006-01-31 08:17:29 +00:00
ac9892ccaf
okay, one more
...
llvm-svn: 25847
2006-01-31 07:45:45 +00:00
882611dc25
another note
...
llvm-svn: 25846
2006-01-31 07:45:08 +00:00
24b0742476
More notes
...
llvm-svn: 25845
2006-01-31 07:43:33 +00:00
57480d0634
another one
...
llvm-svn: 25844
2006-01-31 07:38:32 +00:00
17cd988419
add a note
...
llvm-svn: 25843
2006-01-31 07:37:20 +00:00
799716141b
add conditional moves of float and double values on int/fp condition codes.
...
llvm-svn: 25842
2006-01-31 07:26:55 +00:00
b0fe138b65
example nate pointed out
...
llvm-svn: 25841
2006-01-31 07:16:34 +00:00
6f9bf658a7
treat conditional branches the same way as conditional moves (giving them
...
an operand that contains the condcode), making things significantly simpler.
llvm-svn: 25840
2006-01-31 06:56:30 +00:00
21ec192419
compactify all of the integer conditional moves into one instruction that takes
...
a CC as an operand. Much smaller, much happier.
llvm-svn: 25839
2006-01-31 06:49:09 +00:00
196d58373c
Add immediate forms of integer cmovs
...
llvm-svn: 25838
2006-01-31 06:24:29 +00:00
283492b4fe
Shrinkify
...
llvm-svn: 25837
2006-01-31 06:18:16 +00:00
70c9e42593
Add the full complement of conditional moves of integer registers.
...
llvm-svn: 25834
2006-01-31 05:26:36 +00:00
b6493b3165
Compile this:
...
void %X(int %A) {
%C = setlt int %A, 123 ; <bool> [#uses=1]
br bool %C, label %T, label %F
T: ; preds = %0
call int %main( int 0 ) ; <int>:0 [#uses=0]
ret void
F: ; preds = %0
ret void
}
to this:
X:
save -96, %o6, %o6
subcc %i0, 122, %l0
bg .LBBX_2 ! F
nop
...
not this:
X:
save -96, %o6, %o6
sethi 0, %l0
or %g0, 1, %l1
subcc %i0, 122, %l2
bg .LBBX_4 !
nop
.LBBX_3: !
or %g0, %l0, %l1
.LBBX_4: !
subcc %l1, 0, %l0
bne .LBBX_2 ! F
nop
llvm-svn: 25833
2006-01-31 05:05:52 +00:00
e9721b2984
Only insert an AND when converting from BR_COND to BRCC if needed.
...
llvm-svn: 25832
2006-01-31 05:04:52 +00:00
2dd217b88f
Added custom lowering of fabs
...
llvm-svn: 25831
2006-01-31 03:14:29 +00:00
a9bfca8d1e
add the 'lucas' optimization
...
llvm-svn: 25830
2006-01-31 02:55:28 +00:00
0e70729e83
I don't see why this optimization isn't safe, but it isn't, so disable it
...
llvm-svn: 25829
2006-01-31 02:45:52 +00:00
d916e78b0a
Another high-prio selection performance bug
...
llvm-svn: 25828
2006-01-31 02:10:06 +00:00
2e56e89452
Handle physreg input/outputs. We now compile this:
...
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
llvm-svn: 25827
2006-01-31 02:03:41 +00:00
2b70a6f853
more mumbling
...
llvm-svn: 25826
2006-01-31 00:45:37 +00:00
b521361fb9
add some notes
...
llvm-svn: 25825
2006-01-31 00:20:38 +00:00
45df7f84ff
Don't generate complex sequence for SETOLE, SETOLT, SETULT, and SETUGT. Flip
...
the order of the compare operands and generate SETOGT, SETOGE, SETUGE, and
SETULE instead.
llvm-svn: 25824
2006-01-30 23:41:35 +00:00
57ecb561c6
Print the most trivial inline asms.
...
llvm-svn: 25822
2006-01-30 23:00:08 +00:00
f263a23735
Fix a bug in my legalizer reworking that caused the X86 backend to not get
...
a chance to custom legalize setcc, which broke a bunch of C++ Codes.
Testcase here: CodeGen/X86/2006-01-30-LongSetcc.ll
llvm-svn: 25821
2006-01-30 22:43:50 +00:00
9a90572374
Fix FP constants, and the SparcV8/2006-01-22-BitConvertLegalize.ll failure from last night
...
llvm-svn: 25819
2006-01-30 22:20:49 +00:00
08390f6a21
i64 -> f32, f32 -> i64 and some clean up.
...
llvm-svn: 25818
2006-01-30 22:13:22 +00:00
5b97fcf0f5
Always use FP stack instructions to perform i64 to f64 as well as f64 to i64
...
conversions. SSE does not have instructions to handle these tasks.
llvm-svn: 25817
2006-01-30 08:02:57 +00:00
37faeb2b02
Revamp the ICC/FCC reading instructions to be parameterized in terms of the
...
SPARC condition codes, not in terms of the DAG condcodes. This allows us to
write nice clean patterns for cmovs/branches.
llvm-svn: 25815
2006-01-30 07:43:04 +00:00
33a79cae7c
Compile:
...
uint %test(uint %X) {
%Y = call uint %llvm.ctpop.i32(uint %X)
ret uint %Y
}
to:
test:
save -96, %o6, %o6
sll %i0, 0, %l0
popc %l0, %i0
restore %g0, %g0, %g0
retl
nop
instead of to 40 logical ops. Note the shift-by-zero that clears the top
part of the 64-bit V9 register.
Testcase here: CodeGen/SparcV8/ctpop.ll
llvm-svn: 25814
2006-01-30 06:14:02 +00:00
321e337d95
If the target has V9 instructions, this pass is a noop, don't bother
...
running it.
llvm-svn: 25811
2006-01-30 05:51:14 +00:00
90d3fd9e7c
When in v9 mode, emit fabsd/fnegd/fmovd
...
llvm-svn: 25810
2006-01-30 05:48:37 +00:00
99dcb95e14
First step towards V9 instructions in the V8 backend, two conditional move
...
patterns. This allows emission of this code:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
move %icc, %i0, %i2
or %g0, %i2, %i0
restore %g0, %g0, %g0
retl
nop
instead of this:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
be .LBBt1_2 !
nop
.LBBt1_1: !
or %g0, %i2, %i0
.LBBt1_2: !
restore %g0, %g0, %g0
retl
nop
for this:
int %t1(int %a, int %b, int %c) {
%tmp.2 = seteq int %a, %b
%tmp3 = select bool %tmp.2, int %a, int %c
ret int %tmp3
}
llvm-svn: 25809
2006-01-30 05:35:57 +00:00
238fe93242
Two changes:
...
1. Default to having V9 instructions, instead of just V8.
2. unless -enable-sparc-v9-insts is passed, disable V9 (for use with llcbeta)
llvm-svn: 25807
2006-01-30 04:57:43 +00:00
af209b8b13
When lowering SELECT_CC, see if the input is a lowered SETCC. If so, fold
...
the two operations together. This allows us to compile this:
void %two(int %a, int* %b) {
%tmp.2 = seteq int %a, 0
%tmp.0.0 = select bool %tmp.2, int 10, int 20
store int %tmp.0.0, int* %b
ret void
}
into:
two:
save -96, %o6, %o6
or %g0, 20, %l0
or %g0, 10, %l1
subcc %i0, 0, %l2
be .LBBtwo_2 ! entry
nop
.LBBtwo_1: ! entry
or %g0, %l0, %l1
.LBBtwo_2: ! entry
st %l1, [%i1]
restore %g0, %g0, %g0
retl
nop
instead of:
two:
save -96, %o6, %o6
sethi 0, %l0
or %g0, 1, %l1
or %g0, 20, %l2
or %g0, 10, %l3
subcc %i0, 0, %l4
be .LBBtwo_2 ! entry
nop
.LBBtwo_1: ! entry
or %g0, %l0, %l1
.LBBtwo_2: ! entry
subcc %l1, 0, %l0
bne .LBBtwo_4 ! entry
nop
.LBBtwo_3: ! entry
or %g0, %l2, %l3
.LBBtwo_4: ! entry
st %l3, [%i1]
restore %g0, %g0, %g0
retl
nop
llvm-svn: 25806
2006-01-30 04:34:44 +00:00
baeb39c969
Add AddSymbol() method to DynamicLibrary to work around Windows limitation
...
of being unable to search for symbols in an EXE. It will also allow other
existing hacks to be improved.
llvm-svn: 25805
2006-01-30 04:33:51 +00:00
d6f5ae4455
don't insert an and node if it isn't needed here, this can prevent folding
...
of lowered target nodes.
llvm-svn: 25804
2006-01-30 04:22:28 +00:00
f0b24d2dc0
Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler.
...
llvm-svn: 25803
2006-01-30 04:09:27 +00:00
4ac0fa2aa5
Implement isMaskedValueZeroForTargetNode for the various v8 selectcc nodes,
...
allowing redundant and's to be eliminated by the dag combiner.
llvm-svn: 25800
2006-01-30 03:51:45 +00:00
3b40e64aa3
pass the address of MaskedValueIsZero into isMaskedValueZeroForTargetNode,
...
to permit recursion
llvm-svn: 25799
2006-01-30 03:49:37 +00:00
c6fa0282d2
adjust prototype
...
llvm-svn: 25798
2006-01-30 03:49:07 +00:00
8ee89c774b
Fix indentation.
...
llvm-svn: 25795
2006-01-29 22:02:52 +00:00
4d1ea71a31
Fix RET of promoted values on targets that custom expand RET to a target node.
...
llvm-svn: 25794
2006-01-29 21:02:23 +00:00
32058cfb7b
Functions that are lazily streamed in from the .bc file are *not* external.
...
This fixes llvm-test/SingleSource/UnitTests/2006-01-29-SimpleIndirectCall.c
and PR704
llvm-svn: 25793
2006-01-29 20:49:17 +00:00
3c6a950653
add another note
...
llvm-svn: 25789
2006-01-29 09:46:06 +00:00
dabee1f655
add some performance notes from looking at sgefa
...
llvm-svn: 25788
2006-01-29 09:42:20 +00:00
7c7cbde0e5
add a high-priority SSE issue from sgefa
...
llvm-svn: 25787
2006-01-29 09:14:47 +00:00
5a7a22c9dd
add a missed optimization
...
llvm-svn: 25786
2006-01-29 09:08:15 +00:00
2c748afd6c
cleanups to the ValueTypeActions interface
...
llvm-svn: 25785
2006-01-29 08:42:06 +00:00
3072af4d4f
Now that OpActions is big enough, we can specify actions for vector types
...
llvm-svn: 25784
2006-01-29 08:41:37 +00:00
8a4a3deaf9
clean up interface to ValueTypeActions
...
llvm-svn: 25783
2006-01-29 08:41:12 +00:00
ccb4476c87
Remove some special case hacks for CALLSEQ_*, using UpdateNodeOperands
...
instead.
llvm-svn: 25780
2006-01-29 07:58:15 +00:00
d7738e6b32
disable this for now
...
llvm-svn: 25778
2006-01-29 07:31:33 +00:00
0c05a2c99c
Add a note about lowering llvm.memset, llvm.memcpy, and llvm.memmove to a
...
few stores under certain conditions.
llvm-svn: 25777
2006-01-29 06:48:25 +00:00
35d20a4c00
remove now-dead code, the legalizer takes care of this for us
...
llvm-svn: 25776
2006-01-29 06:45:31 +00:00
132177e103
The FP stack doesn't support UNDEF, ask the legalizer to legalize it
...
instead of lying and saying we have it.
llvm-svn: 25775
2006-01-29 06:44:22 +00:00
2f292789dc
Allow custom expansion of ConstantVec nodes. PPC will use this in the future.
...
llvm-svn: 25774
2006-01-29 06:34:16 +00:00
d33c60b52b
Request expansion of ConstantVec nodes.
...
llvm-svn: 25773
2006-01-29 06:32:58 +00:00
758b0ac54b
Legalize ConstantFP into TargetConstantFP when the target allows. Implement
...
custom expansion of ConstantFP nodes.
llvm-svn: 25772
2006-01-29 06:26:56 +00:00
61c9a8e942
Targets all now request ConstantFP to be legalized into TargetConstantFP.
...
'fpimm' in .td files is now TargetConstantFP.
llvm-svn: 25771
2006-01-29 06:26:08 +00:00
b5f0ba6051
Update alpha to reflect recent constantfp legalize changes. It's not clear
...
why all this code isn't autogenerated. :(
llvm-svn: 25770
2006-01-29 06:25:22 +00:00
678da98835
eliminate uses of SelectionDAG::getBR2Way_CC
...
llvm-svn: 25767
2006-01-29 06:00:45 +00:00
1b09c6ba87
cmovle != cmovlt
...
llvm-svn: 25761
2006-01-29 03:47:30 +00:00
4ab39e43e8
Fix typo.
...
llvm-svn: 25760
2006-01-29 03:45:35 +00:00
8643ea67b1
Flesh out AMD family/models.
...
llvm-svn: 25755
2006-01-28 20:30:18 +00:00
58ca0be9af
Correctly determine CPU vendor.
...
llvm-svn: 25754
2006-01-28 19:48:34 +00:00
71287085a1
Use union instead of reinterpret_cast.
...
llvm-svn: 25751
2006-01-28 18:47:32 +00:00
b5de47cd9a
Fix recognition of Intel CPUs.
...
llvm-svn: 25750
2006-01-28 18:38:20 +00:00
b3ab2d3a42
Is64Bit reflects the capability of the chip, not an aspect of the target os
...
llvm-svn: 25749
2006-01-28 18:23:48 +00:00
be08957dc5
Fix a bunch of JIT failures with the new isel
...
llvm-svn: 25748
2006-01-28 18:19:37 +00:00
e128d5f724
Improve X86 subtarget support for Windows and AMD.
...
llvm-svn: 25747
2006-01-28 18:09:06 +00:00
d02b05473c
Use the new "UpdateNodeOperands" method to simplify LegalizeDAG and make it
...
faster. This cuts about 120 lines of code out of the legalizer (mostly code
checking to see if operands have changed).
It also fixes an ugly performance issue, where the legalizer cloned the entire
graph after any change. Now the "UpdateNodeOperands" method gives it a chance
to reuse nodes if the operands of a node change but not its opcode or valuetypes.
This speeds up instruction selection time on kimwitu++ by about 8.2% with a
release build.
llvm-svn: 25746
2006-01-28 10:58:55 +00:00
ccd2a20c4b
silence a warning
...
llvm-svn: 25745
2006-01-28 10:34:47 +00:00
580b12ad34
add another method variant
...
llvm-svn: 25744
2006-01-28 10:09:25 +00:00
f34156e8cb
add some methods for updating nodes
...
llvm-svn: 25742
2006-01-28 09:32:45 +00:00
eb63751499
minor tweaks
...
llvm-svn: 25740
2006-01-28 08:31:04 +00:00
689bdcc9cf
move a bunch of code, no other change.
...
llvm-svn: 25739
2006-01-28 08:25:58 +00:00
fcfda5a174
remove a couple more now-extraneous legalizeop's
...
llvm-svn: 25738
2006-01-28 08:22:56 +00:00
364b89a784
fix a bug
...
llvm-svn: 25737
2006-01-28 07:42:08 +00:00
9dcce6da8e
Several major changes:
...
1. Pull out the expand cases for BSWAP and CT* into a separate function,
reducing the size of LegalizeOp.
2. Fix a bug where expand(bswap i64) was wrong when i64 is legal.
3. Changed LegalizeOp/PromoteOp so that the legalizer never needs to be
iterative. It now operates in a single pass over the nodes.
4. Simplify a LOT of code, with a net reduction of ~280 lines.
llvm-svn: 25736
2006-01-28 07:39:30 +00:00
30432e07f0
Fix a bug in my elimination of ISD::CALL this morning. PPC now has to
...
provide the expansion for i64 calls itself
llvm-svn: 25735
2006-01-28 07:33:03 +00:00
dc8bbb6527
make this work on non-native hosts
...
llvm-svn: 25734
2006-01-28 06:05:41 +00:00
0c7b4666a3
add a note about how we should implement this FIXME from the legalizer:
...
// FIXME: revisit this when we have some kind of mechanism by which targets
// can decided legality of vector constants, of which there may be very
// many.
llvm-svn: 25733
2006-01-28 05:40:47 +00:00
fd4a7f76a9
Eliminate the need for ExpandOp to set 'needsanotheriteration', as it already
...
relegalizes the stuff it returns.
Add the ability to custom expand ADD/SUB, so that targets don't need to deal
with ADD_PARTS/SUB_PARTS if they don't want.
Fix some obscure potential bugs and simplify code.
llvm-svn: 25732
2006-01-28 05:07:51 +00:00
10f677508f
Instead of making callers of ExpandLibCall legalize the result, make
...
ExpandLibCall do it itself.
llvm-svn: 25731
2006-01-28 04:28:26 +00:00
a593acfe66
Eliminate the need to do another iteration of the legalizer after inserting
...
a libcall.
llvm-svn: 25730
2006-01-28 04:23:12 +00:00
98ed05c81d
remove method I just added
...
llvm-svn: 25728
2006-01-28 03:43:09 +00:00
43b867dd3b
add a new callback
...
llvm-svn: 25727
2006-01-28 03:37:03 +00:00
595ec734fc
Implement Promote for VAARG, and allow it to be custom promoted for people
...
who don't want the default behavior (Alpha).
llvm-svn: 25726
2006-01-28 03:14:31 +00:00
6c82262289
Add a couple more things to the readme.
...
llvm-svn: 25724
2006-01-28 01:22:10 +00:00
af397cec0b
Add a missing case to the dag combiner.
...
llvm-svn: 25723
2006-01-28 01:06:30 +00:00
fb16a62fba
Remove the ISD::CALL and ISD::TAILCALL nodes
...
llvm-svn: 25721
2006-01-28 00:18:58 +00:00
b292de6703
Remove some dead code
...
llvm-svn: 25719
2006-01-28 00:02:51 +00:00
2c00db82bd
Switch to AlphaISD::CALL instead of ISD::CALL
...
llvm-svn: 25718
2006-01-27 23:39:00 +00:00
f424a66524
Use PPCISD::CALL instead of ISD::CALL
...
llvm-svn: 25717
2006-01-27 23:34:02 +00:00
a9382ca59e
Use V8ISD::CALL instead of ISD::CALL
...
llvm-svn: 25716
2006-01-27 23:30:03 +00:00
18243826fd
A bit of wisdom from Chris on the last entry.
...
llvm-svn: 25715
2006-01-27 22:54:32 +00:00
63045d221b
AT&T assembly convention: registers are in lower case.
...
llvm-svn: 25714
2006-01-27 22:53:29 +00:00
a502b93fae
initialize member vars
...
llvm-svn: 25712
2006-01-27 22:38:36 +00:00
dbfc299915
initialize all instance vars
...
llvm-svn: 25711
2006-01-27 22:37:09 +00:00
4d967a4cbb
Make llvm.frame/returnaddr not crash on ppc
...
llvm-svn: 25710
2006-01-27 22:25:06 +00:00
9857d075b5
Added notes about a x86 isel deficiency.
...
llvm-svn: 25706
2006-01-27 22:11:01 +00:00
1073ae07b0
Added a temporary option -enable-x86-sse to enable sse support. It is used by
...
llc-beta.
llvm-svn: 25701
2006-01-27 21:49:34 +00:00
a814f0b31c
Bye bye Pattern ISel, hello DAG ISel.
...
llvm-svn: 25700
2006-01-27 21:26:54 +00:00
8c47c3a3b1
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
...
the same functionality. This addresses another piece of bug 680. Next,
on to fixing Alpha VAARG, which I broke last time.
llvm-svn: 25696
2006-01-27 21:09:22 +00:00
0cda006a69
Using bit size of integers instead of ambiguous "long" et all.
...
llvm-svn: 25694
2006-01-27 20:31:25 +00:00
afab7aa8f2
A better workaround
...
llvm-svn: 25692
2006-01-27 19:30:30 +00:00
4a84e97421
Sorry - really folowing convention.
...
llvm-svn: 25691
2006-01-27 18:32:41 +00:00
4be147f456
force sse/3dnow off until they work. This fixes all the x86 failures last night
...
llvm-svn: 25690
2006-01-27 18:30:50 +00:00
116bb15473
Following convention.
...
llvm-svn: 25689
2006-01-27 18:28:31 +00:00
ed2bb8562f
Unbreak the JIT with SSE
...
llvm-svn: 25688
2006-01-27 18:27:18 +00:00
fc3eca9023
fix build
...
llvm-svn: 25687
2006-01-27 18:16:17 +00:00
ecd7e61a1f
Fix build error that is apparently only a warning with some compilers.
...
llvm-svn: 25686
2006-01-27 17:31:30 +00:00
2b6efa9d41
Forgot the version number.
...
llvm-svn: 25685
2006-01-27 15:46:54 +00:00
f98fc8441c
Improve visibility/correctness of operand indices in "llvm.db" objects.
...
Handle 64 in DIEs.
llvm-svn: 25684
2006-01-27 15:20:54 +00:00
76a8d45e32
Fix auto-upgrade of intrinsics to work properly with both assembly and
...
bytecode reading. This code is crufty, the result of much hacking to get things
working correctly. Cleanup patches will follow.
llvm-svn: 25682
2006-01-27 11:49:27 +00:00
cde9e30bc6
x86 CPU detection and proper subtarget support
...
llvm-svn: 25679
2006-01-27 08:10:46 +00:00
d98701c639
Subtarget feature can now set any variable to any value
...
llvm-svn: 25678
2006-01-27 08:09:42 +00:00
061d9e2cf0
Stub out a method
...
llvm-svn: 25676
2006-01-27 02:10:10 +00:00
1240574609
PHI and INLINEASM are now built-in instructions provided by Target.td
...
llvm-svn: 25674
2006-01-27 01:46:15 +00:00
1c341ac1fe
Add a default NoItinerary class for targets to use.
...
llvm-svn: 25670
2006-01-27 01:41:38 +00:00
4df279cfda
Teach the scheduler to emit the appropriate INLINEASM MachineInstr for an
...
ISD::INLINEASM node.
llvm-svn: 25668
2006-01-26 23:28:04 +00:00
476e67be14
initial selectiondag support for new INLINEASM node. Note that inline asms
...
with outputs or inputs are not supported yet. :)
llvm-svn: 25664
2006-01-26 22:24:51 +00:00
0689dfad23
Use global information to fill out Dwarf compile units.
...
llvm-svn: 25662
2006-01-26 21:22:49 +00:00
15a8c15a1f
Improve compatibility with VC2005, patch by Morten Ofstad!
...
llvm-svn: 25661
2006-01-26 20:41:32 +00:00
32fef53f5c
Implement a method for inline asm support
...
llvm-svn: 25660
2006-01-26 20:37:03 +00:00
0bbdc55333
Set up MachineDebugInfo to scan for debug information form "llvm.db"g globals.
...
Global Variable information is now pulled from "llvm.dbg.globals"
llvm-svn: 25655
2006-01-26 20:21:46 +00:00
ebbfb386a5
Improve compatibility with VC2005, patch by Morten Ofstad!
...
llvm-svn: 25653
2006-01-26 19:55:20 +00:00
4558e4ae10
dynamically allocate plugin space as needed
...
llvm-svn: 25652
2006-01-26 19:38:58 +00:00
bb4c9c0bd7
Remember plugins should someone like bugpoint want to know them.
...
llvm-svn: 25649
2006-01-26 18:36:50 +00:00
54c13da29c
Added preliminary x86 subtarget support.
...
llvm-svn: 25645
2006-01-26 09:53:06 +00:00
0ebb0b1c5c
fix stack corruption! Previously, 16-byte whole-FP-register stores were
...
being treated as needing only 8 bytes (though they were 16 byte aligned.)
This should fix a bunch of tests - anyone have any comments, though?
- in Target.td , SpillSize and SpillAlignment seem dead - is this what
Size and Alignment do now?
- in CodeGenRegisters.h/CodeGenTarget.cpp , DeclaredSpillSize and
DeclaredSpillAlignment seem dead.
- there are a bunch of comments here and there that don't clearly
distinguish between 'size' and 'spillsize' etc. hmm.
llvm-svn: 25644
2006-01-26 09:45:03 +00:00
c090ac13bd
some hoovering
...
llvm-svn: 25643
2006-01-26 09:08:31 +00:00
dbc2aac1e7
Rest of subtarget support, remove references to ppc
...
llvm-svn: 25642
2006-01-26 07:22:22 +00:00
e6842a9da6
Add trivial subtarget support
...
llvm-svn: 25641
2006-01-26 06:51:21 +00:00
0a01374299
minor renaming
...
llvm-svn: 25640
2006-01-26 03:24:15 +00:00
153f808f53
allow R28 to be used for frame calculations without entirely removing it from circulation
...
llvm-svn: 25639
2006-01-26 03:22:07 +00:00
fcdce6d26f
Work around some x86 Darwin assembler bugs
...
llvm-svn: 25638
2006-01-26 02:27:43 +00:00
c981b8e35a
add method for constraint parsing
...
llvm-svn: 25637
2006-01-26 02:21:59 +00:00
944d1e91ea
When trying to fold X86::SETCC into a Select, make a copy if it has more than
...
one use. This allows more CMOV instructions.
llvm-svn: 25634
2006-01-26 02:13:10 +00:00
120f31b1fd
teach the cloner to handle inline asms
...
llvm-svn: 25633
2006-01-26 01:55:22 +00:00
8547e3ab16
parse and verify the constraint string.
...
llvm-svn: 25631
2006-01-26 00:48:33 +00:00
c4c339c3d0
Clean up some code; improve efficiency; and fixed a potential bug involving
...
chain successors.
llvm-svn: 25630
2006-01-26 00:30:29 +00:00
97c68f0f5c
Remove the uses of STATUS flag register. Rely on node property SDNPInFlag,
...
SDNPOutFlag, and SDNPOptInFlag instead.
llvm-svn: 25629
2006-01-26 00:29:36 +00:00
41eb5cd9c3
Make sure the only user of InlineAsm's are direct calls.
...
llvm-svn: 25626
2006-01-26 00:08:45 +00:00
5c3dd5fafd
oops
...
llvm-svn: 25623
2006-01-25 23:33:32 +00:00
4470691999
add bc reader/writer support for inline asm
...
llvm-svn: 25621
2006-01-25 23:08:15 +00:00
a852660e74
forgot one
...
llvm-svn: 25620
2006-01-25 22:28:07 +00:00
e0a4ee9db7
regenerate
...
llvm-svn: 25619
2006-01-25 22:27:16 +00:00
a02d603c18
Parse inline asm objects
...
llvm-svn: 25618
2006-01-25 22:26:43 +00:00
a2d810d935
Print InlineAsm objects
...
llvm-svn: 25617
2006-01-25 22:26:05 +00:00
93fd315292
make things compile again
...
llvm-svn: 25614
2006-01-25 21:54:38 +00:00
5edde66863
Don't break the optimized build (by incorrect placement of #endif)
...
llvm-svn: 25613
2006-01-25 21:49:13 +00:00
8bbcda2fda
Change inline asms to be uniqued like constants, not embedded in a Module.
...
llvm-svn: 25610
2006-01-25 18:57:27 +00:00
d07c86465d
initialize an instance var, apparently I forgot to commit this long ago
...
llvm-svn: 25609
2006-01-25 18:57:15 +00:00
1880f8db02
No need to keep track of top and bottom nodes in a group since the vector is
...
already in order. Thanks Jim for pointing it out.
llvm-svn: 25608
2006-01-25 18:54:24 +00:00
030e002fb9
Set SchedulingForLatency to be the default scheduling preference for all.
...
llvm-svn: 25607
2006-01-25 18:52:42 +00:00
e74795cd70
First part of bug 680:
...
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
llvm-svn: 25606
2006-01-25 18:21:52 +00:00
c3cafb8a67
Make it even more portable.
...
llvm-svn: 25605
2006-01-25 17:18:50 +00:00
fb20616aa6
Fix VC++ compilation error.
...
llvm-svn: 25604
2006-01-25 17:17:49 +00:00
1092a02619
Default scheduling preference is SchedulingForLatency.
...
llvm-svn: 25603
2006-01-25 09:15:54 +00:00
83eeefbbd1
X86 prefer scheduling for reduced register pressure.
...
llvm-svn: 25602
2006-01-25 09:15:17 +00:00
ab49556cf4
Bottom up register usage reducing list scheduler.
...
llvm-svn: 25601
2006-01-25 09:14:32 +00:00
fbc88a624a
Keep track of bottom / top element of a set of flagged nodes.
...
llvm-svn: 25600
2006-01-25 09:13:41 +00:00
a6eff8a432
If scheduler choice is the default (-sched=default), use target scheduling
...
preference to determine which scheduler to use. SchedulingForLatency ==
Breadth first; SchedulingForRegPressure == bottom up register reduction list
scheduler.
llvm-svn: 25599
2006-01-25 09:12:57 +00:00
aff0800fd1
Fix a selectcc lowering bug. Make a copy of X86ISD::CMP when folding it.
...
llvm-svn: 25596
2006-01-25 09:05:09 +00:00
bc7226a7cc
Loosen up these checks to allow direct uses of ESP
...
llvm-svn: 25595
2006-01-25 08:00:36 +00:00
a292744ecc
Portably cast a pointer to an integer.
...
llvm-svn: 25594
2006-01-25 02:40:10 +00:00
5ea06a9f13
add bundling! well not really, for now it's just stop-insertion.
...
llvm-svn: 25593
2006-01-25 02:23:38 +00:00
94150f0666
maintaining stackpointer alignment. Perhaps it doesn't matter
...
llvm-svn: 25592
2006-01-25 01:51:08 +00:00
1dbc389ad2
fix build on 64 bit hosts
...
llvm-svn: 25591
2006-01-24 21:26:43 +00:00
c0f633a598
Fix Regression/Transforms/ScalarRepl/2006-01-24-IllegalUnionPromoteCrash.ll
...
llvm-svn: 25587
2006-01-24 19:36:27 +00:00
27d30a5f42
use ESP directly, not a copy of ESP into some other register for fastcc calls
...
llvm-svn: 25584
2006-01-24 06:14:44 +00:00
f9a1e3aadc
Fix an infinite loop I caused by making sure to legalize the flag operand
...
of CALLSEQ_* nodes
llvm-svn: 25582
2006-01-24 05:48:21 +00:00
6f33eaeb81
Emit the copies out of call return registers *after* the ISD::CALLSEQ_END
...
node, fixing fastcc and the case where a function has a frame pointer due
to dynamic allocas.
llvm-svn: 25580
2006-01-24 05:17:12 +00:00
68e62a5184
Allow jit-beta to work
...
llvm-svn: 25578
2006-01-24 04:50:48 +00:00
12f8441c03
Fix VC++ compilation error.
...
llvm-svn: 25577
2006-01-24 04:43:17 +00:00
b56a80061a
Remove unused variables.
...
llvm-svn: 25576
2006-01-24 04:42:53 +00:00
00fcdfef0d
rename method
...
llvm-svn: 25572
2006-01-24 04:16:34 +00:00
8ebd2164eb
Rename method
...
llvm-svn: 25571
2006-01-24 04:14:29 +00:00
eef2fe72c0
Initial checkin of the InlineAsm class
...
llvm-svn: 25570
2006-01-24 04:13:11 +00:00
3e65f28ffe
Crude Dwarf global variable debugging.
...
llvm-svn: 25569
2006-01-24 00:49:18 +00:00
efaf35d52a
Pretty print file-scope asm blocks.
...
llvm-svn: 25568
2006-01-24 00:45:30 +00:00
3acaf5cb11
syntax change
...
llvm-svn: 25567
2006-01-24 00:40:17 +00:00
e3a79268a2
Print file-scope inline asm blocks at the start of the output file.
...
llvm-svn: 25565
2006-01-23 23:47:53 +00:00
bc7b2581cb
Add support for reading/writing inline asm
...
llvm-svn: 25564
2006-01-23 23:43:17 +00:00
dd2d3faf19
Add support for linking inline asm
...
llvm-svn: 25560
2006-01-23 23:08:37 +00:00
37992b34c2
When cloning a module, clone the inline asm.
...
llvm-svn: 25559
2006-01-23 23:06:28 +00:00
edd9b0389b
regenerate
...
llvm-svn: 25558
2006-01-23 23:05:42 +00:00
f09741f441
Add support for parsing global asm blocks
...
llvm-svn: 25557
2006-01-23 23:05:15 +00:00
6ed87bdeb4
Print out inline asm strings
...
llvm-svn: 25556
2006-01-23 23:03:36 +00:00
c0bf377f98
bye bye Pattern ISEL
...
llvm-svn: 25553
2006-01-23 21:56:07 +00:00
fef7dec9cc
added stores to lsmark
...
llvm-svn: 25552
2006-01-23 21:51:33 +00:00
683352382e
another couple selects
...
llvm-svn: 25551
2006-01-23 21:51:14 +00:00
208bbe9ca9
fix up more lsmark stuff
...
llvm-svn: 25550
2006-01-23 21:23:26 +00:00
ba97ea52d4
yea, lowering this stuff will basically work
...
llvm-svn: 25549
2006-01-23 20:59:50 +00:00
c28563874c
another selectto
...
llvm-svn: 25548
2006-01-23 20:59:12 +00:00
b8566fa10a
Typo.
...
llvm-svn: 25545
2006-01-23 13:34:04 +00:00
31272347d4
Skeleton of the list schedule.
...
llvm-svn: 25544
2006-01-23 08:26:10 +00:00
421cfe8006
Minor clean up.
...
llvm-svn: 25543
2006-01-23 08:25:34 +00:00
455d1217ea
Revert last patch because it messes up the JIT, amongst other things.
...
llvm-svn: 25541
2006-01-23 08:11:03 +00:00
281dcd6ace
For PR411:
...
No functionality changes, just improve the code by a) providing better
function names, b) eliminating a call to get_suffix and c) tightening up
a function elimination test to reduce further checking.
llvm-svn: 25540
2006-01-23 07:42:30 +00:00
95c05bf1b4
For PR411:
...
Don't try to be smart about fixing intrinsic functions when they're read
in, just fix them after the module is read when all names are resolved.
llvm-svn: 25539
2006-01-23 07:39:03 +00:00
763dfd7723
Fix Regression/CodeGen/SparcV8/2006-01-22-BitConvertLegalize.ll by making
...
sure that the result of expanding a BIT_CONVERT node is itself legalized.
llvm-svn: 25538
2006-01-23 07:30:46 +00:00
87063b9986
Remove a couple of unnecessary #include's
...
llvm-svn: 25535
2006-01-23 07:21:01 +00:00
8935e3eb7d
remove the V8 simple isel
...
llvm-svn: 25534
2006-01-23 07:20:15 +00:00
c1e1d9724d
Factor out more instruction scheduler code to the base class.
...
llvm-svn: 25532
2006-01-23 07:01:07 +00:00
5774040c09
add a bunch more optimizations for unary double math functions
...
llvm-svn: 25530
2006-01-23 06:24:46 +00:00
37c8ad14f4
die, die!! r15, you are not callee-saved
...
llvm-svn: 25527
2006-01-23 06:11:45 +00:00
cc87402925
fix register corruption! (my god.) r15 is a scratch reg, using that as
...
a frame pointer is a pretty doofus thing to do. use r5 instead, and
mark it callee-saved, coz that's what it is!
llvm-svn: 25526
2006-01-23 06:08:46 +00:00
57a2863cbb
Refactor/genericize this, no functionality change
...
llvm-svn: 25525
2006-01-23 05:57:36 +00:00
deda32a786
Fix bugs lowering stackrestore, fixing 2004-08-12-InlinerAndAllocas.c on
...
PPC.
llvm-svn: 25522
2006-01-23 05:22:07 +00:00
c66da83a89
Speedup and simplify pass registration by the observation that there is
...
exactly one PassInfo object per RegisterPass object and that their lifetimes
are the same. As such, there is no reason for the RegisterPass object to
dynamically allocate the PassInfo object at compiler startup time: just inline
the object by-value. This should reduce codesize, heap size, and startup time. Yaay.
llvm-svn: 25521
2006-01-23 01:01:04 +00:00
01a325ed68
Add #include of <iostream>
...
llvm-svn: 25516
2006-01-22 23:41:42 +00:00
de02d7727f
Add explicit #includes of <iostream>
...
llvm-svn: 25515
2006-01-22 23:41:00 +00:00
c597b8a55e
Make iostream #inclusion explicit
...
llvm-svn: 25514
2006-01-22 23:32:06 +00:00
6806c02380
Add explicit iostream #includes
...
llvm-svn: 25513
2006-01-22 23:19:18 +00:00
33081b4648
Make this more efficient in the following ways:
...
1. Do not statically construct a map when the program starts up, this
is expensive and cannot be optimized. Instead, create a list.
2. Do not insert entries for all function in the module into a hashmap
that lives the full life of the compiler.
llvm-svn: 25512
2006-01-22 23:10:26 +00:00
469640e506
Add explicit #includes of <iostream>
...
llvm-svn: 25509
2006-01-22 22:53:01 +00:00
0d4ebfc15b
Several non-functionality changing changes:
...
1. Use the varargs version of getOrInsertFunction to simplify code.
2. remove #include
3. Reduce the number of #ifdef's.
4. remove extraneous vertical whitespace.
llvm-svn: 25508
2006-01-22 22:35:08 +00:00
e23928c67f
Fix a bug in a recent refactor that caused a bunch of programs to miscompile
...
or the compiler to crash.
llvm-svn: 25503
2006-01-21 19:12:11 +00:00
4204e02fc6
insignificant, but next up is proper stack frame layout!
...
llvm-svn: 25497
2006-01-21 14:27:19 +00:00
44cab00045
Fix CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll
...
llvm-svn: 25496
2006-01-21 04:27:00 +00:00
468fecdc99
Rename fcmovae to fcmovnb and fcmova to fcmovnbe (following Intel manual).
...
Some assemblers can't recognize the aliases.
llvm-svn: 25494
2006-01-21 02:55:41 +00:00
739a6a456e
Do some code refactoring on Jim's scheduler in preparation of the new list
...
scheduler.
llvm-svn: 25493
2006-01-21 02:32:06 +00:00
9436aa74a9
trivial formatting improvement: don't insert extra blank lines between .comm
...
vars.
llvm-svn: 25492
2006-01-21 01:35:26 +00:00
Chris Lattner