b19a5c661b
Turn casts into getelementptr's when possible. This enables SROA to be more
...
aggressive in some cases where LLVMGCC 4 is inserting casts for no reason.
This implements InstCombine/cast.ll:test27/28.
llvm-svn: 27620
2006-04-12 18:09:35 +00:00
175d57c4bc
Don't emit useless warning messages.
...
llvm-svn: 27617
2006-04-12 17:56:16 +00:00
74cf9ff761
Rename get_VSPLI_elt -> get_VSPLTI_elt
...
Canonicalize BUILD_VECTOR's that match VSPLTI's into a single type for each
form, eliminating a bunch of Pat patterns in the .td file and allowing us to
CSE stuff more aggressively. This implements
PowerPC/buildvec_canonicalize.ll:VSPLTI
llvm-svn: 27614
2006-04-12 17:37:20 +00:00
e2157c6e41
Promote v4i32, v8i16, v16i8 load to v2i64 load.
...
llvm-svn: 27612
2006-04-12 17:12:36 +00:00
e318a7574e
Ensure that zero vectors are always v4i32, which forces them to CSE with
...
each other. This implements CodeGen/PowerPC/vxor-canonicalize.ll
llvm-svn: 27609
2006-04-12 16:53:28 +00:00
be8a8933e6
Vector type promotion for ISD::LOAD and ISD::SELECT
...
llvm-svn: 27606
2006-04-12 16:33:18 +00:00
d3b504ae10
Implement support for the formal_arguments node. To get this, targets shouldcustom legalize it and remove their XXXTargetLowering::LowerArguments overload
...
llvm-svn: 27604
2006-04-12 16:20:43 +00:00
29be057d92
Various SSE2 conversion intrinsics
...
llvm-svn: 27603
2006-04-12 05:20:24 +00:00
417b96b6dd
Don't memoize vloads in the load map! Don't memoize them anywhere here, let
...
getNode do it. This fixes CodeGen/Generic/2006-04-11-vecload.ll
llvm-svn: 27602
2006-04-12 03:25:41 +00:00
70c74a3ced
Added __builtin_ia32_storelv4si, __builtin_ia32_movqv4si,
...
__builtin_ia32_loadlv4si, __builtin_ia32_loaddqu, __builtin_ia32_storedqu.
llvm-svn: 27599
2006-04-11 22:28:25 +00:00
f19bcd5177
Fix SingleSource/UnitTests/Vector/sumarray-dbl
...
llvm-svn: 27594
2006-04-11 19:44:43 +00:00
1bb132099f
Fix PR727, correctly handling large stack aligments on ppc
...
llvm-svn: 27593
2006-04-11 19:29:21 +00:00
aaa04230bd
we have a shuffle instr, add an example.
...
llvm-svn: 27592
2006-04-11 18:47:03 +00:00
6b60357f4a
gcc lower SSE prefetch into generic prefetch intrinsic. Need to add support
...
later.
llvm-svn: 27591
2006-04-11 18:04:57 +00:00
6ea715af28
Misc. intrinsics.
...
llvm-svn: 27590
2006-04-11 17:35:57 +00:00
02b3b72bfc
Suppress debug label when not debug.
...
llvm-svn: 27588
2006-04-11 08:11:53 +00:00
09a956271a
movnt* and maskmovdqu intrinsics
...
llvm-svn: 27587
2006-04-11 06:57:30 +00:00
7256b0ae05
Only get Tmp2 for cases where number of operands is > 1. Fixed return void.
...
llvm-svn: 27586
2006-04-11 06:33:39 +00:00
6cf3bbbe17
add some todos
...
llvm-svn: 27580
2006-04-11 02:00:08 +00:00
e4db08a2f1
Vector function results go into V2 according to GCC. The darwin ABI doc
...
doesn't say where they go :-/
llvm-svn: 27579
2006-04-11 01:38:39 +00:00
2eb22eef7d
Add basic support for legalizing returns of vectors
...
llvm-svn: 27578
2006-04-11 01:31:51 +00:00
92533cfb4a
Move some return-handling code from lowerarguments to the ISD::RET handling stuff.
...
No functionality change.
llvm-svn: 27577
2006-04-11 01:21:43 +00:00
12ba3e23d0
Added support for _mm_move_ss and _mm_move_sd.
...
llvm-svn: 27575
2006-04-11 00:19:04 +00:00
dca2655daa
Use existing information.
...
llvm-svn: 27574
2006-04-10 23:09:19 +00:00
2d37f920ad
Implement vec_shuffle.ll:test3
...
llvm-svn: 27573
2006-04-10 23:06:36 +00:00
fbb77a408b
Implement InstCombine/vec_shuffle.ll:test[12]
...
llvm-svn: 27571
2006-04-10 22:45:52 +00:00
f8ac02283c
Remove some bogus patterns; clean up.
...
llvm-svn: 27569
2006-04-10 22:35:16 +00:00
d99f57c1e1
add a note
...
llvm-svn: 27567
2006-04-10 21:51:03 +00:00
051de9a82b
Remove an entry that is now done.
...
llvm-svn: 27565
2006-04-10 21:42:57 +00:00
76112c3cb8
Added some missing shuffle patterns.
...
llvm-svn: 27564
2006-04-10 21:42:19 +00:00
664fcba5fa
Correct an entry
...
llvm-svn: 27563
2006-04-10 21:41:39 +00:00
395fa3d2a6
movups / movupd
...
llvm-svn: 27562
2006-04-10 21:11:06 +00:00
a9cdcca3c3
Add a simple pass to make sure that all (non-library) calls to malloc and free
...
are visible to analysis as intrinsics. That is, make sure someone doesn't pass
free around by address in some struct (as happens in say 176.gcc).
This doesn't get rid of any indirect calls, just ensure calls to free and malloc
are always direct.
llvm-svn: 27560
2006-04-10 19:26:09 +00:00
cb73b8d419
Missing break
...
llvm-svn: 27559
2006-04-10 18:54:36 +00:00
617a6a812e
Conditional move of vector types.
...
llvm-svn: 27556
2006-04-10 07:23:14 +00:00
014849e121
New entries
...
llvm-svn: 27555
2006-04-10 07:22:03 +00:00
c9ed8e4c1a
Use movaps to do VR128 reg-to-reg copies for now. It's shorter and available for SSE1.
...
llvm-svn: 27554
2006-04-10 07:21:31 +00:00
3a68f3c3ca
properly mark vector selects as expanded to select_cc
...
llvm-svn: 27544
2006-04-08 22:59:15 +00:00
0a3d1bbca4
Add VRRC select support
...
llvm-svn: 27543
2006-04-08 22:45:08 +00:00
02274a5265
Add code generator support for VSELECT
...
llvm-svn: 27542
2006-04-08 22:22:57 +00:00
3f9c17906f
Disable switch lowering for targets based on the selection dag isel,
...
letting the code generator handle them directly.
llvm-svn: 27539
2006-04-08 19:46:55 +00:00
d9e80f4516
Implement PowerPC/CodeGen/vec_splat.ll:spltish to use vsplish instead of a
...
constant pool load.
llvm-svn: 27538
2006-04-08 07:14:26 +00:00
d71a1f946d
Change the interface to the predicate that determines if vsplti* can be used.
...
No functionality changes.
llvm-svn: 27536
2006-04-08 06:46:53 +00:00
cf905223c5
Initialize SDOperand values because the gcc 4.0.2 compiler complains about
...
them.
llvm-svn: 27534
2006-04-08 05:38:03 +00:00
e1401e3610
Canonicalize vvector_shuffle(x,x) -> vvector_shuffle(x,undef) to enable patterns
...
to match again :)
llvm-svn: 27533
2006-04-08 05:34:25 +00:00
a93b4b5866
Add constant replacement for insertelement/vectorshuffle constant exprs
...
llvm-svn: 27532
2006-04-08 05:09:48 +00:00
098c01e94e
Codegen shufflevector as VVECTOR_SHUFFLE
...
llvm-svn: 27529
2006-04-08 04:15:24 +00:00
101ea66813
add a sanity check: LegalizeOp should return a value that is the same type
...
as its input.
llvm-svn: 27528
2006-04-08 04:13:17 +00:00
fc72a6b72d
use isValidOperands instead of duplicating checks
...
llvm-svn: 27527
2006-04-08 04:09:19 +00:00
931565caf6
Regenerate
...
llvm-svn: 27526
2006-04-08 04:09:02 +00:00
80f554f209
Use isValidOperands instead of duplicating or eliding checks.
...
llvm-svn: 27525
2006-04-08 04:08:32 +00:00
38c4cb2f9e
Use the isValidOperands helper instead of duplicating checking code
...
llvm-svn: 27524
2006-04-08 04:07:52 +00:00
54865b39ab
Add methods to check insertelement/extractelement instructions for validity,
...
check validity when instructions are created.
llvm-svn: 27523
2006-04-08 04:05:48 +00:00
aebccf891a
regenerate
...
llvm-svn: 27521
2006-04-08 03:55:17 +00:00
8c32ad0040
Add insertelement and shufflevector constantexpr support
...
llvm-svn: 27520
2006-04-08 03:53:34 +00:00
78e3d565af
INSERT_VECTOR_ELT lowering bug:
...
store vector to $esp
store element to $esp + sizeof(VT) * index
load vector from $esp
The bug is VT is the type of the vector element, not the type of the vector!
llvm-svn: 27517
2006-04-08 01:46:37 +00:00
0197e454d1
Add shufflevector support
...
llvm-svn: 27515
2006-04-08 01:19:47 +00:00
aa3185f12e
Stub out shufflevector
...
llvm-svn: 27514
2006-04-08 01:19:25 +00:00
17bd60588c
Add supprot for shufflevector
...
llvm-svn: 27513
2006-04-08 01:19:12 +00:00
9ff96a70f2
regenerate
...
llvm-svn: 27512
2006-04-08 01:18:56 +00:00
8ec3c2e31f
Parse shufflevector
...
llvm-svn: 27511
2006-04-08 01:18:35 +00:00
bbe0a4248b
Add shufflevector support, todo, implement better constant folding.
...
llvm-svn: 27510
2006-04-08 01:18:18 +00:00
161e7cfc17
Add shufflevector reading support
...
llvm-svn: 27509
2006-04-08 01:17:59 +00:00
0df9c9f57d
ldmxcsr and stmxcsr.
...
llvm-svn: 27506
2006-04-08 00:47:44 +00:00
7d4592733c
Remove section change in function end, preventing override of function's real
...
section.
llvm-svn: 27503
2006-04-08 00:35:59 +00:00
ac847268c5
Code clean up.
...
llvm-svn: 27501
2006-04-07 21:53:05 +00:00
aa18a52545
Added patterns for MOVHPSmr and MOVLPSmr.
...
llvm-svn: 27497
2006-04-07 21:20:58 +00:00
748e573ce5
Keep track of an Mac OS X / x86 ABI bug.
...
llvm-svn: 27496
2006-04-07 21:19:53 +00:00
c0d6518f27
Make sure that debug labels are defined within the same section and after the
...
entry point of a function.
llvm-svn: 27494
2006-04-07 20:44:42 +00:00
2d7298c362
Foundation for call frame information.
...
llvm-svn: 27491
2006-04-07 16:34:46 +00:00
92b1a57010
We have an assertion that checks that we do not encode null values into the
...
.bc file if they are supposed to be implicit. This is cool, except that it
checked *after* constant expr folding: improving constant expr folding could
cause the .bc reader to assert out on old .bc files. Move the check so that
it checks all simple constants, but no constantexprs.
llvm-svn: 27480
2006-04-07 05:00:02 +00:00
e4f9d7b23c
Constant fold extractelement(zero, x) -> zero
...
llvm-svn: 27479
2006-04-07 04:44:06 +00:00
8ec0205de4
Fix inlining of insert/extract element constantexprs
...
llvm-svn: 27478
2006-04-07 04:41:03 +00:00
5c349b8b7d
Add code to RemapOperand() to handle Instruction::ExtractElement and
...
Instruction::InsertElement.
llvm-svn: 27477
2006-04-07 01:27:42 +00:00
d8e1a01be6
A MOVPS2SSmr, i.e. _mm_store_ss, encoding bug.
...
Also MOVPDI2DIrr.
llvm-svn: 27476
2006-04-06 23:53:29 +00:00
c995b45f67
- movlp{s|d} and movhp{s|d} support.
...
- Normalize shuffle nodes so result vector lower half elements come from the
first vector, the rest come from the second vector. (Except for the
exceptions :-).
- Other minor fixes.
llvm-svn: 27474
2006-04-06 23:23:56 +00:00
acf8b3c828
New entries.
...
llvm-svn: 27473
2006-04-06 23:21:24 +00:00
613996c55e
1. If both vector operands of a vector_shuffle are undef, turn it into an undef.
...
2. A shuffle mask element can also be an undef.
llvm-svn: 27472
2006-04-06 23:20:43 +00:00
1596a1b276
This may be overconservative, but it lets the new cfe compile
...
llvm-svn: 27471
2006-04-06 23:18:45 +00:00
e61cfad815
Add an item
...
llvm-svn: 27470
2006-04-06 23:16:19 +00:00
466841ddc7
Make sure to return the result in the right type.
...
llvm-svn: 27469
2006-04-06 23:12:19 +00:00
477169e36a
Move this to lib/Analysis.
...
This reduces Core size, yay.
llvm-svn: 27468
2006-04-06 22:58:58 +00:00
a4bbfaed5c
Match vpku[hw]um(x,x).
...
Convert vsldoi(x,x) to work the same way other (x,x) cases work.
llvm-svn: 27467
2006-04-06 22:28:36 +00:00
f38e033270
Add support for matching vmrg(x,x) patterns
...
llvm-svn: 27463
2006-04-06 22:02:42 +00:00
cee782d514
fix some linking problems with the new gcc
...
llvm-svn: 27460
2006-04-06 21:26:32 +00:00
d1dcb52093
Pattern match vmrg* instructions, which are now lowered by the CFE into shuffles.
...
llvm-svn: 27457
2006-04-06 21:11:54 +00:00
a4c727f1cc
remove two done items
...
llvm-svn: 27453
2006-04-06 19:19:38 +00:00
e79d249c29
Lower vperm(x,y, mask) -> shuffle(x,y,mask) if mask is constant. This allows
...
us to compile oh-so-realistic stuff like this:
vec_vperm(A, B, (vector unsigned char){14});
to:
vspltb v0, v0, 14
instead of:
vspltisb v0, 14
vperm v0, v2, v1, v0
llvm-svn: 27452
2006-04-06 19:19:17 +00:00
1d33819194
Support pattern matching vsldoi(x,y) and vsldoi(x,x), which allows the f.e. to
...
lower it and LLVM to have one fewer intrinsic. This implements
CodeGen/PowerPC/vec_shuffle.ll
llvm-svn: 27450
2006-04-06 18:26:28 +00:00
e8b83b4206
Compile the vpkuhum/vpkuwum intrinsics into vpkuhum/vpkuwum instead of into
...
vperm with a perm mask lvx'd from the constant pool.
llvm-svn: 27448
2006-04-06 17:23:16 +00:00
695e45c252
POR encoded as PAND, yikes.
...
llvm-svn: 27446
2006-04-06 01:49:20 +00:00
dddb688a40
An entry about comi / ucomi intrinsics.
...
llvm-svn: 27445
2006-04-05 23:46:04 +00:00
780382946e
Support for comi / ucomi intrinsics.
...
llvm-svn: 27444
2006-04-05 23:38:46 +00:00
c94d932447
Add all of the data stream intrinsics and instructions. woo
...
llvm-svn: 27442
2006-04-05 22:27:14 +00:00
39dc64c955
Fix a typo
...
llvm-svn: 27440
2006-04-05 20:15:25 +00:00
39cc717c65
Fix CodeGen/PowerPC/2006-04-05-splat-ish.ll
...
llvm-svn: 27439
2006-04-05 17:39:25 +00:00
f3b52c84ea
Handle canonical form of e.g.
...
vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>
This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.
It would match a {p}unpckl on x86.
llvm-svn: 27437
2006-04-05 07:20:06 +00:00
4a2413a590
Make a vector live across blocks have the correct Vec type. This fixes
...
CodeGen/X86/2006-04-04-CrossBlockCrash.ll
llvm-svn: 27436
2006-04-05 06:54:42 +00:00
6d196db40d
Bogus assert
...
llvm-svn: 27434
2006-04-05 06:11:20 +00:00
2cf4232ced
Fallthrough to expand if a VECTOR_SHUFFLE cannot be custom lowered.
...
llvm-svn: 27433
2006-04-05 06:09:26 +00:00
9fa8959dce
Exapnd a VECTOR_SHUFFLE to a BUILD_VECTOR if target asks for it to be expanded
...
or custom lowering fails.
llvm-svn: 27432
2006-04-05 06:07:11 +00:00
8f321af723
revert this, this is safe, if conservative. leave a note to that effect
...
llvm-svn: 27428
2006-04-05 02:42:36 +00:00
59a6355e82
Handle v8i16 shuffle that must be broken into a pair of pshufhw / pshuflw.
...
llvm-svn: 27427
2006-04-05 01:47:37 +00:00
2f8e2b2895
add vsl
...
llvm-svn: 27425
2006-04-05 01:16:22 +00:00
575352ac20
add vmladduhm
...
llvm-svn: 27423
2006-04-05 00:49:48 +00:00
5a528e565b
Add m[tf]vscr instructions.
...
llvm-svn: 27421
2006-04-05 00:03:57 +00:00
0c82447c66
add a note
...
llvm-svn: 27419
2006-04-04 23:45:11 +00:00
281bb5da1d
Add missing byte merges.
...
llvm-svn: 27418
2006-04-04 23:43:56 +00:00
fc50ae521c
Add FP -> Int Conversions
...
llvm-svn: 27417
2006-04-04 23:25:02 +00:00
96338b6a21
add average intrinsics
...
llvm-svn: 27416
2006-04-04 23:14:00 +00:00
4464383a17
add a note
...
llvm-svn: 27414
2006-04-04 22:43:55 +00:00
4a744e5c9d
Fix some broken logic that would cause us to codegen {2147483647,2147483647,2147483647,2147483647} as 'vspltisb v0, -1'.
...
llvm-svn: 27413
2006-04-04 22:28:35 +00:00
011c23d9d3
Added pslldq and psrldq.
...
llvm-svn: 27412
2006-04-04 21:49:39 +00:00
8f3b6b8d8a
Minor fixes + naming changes.
...
llvm-svn: 27410
2006-04-04 19:12:30 +00:00
802b35c339
PSHUF* encoding bugs.
...
llvm-svn: 27405
2006-04-04 18:40:36 +00:00
4ea52cac01
Do not create ZEXTLOAD's unless we are before legalize or the operation is
...
legal.
llvm-svn: 27402
2006-04-04 17:39:18 +00:00
95c7adc7cb
Ask legalize to promote all vector shuffles to be v16i8 instead of having to
...
handle all 4 PPC vector types. This simplifies the matching code and allows
us to eliminate a bunch of patterns. This also adds cases we were missing,
such as CodeGen/PowerPC/vec_splat.ll:splat_h.
llvm-svn: 27400
2006-04-04 17:25:31 +00:00
6be79823e7
* Add supprot for SCALAR_TO_VECTOR operations where the input needs to be
...
promoted/expanded (e.g. SCALAR_TO_VECTOR from i8/i16 on PPC).
* Add support for targets to request that VECTOR_SHUFFLE nodes be promoted
to a canonical type, for example, we only want v16i8 shuffles on PPC.
* Move isShuffleLegal out of TLI into Legalize.
* Teach isShuffleLegal to allow shuffles that need to be promoted.
llvm-svn: 27399
2006-04-04 17:23:26 +00:00
6b2c9748c3
Signed shr by a constant is not the same as sdiv by 2^k
...
llvm-svn: 27395
2006-04-04 06:11:42 +00:00
e91e3bd874
cmpps / cmppd encoding bug
...
llvm-svn: 27393
2006-04-04 03:04:07 +00:00
a9e77d14c7
Constant fold bitconvert(undef)
...
llvm-svn: 27391
2006-04-04 01:02:22 +00:00
dd2eb27d6d
Compact some intrinsic definitions.
...
llvm-svn: 27388
2006-04-04 00:10:53 +00:00
b1e6d84544
Plug in the byte and short splats
...
llvm-svn: 27387
2006-04-04 00:05:13 +00:00
447a7968af
Revert accidentally committed hunks.
...
llvm-svn: 27386
2006-04-03 23:58:04 +00:00
533aed9a35
Make sure to mark unsupported SCALAR_TO_VECTOR operations as expand.
...
llvm-svn: 27385
2006-04-03 23:55:43 +00:00
0ef83c83e1
Some SSE1 intrinsics: min, max, sqrt, etc.
...
llvm-svn: 27384
2006-04-03 23:49:17 +00:00
bf0016f2d4
revert previous patch
...
llvm-svn: 27383
2006-04-03 23:14:49 +00:00
b64827e662
Use movlpd to: store lower f64 extracted from v2f64.
...
Use movhpd to: store upper f64 extracted from v2f64.
llvm-svn: 27382
2006-04-03 22:30:54 +00:00
5400727595
Force use of a frame-pointer if there is anything on the stack that is aligned
...
more than the OS keeps the stack aligned.
llvm-svn: 27381
2006-04-03 22:03:29 +00:00
b710a81e54
The stack alignment is now computed dynamically, just verify it is correct.
...
llvm-svn: 27380
2006-04-03 21:39:57 +00:00
6bc4b9c7f8
Remove unused method
...
llvm-svn: 27379
2006-04-03 21:39:03 +00:00
ebf1006d16
- More efficient extract_vector_elt with shuffle and movss, movsd, movd, etc.
...
- Some bug fixes and naming inconsistency fixes.
llvm-svn: 27377
2006-04-03 20:53:28 +00:00
78c788b450
Align vectors to the size in bytes, not bits.
...
llvm-svn: 27376
2006-04-03 19:28:50 +00:00
e1e3adf802
Add a missing check, this fixes UnitTests/Vector/sumarray.c
...
llvm-svn: 27375
2006-04-03 17:29:28 +00:00
04c00fc844
Add a missing check, which broke a bunch of vector tests.
...
llvm-svn: 27374
2006-04-03 17:21:50 +00:00
9ccd61c893
Add the full set of min/max instructions
...
llvm-svn: 27372
2006-04-03 15:58:28 +00:00
df7abf8b74
support x * (c1 + c2) where c1 and c2 are pow2s. special case for c2 == 4
...
llvm-svn: 27370
2006-04-03 04:19:17 +00:00
4e2c073a33
mul by const conversion sequences. more coming soon
...
llvm-svn: 27368
2006-04-03 03:18:59 +00:00
94f012f606
back this out
...
llvm-svn: 27367
2006-04-03 03:16:50 +00:00
015eaf5f33
This should be a win of every arch
...
llvm-svn: 27364
2006-04-02 21:42:45 +00:00
444bdb069a
This makes McCat/12-IOtest go 8x faster or so
...
llvm-svn: 27363
2006-04-02 21:08:39 +00:00
01bd5523a3
This will be needed soon
...
llvm-svn: 27362
2006-04-02 20:13:57 +00:00
acf1fc8a28
add a note
...
llvm-svn: 27360
2006-04-02 07:20:00 +00:00
c5287c0ece
Inform the dag combiner that the predicate compares only return a low bit.
...
llvm-svn: 27359
2006-04-02 06:26:07 +00:00
6c1321ca3f
relax assertion
...
llvm-svn: 27358
2006-04-02 06:19:46 +00:00
e6025525fb
Allow targets to compute masked bits for intrinsics.
...
llvm-svn: 27357
2006-04-02 06:15:09 +00:00
4993249a04
Add a little dag combine to compile this:
...
int %AreSecondAndThirdElementsBothNegative(<4 x float>* %in) {
entry:
%tmp1 = load <4 x float>* %in ; <<4 x float>> [#uses=1]
%tmp = tail call int %llvm.ppc.altivec.vcmpgefp.p( int 1, <4 x float> < float 0x7FF8000000000000, float 0.000000e+00, float 0.000000e+00, float 0x7FF8000000000000 >, <4 x float> %tmp1 ) ; <int> [#uses=1]
%tmp = seteq int %tmp, 0 ; <bool> [#uses=1]
%tmp3 = cast bool %tmp to int ; <int> [#uses=1]
ret int %tmp3
}
into this:
_AreSecondAndThirdElementsBothNegative:
mfspr r2, 256
oris r4, r2, 49152
mtspr 256, r4
li r4, lo16(LCPI1_0)
lis r5, ha16(LCPI1_0)
lvx v0, 0, r3
lvx v1, r5, r4
vcmpgefp. v0, v1, v0
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
mtspr 256, r2
blr
instead of this:
_AreSecondAndThirdElementsBothNegative:
mfspr r2, 256
oris r4, r2, 49152
mtspr 256, r4
li r4, lo16(LCPI1_0)
lis r5, ha16(LCPI1_0)
lvx v0, 0, r3
lvx v1, r5, r4
vcmpgefp. v0, v1, v0
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
xori r3, r3, 1
cntlzw r3, r3
srwi r3, r3, 5
mtspr 256, r2
blr
llvm-svn: 27356
2006-04-02 06:11:11 +00:00
caba72b6ff
vector casts of casts are eliminable. Transform this:
...
%tmp = cast <4 x uint> %tmp to <4 x int> ; <<4 x int>> [#uses=1]
%tmp = cast <4 x int> %tmp to <4 x float> ; <<4 x float>> [#uses=1]
into:
%tmp = cast <4 x uint> %tmp to <4 x float> ; <<4 x float>> [#uses=1]
llvm-svn: 27355
2006-04-02 05:43:13 +00:00
7ee10dec05
vector casts never reinterpret bits
...
llvm-svn: 27354
2006-04-02 05:40:28 +00:00
ebca476b27
Allow transforming this:
...
%tmp = cast <4 x uint>* %testData to <4 x int>* ; <<4 x int>*> [#uses=1]
%tmp = load <4 x int>* %tmp ; <<4 x int>> [#uses=1]
to this:
%tmp = load <4 x uint>* %testData ; <<4 x uint>> [#uses=1]
%tmp = cast <4 x uint> %tmp to <4 x int> ; <<4 x int>> [#uses=1]
llvm-svn: 27353
2006-04-02 05:37:12 +00:00
Chris Lattner