45c709388a
Compactify comparisons.
...
llvm-svn: 27287
2006-03-31 05:32:57 +00:00
d7495ae7e9
Lower vector compares to VCMP nodes, just like we lower vector comparison
...
predicates to VCMPo nodes.
llvm-svn: 27285
2006-03-31 05:13:27 +00:00
e5a6c4f8b7
These are done
...
llvm-svn: 27284
2006-03-31 04:53:21 +00:00
b37dfd631c
Add a new method to verify intrinsic function prototypes.
...
llvm-svn: 27282
2006-03-31 04:46:47 +00:00
ba38035e21
Make sure to pass enough values to phi nodes when we are dealing with
...
decimated vectors. This fixes UnitTests/Vector/sumarray-dbl.c
llvm-svn: 27280
2006-03-31 02:12:18 +00:00
5fe1f54c17
Significantly improve handling of vectors that are live across basic blocks,
...
handling cases where the vector elements need promotion, expansion, and when
the vector type itself needs to be decimated.
llvm-svn: 27278
2006-03-31 02:06:56 +00:00
051f7861b8
Was returning the wrong type.
...
llvm-svn: 27277
2006-03-31 01:50:09 +00:00
bca5fbe914
Mark INSERT_VECTOR_ELT as expand
...
llvm-svn: 27276
2006-03-31 01:48:55 +00:00
1b0d294de0
Expand all INSERT_VECTOR_ELT (obviously bad) for now.
...
llvm-svn: 27275
2006-03-31 01:30:39 +00:00
168e45b0b3
Expand INSERT_VECTOR_ELT to store vec, sp; store elt, sp+k; vec = load sp;
...
llvm-svn: 27274
2006-03-31 01:27:51 +00:00
f144dac7b7
Modify the TargetLowering::getPackedTypeBreakdown method to also return the
...
unpromoted element type.
llvm-svn: 27273
2006-03-31 00:46:36 +00:00
d9d0bbb5ac
Typo
...
llvm-svn: 27272
2006-03-31 00:33:57 +00:00
99d7205fba
Ok for vector_shuffle mask to contain undef elements.
...
llvm-svn: 27271
2006-03-31 00:30:29 +00:00
549fb167eb
Implement TargetLowering::getPackedTypeBreakdown
...
llvm-svn: 27270
2006-03-31 00:28:56 +00:00
c4e3eadf21
Add the rest of the vmul instructions and the vmulsum* instructions.
...
llvm-svn: 27268
2006-03-30 23:39:06 +00:00
a23158f1ca
Use a new tblgen feature to significantly shrinkify instruction definitions that
...
directly correspond to intrinsics.
llvm-svn: 27266
2006-03-30 23:21:27 +00:00
551d3a11d3
Add a bunch of new instructions for intrinsics.
...
llvm-svn: 27265
2006-03-30 23:07:36 +00:00
612fa8e6f3
Fix Transforms/InstCombine/2006-03-30-ExtractElement.ll
...
llvm-svn: 27261
2006-03-30 22:02:40 +00:00
7e2ff11a42
Make sure all possible shuffles are matched.
...
Use pshufd, pshuhw, and pshulw to shuffle v4f32 if shufps doesn't match.
Use shufps to shuffle v4f32 if pshufd, pshuhw, and pshulw don't match.
llvm-svn: 27259
2006-03-30 19:54:57 +00:00
dd487d865b
More logical ops patterns
...
llvm-svn: 27257
2006-03-30 07:33:32 +00:00
c58ef7deeb
Add support for _mm_cmp{cc}_ss and _mm_cmp{cc}_ps intrinsics
...
llvm-svn: 27256
2006-03-30 06:21:22 +00:00
593310016d
Add 128-bit pmovmskb intrinsic support.
...
llvm-svn: 27255
2006-03-30 00:33:26 +00:00
c5cf9bba05
Change SSE pack operation definitions to fit what the intrinsics expected.
...
For example, packsswb actually creates a v16i8 from a pair of v8i16. But since
the intrinsic specification forces the output type to match the operands.
llvm-svn: 27254
2006-03-29 23:53:14 +00:00
b7fedffc78
- Added some SSE2 128-bit packed integer ops.
...
- Added SSE2 128-bit integer pack with signed saturation ops.
- Added pshufhw and pshuflw ops.
llvm-svn: 27252
2006-03-29 23:07:14 +00:00
acc336475e
Need to special case splat after all. Make the second operand of splat
...
vector_shuffle undef.
llvm-svn: 27250
2006-03-29 19:02:40 +00:00
3cf95747c7
Floating point logical operation patterns should match bit_convert. Or else
...
integer vector logical operations would match andp{s|d} instead of pand.
llvm-svn: 27248
2006-03-29 18:47:40 +00:00
500ec16578
- More shuffle related bug fixes.
...
- Whenever possible use ops of the right packed types for vector shuffles /
splats.
llvm-svn: 27246
2006-03-29 03:04:49 +00:00
3a1c4e75de
Another entry about shuffles.
...
llvm-svn: 27245
2006-03-29 03:03:46 +00:00
da59b0d2a8
- Only use pshufd for v4i32 vector shuffles.
...
- Other shuffle related fixes.
llvm-svn: 27244
2006-03-29 01:30:51 +00:00
7d6f4f14b4
add a note
...
llvm-svn: 27243
2006-03-29 00:24:13 +00:00
67271869a8
Bug fixes: handle constantexpr insert/extract element operations
...
Handle constantpacked vectors with constantexpr elements.
This fixes CodeGen/Generic/vector-constantexpr.ll
llvm-svn: 27241
2006-03-29 00:11:43 +00:00
38b34296d0
Added aliases to scalar SSE instructions, e.g. addss, to match x86 intrinsics.
...
The source operands type are v4sf with upper bits passes through.
Added matching code for these.
llvm-svn: 27240
2006-03-28 23:51:43 +00:00
8160fd3d42
Fixing buggy code.
...
llvm-svn: 27239
2006-03-28 23:41:33 +00:00
20e619fba3
When building a VVECTOR_SHUFFLE node from extract_element operations, make
...
sure to build it as SHUFFLE(X, undef, mask), not SHUFFLE(X, X, mask).
The later is not canonical form, and prevents the PPC splat pattern from
matching. For a particular splat, we go from generating this:
li r10, lo16(LCPI1_0)
lis r11, ha16(LCPI1_0)
lvx v3, r11, r10
vperm v3, v2, v2, v3
to generating:
vspltw v3, v2, 3
llvm-svn: 27236
2006-03-28 22:19:47 +00:00
a46dfe80c8
Canonicalize VECTOR_SHUFFLE(X, X, Y) -> VECTOR_SHUFFLE(X,undef,Y')
...
llvm-svn: 27235
2006-03-28 22:11:53 +00:00
c9992548fc
Turn a series of extract_element's feeding a build_vector into a
...
vector_shuffle node. For this:
void test(__m128 *res, __m128 *A, __m128 *B) {
*res = _mm_unpacklo_ps(*A, *B);
}
we now produce this code:
_test:
movl 8(%esp), %eax
movaps (%eax), %xmm0
movl 12(%esp), %eax
unpcklps (%eax), %xmm0
movl 4(%esp), %eax
movaps %xmm0, (%eax)
ret
instead of this:
_test:
subl $76, %esp
movl 88(%esp), %eax
movaps (%eax), %xmm0
movaps %xmm0, (%esp)
movaps %xmm0, 32(%esp)
movss 4(%esp), %xmm0
movss 32(%esp), %xmm1
unpcklps %xmm0, %xmm1
movl 84(%esp), %eax
movaps (%eax), %xmm0
movaps %xmm0, 16(%esp)
movaps %xmm0, 48(%esp)
movss 20(%esp), %xmm0
movss 48(%esp), %xmm2
unpcklps %xmm0, %xmm2
unpcklps %xmm1, %xmm2
movl 80(%esp), %eax
movaps %xmm2, (%eax)
addl $76, %esp
ret
GCC produces this (with -fomit-frame-pointer):
_test:
subl $12, %esp
movl 20(%esp), %eax
movaps (%eax), %xmm0
movl 24(%esp), %eax
unpcklps (%eax), %xmm0
movl 16(%esp), %eax
movaps %xmm0, (%eax)
addl $12, %esp
ret
llvm-svn: 27233
2006-03-28 20:28:38 +00:00
f6f94d3bce
Teach Legalize how to pack VVECTOR_SHUFFLE nodes into VECTOR_SHUFFLE nodes.
...
llvm-svn: 27232
2006-03-28 20:24:43 +00:00
8d57da2ffc
new node
...
llvm-svn: 27231
2006-03-28 19:54:42 +00:00
b7163598f9
Don't crash on X^X if X is a vector. Instead, produce a vector of zeros.
...
llvm-svn: 27229
2006-03-28 19:11:05 +00:00
ffec47ebff
Add an assertion
...
llvm-svn: 27228
2006-03-28 19:04:49 +00:00
66e1410858
add a note
...
llvm-svn: 27227
2006-03-28 18:56:23 +00:00
dea0348853
Refactor address attributes. Add base register to frame info.
...
llvm-svn: 27226
2006-03-28 14:58:32 +00:00
d1aa1638c6
Expose base register for DwarfWriter. Refactor code accordingly.
...
llvm-svn: 27225
2006-03-28 13:48:33 +00:00
67a636c587
More bulletproofing of llvm.dbg.declare.
...
llvm-svn: 27224
2006-03-28 13:45:20 +00:00
457e54efc1
Added missing paren on behalf of Ramana Radhakrishnan.
...
llvm-svn: 27223
2006-03-28 10:17:11 +00:00
21e5476deb
Missed X86::isUNPCKHMask
...
llvm-svn: 27222
2006-03-28 08:27:15 +00:00
be2d9a0e99
movlps and movlpd should be modeled as two address code.
...
llvm-svn: 27221
2006-03-28 07:01:28 +00:00
dc57ae0711
Update
...
llvm-svn: 27220
2006-03-28 06:55:45 +00:00
4e7374ff8a
Typo
...
llvm-svn: 27219
2006-03-28 06:53:49 +00:00
1a194a5264
* Prefer using operation of matching types. e.g unpcklpd rather than movlhps.
...
* Bug fixes.
llvm-svn: 27218
2006-03-28 06:50:32 +00:00
af8c373e77
Fix a couple typos
...
llvm-svn: 27216
2006-03-28 04:18:18 +00:00
1b3928765d
Add a few more altivec intrinsics
...
llvm-svn: 27215
2006-03-28 04:15:58 +00:00
08b473c619
Added a couple of entries about movhps and movlhps.
...
llvm-svn: 27212
2006-03-28 02:49:12 +00:00
3765fadef6
All unpack cases are now being handled.
...
llvm-svn: 27211
2006-03-28 02:44:05 +00:00
2bc3280659
- Clean up / consoladate various shuffle masks.
...
- Some misc. bug fixes.
- Use MOVHPDrm to load from m64 to upper half of a XMM register.
llvm-svn: 27210
2006-03-28 02:43:26 +00:00
3710fca2b8
implement a bunch more intrinsics.
...
llvm-svn: 27209
2006-03-28 02:29:37 +00:00
cb5ec07cc3
Use normal lvx for scalar_to_vector instead of lve*x. They do the exact
...
same thing and we have a dag node for the former.
llvm-svn: 27205
2006-03-28 01:43:22 +00:00
8374e9c4eb
More bulletproofing of DebugInfoDesc verify.
...
llvm-svn: 27203
2006-03-28 01:30:18 +00:00
e55d171ccd
Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value. Split them into separate enums.
...
llvm-svn: 27201
2006-03-28 00:40:33 +00:00
5df75889db
Model unpack lower and interleave as vector_shuffle so we can lower the
...
intrinsics as such.
llvm-svn: 27200
2006-03-28 00:39:58 +00:00
d7e612bbc4
If adding a link to a collapsed, node, ignore offset.
...
Fixes 2006-03-27-LinkedCollapsed.ll
llvm-svn: 27194
2006-03-27 23:39:58 +00:00
d387cc5cde
Reactivate llvm.dbg.declare.
...
llvm-svn: 27192
2006-03-27 23:31:10 +00:00
5bb1d90afd
Disable dbg_declare, it currently breaks the CFE build
...
llvm-svn: 27182
2006-03-27 21:36:03 +00:00
d5f94c9574
Fix legalization of intrinsics with chain and result values
...
llvm-svn: 27181
2006-03-27 20:28:29 +00:00
fa53b276d0
Translate llvm target registers to dwarf register numbers properly.
...
llvm-svn: 27180
2006-03-27 20:18:45 +00:00
018e17c8de
unbreak the build
...
llvm-svn: 27174
2006-03-27 16:52:45 +00:00
0e84f1e532
Unbreak the build on non-apple compilers :-(
...
llvm-svn: 27173
2006-03-27 16:10:59 +00:00
d09b05b0bc
Try again
...
llvm-svn: 27171
2006-03-27 08:10:26 +00:00
939c9ab88f
Add a bunch of notes from my journey thus far.
...
llvm-svn: 27170
2006-03-27 07:41:00 +00:00
64efb35c32
Incorrect check for FP all one's
...
llvm-svn: 27169
2006-03-27 07:26:17 +00:00
22ec3e7b7e
Split out altivec notes into their own README
...
llvm-svn: 27168
2006-03-27 07:04:16 +00:00
9b9cc4fb39
Use pcmpeq to generate vector of all ones.
...
llvm-svn: 27167
2006-03-27 07:00:16 +00:00
a74792fa9d
Changed isBuildVectorAllOnesInteger to isBuildVectorAllOnes.
...
llvm-svn: 27166
2006-03-27 06:59:32 +00:00
c70e33cd6e
Change isBuildVectorAllOnesInteger to isBuildVectorAllOnes. Also check for
...
floating point cases.
llvm-svn: 27165
2006-03-27 06:58:47 +00:00
52fcad3a37
Instead of printing "INTRINSIC" on intrinsic node, print the intrinsic name.
...
llvm-svn: 27164
2006-03-27 06:45:25 +00:00
42e0ba09aa
teach the inliner to work with packed constants
...
llvm-svn: 27161
2006-03-27 05:50:18 +00:00
1738c293b5
Fix the JIT encoding of VSEL
...
llvm-svn: 27160
2006-03-27 03:34:17 +00:00
df59d5314c
Fix the JIT encoding of VSPLTI*
...
llvm-svn: 27159
2006-03-27 03:28:57 +00:00
6e792f9ff8
Pass llvm/test/Regression/CodeGen/Generic/debug-info.ll.
...
llvm-svn: 27158
2006-03-27 01:51:47 +00:00
ed728c1291
SelectionDAGISel can now natively handle Switch instructions, in the same
...
manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks. The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.
This functionality is currently only enabled on x86, but should be safe for
every target. In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.
llvm-svn: 27156
2006-03-27 01:32:24 +00:00
7092888bcc
Bullet proof against undefined args produced by upgrading ols-style debug info.
...
llvm-svn: 27155
2006-03-26 22:46:27 +00:00
84c2f0a705
How to be dumb on $5/day. Need a tri-state to track valid debug descriptors.
...
llvm-svn: 27154
2006-03-26 22:45:20 +00:00
65473e20d8
add vsel
...
llvm-svn: 27153
2006-03-26 22:38:43 +00:00
68cc9d4540
Readme note
...
llvm-svn: 27152
2006-03-26 19:19:27 +00:00
6961fc76bb
Codegen vector predicate compares.
...
llvm-svn: 27151
2006-03-26 10:06:40 +00:00
ed6184aef2
Remove X86:isZeroVector, use ISD::isBuildVectorAllZeros instead; some fixes / cleanups
...
llvm-svn: 27150
2006-03-26 09:53:12 +00:00
b1ddc988af
Remove PPC:isZeroVector, use ISD::isBuildVectorAllZeros instead
...
llvm-svn: 27149
2006-03-26 09:52:32 +00:00
5562f2092f
Add immAllZerosV helper
...
llvm-svn: 27148
2006-03-26 09:51:39 +00:00
a67899195f
Add ISD::isBuildVectorAllZeros predicate
...
llvm-svn: 27147
2006-03-26 09:50:58 +00:00
30ee72586d
Allow targets to custom lower their own intrinsics if desired.
...
llvm-svn: 27146
2006-03-26 09:12:51 +00:00
563c7022a5
Update dependencies to reflect split of the Intrinsics.td file
...
llvm-svn: 27144
2006-03-26 07:45:48 +00:00
793cbcb4fd
Add all of the altivec comparison instructions. Add patterns for the
...
non-predicate altivec compare intrinsics.
llvm-svn: 27143
2006-03-26 04:57:17 +00:00
c6c88b2ea1
Add and 8/16-bit adds, add all integer subtracts, add saturating subtract
...
intrinsics.
llvm-svn: 27142
2006-03-26 02:39:02 +00:00
53e07decd7
implement the vsldoi intrinsic.
...
llvm-svn: 27139
2006-03-26 00:41:48 +00:00
5c0c762443
fix the pattern for vandc, it's NOT vnand
...
llvm-svn: 27136
2006-03-25 23:10:40 +00:00
e8c1d04051
add patterns for VANDC/VNOR, implementing
...
CodeGen/PowerPC/eqv-andc-orc-nor.ll:VNOR/VANDC
llvm-svn: 27135
2006-03-25 23:05:29 +00:00
b6e2d0027a
Add some comments.
...
llvm-svn: 27133
2006-03-25 23:00:56 +00:00
3de9286e09
add a vnot helper node for matching 'not' on vectors
...
llvm-svn: 27132
2006-03-25 23:00:08 +00:00
f6e3b957b8
Fix a bug in ISD::isBuildVectorAllOnesInteger that caused it to always return
...
false
llvm-svn: 27131
2006-03-25 22:59:28 +00:00
c2d2811a07
Implement the ISD::isBuildVectorAllOnesInteger predicate
...
llvm-svn: 27130
2006-03-25 22:57:01 +00:00
dc1eab5886
Don't call SimplifyDemandedBits on vectors
...
llvm-svn: 27128
2006-03-25 22:19:00 +00:00
b3617beb52
Add some logical operations
...
llvm-svn: 27127
2006-03-25 22:16:05 +00:00
d70d9f5b24
Don't crash on packed logical ops
...
llvm-svn: 27125
2006-03-25 21:58:26 +00:00
e8e7ac465d
Teach BinaryOperator::createNot to work with packed integer types
...
llvm-svn: 27124
2006-03-25 21:54:21 +00:00
b434464d1c
Cast instruction not inserted into basic block.
...
llvm-svn: 27122
2006-03-25 18:40:47 +00:00
3e4d38eea5
Added missing (any_extend (load ...)) patterns.
...
llvm-svn: 27120
2006-03-25 09:45:48 +00:00
2bc0941e2a
Build arbitrary vector with more than 2 distinct scalar elements with a
...
series of unpack and interleave ops.
llvm-svn: 27119
2006-03-25 09:37:23 +00:00
1b4bb22f8a
implement a bunch of intrinsics
...
llvm-svn: 27118
2006-03-25 08:01:02 +00:00
2a85fa1f79
Move all Altivec stuff out into a new PPCInstrAltivec.td file.
...
Add a bunch of patterns for different datatypes, e.g. bit_convert, undef and
zero vector support.
llvm-svn: 27117
2006-03-25 07:51:43 +00:00
1cb91b3cd9
Add some basic patterns for other datatypes
...
llvm-svn: 27116
2006-03-25 07:39:07 +00:00
3a66a75108
add all supported formats to the vector register file
...
llvm-svn: 27115
2006-03-25 07:36:56 +00:00
f653cdd3f9
Add support for __builtin_altivec_vnmsubfp /vmaddfp
...
llvm-svn: 27112
2006-03-25 07:05:55 +00:00
5d70a7c4a5
#include Intrinsics.h into all dag isels
...
llvm-svn: 27109
2006-03-25 06:47:10 +00:00
71b8c980da
Implement Intrinsic::getName
...
llvm-svn: 27108
2006-03-25 06:32:47 +00:00
2771e2c960
Codegen things like:
...
<int -1, int -1, int -1, int -1>
and
<int 65537, int 65537, int 65537, int 65537>
Using things like:
vspltisb v0, -1
and:
vspltish v0, 1
instead of using constant pool loads.
This implements CodeGen/PowerPC/vec_splat.ll:splat_imm_i{32|16}.
llvm-svn: 27106
2006-03-25 06:12:06 +00:00
79e500ec74
Added SSE cachebility ops
...
llvm-svn: 27103
2006-03-25 06:03:26 +00:00
1aaa7280cd
Instruction encoding bug
...
llvm-svn: 27102
2006-03-25 06:00:03 +00:00
9dc2d17ae6
Add new intrinsic node definitions for tblgen use
...
llvm-svn: 27100
2006-03-25 02:29:35 +00:00
6f7d31ea50
Added 128-bit packed integer subtraction.
...
llvm-svn: 27096
2006-03-25 01:33:37 +00:00
8e481df625
Added CVTTPS2PI.
...
llvm-svn: 27095
2006-03-25 01:31:59 +00:00
980c4d5b46
Added CVTSS2SI.
...
llvm-svn: 27094
2006-03-25 01:00:18 +00:00
e7ee6a5e32
Support for scalar to vector with zero extension.
...
llvm-svn: 27091
2006-03-24 23:15:12 +00:00
313229c74b
fix inverted conditional
...
llvm-svn: 27089
2006-03-24 22:49:42 +00:00
bb84eae239
D'oh - should be even numbered.
...
llvm-svn: 27088
2006-03-24 22:48:02 +00:00
2f0277bf48
Added LDMXCSR
...
llvm-svn: 27087
2006-03-24 22:28:37 +00:00
97599f1211
plug the intrinsics into the patterns for movmsk*
...
llvm-svn: 27083
2006-03-24 21:49:18 +00:00
f0729b4067
Add dwarf register numbering to register data.
...
llvm-svn: 27081
2006-03-24 21:15:58 +00:00
3b338d5566
Add support for dwarf register numbering.
...
llvm-svn: 27080
2006-03-24 21:13:21 +00:00
3324c7236f
Hack no more.
...
llvm-svn: 27079
2006-03-24 21:10:36 +00:00
9f9b6116e1
add another note
...
llvm-svn: 27077
2006-03-24 20:04:27 +00:00
0affd76182
add a note
...
llvm-svn: 27076
2006-03-24 19:59:17 +00:00
c6b13e21cc
Shuffle some includes around
...
llvm-svn: 27073
2006-03-24 18:52:35 +00:00
68d9bf26c8
Only to vector shuffle for {x,x,y,y} cases when SCALAR_TO_VECTOR is free.
...
llvm-svn: 27071
2006-03-24 18:45:20 +00:00
58a9622957
expose intrinsic info to the targets.
...
llvm-svn: 27070
2006-03-24 18:44:11 +00:00
d589dd1352
Fix a bad JIT encoding of VPERM. Why is VPERM D,A,B,C but vfmadd is D,A,C,B ??
...
llvm-svn: 27069
2006-03-24 18:24:43 +00:00
f2286d5917
Like the comment says, prefer to use the implicit add done by [r+r] addressing
...
modes than emitting an explicit add and using a base of r0. This implements
Regression/CodeGen/PowerPC/mem-rr-addr-mode.ll
llvm-svn: 27068
2006-03-24 17:58:06 +00:00
dd3fa41f0f
Fix indent.
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llvm-svn: 27065
2006-03-24 10:08:23 +00:00
864e444749
Clean up some commentary.
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llvm-svn: 27064
2006-03-24 10:00:56 +00:00
53f1ecc560
Rename for truth in advertising.
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llvm-svn: 27063
2006-03-24 09:50:27 +00:00
a90b7141ed
Disable the i32->float G5 optimization. It is unsafe, as documented in the
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comment.
This fixes 177.mesa, and McCat/09-vor with the td scheduler.
llvm-svn: 27060
2006-03-24 07:53:47 +00:00
ab882abce8
add support for using vxor to build zero vectors. This implements
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Regression/CodeGen/PowerPC/vec_zero.ll
llvm-svn: 27059
2006-03-24 07:48:08 +00:00
082c8785ef
Handle BUILD_VECTOR with all zero elements.
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llvm-svn: 27056
2006-03-24 07:29:27 +00:00
77e271cb4e
prefer to generate constant pool loads over splats. This prevents us from
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using a splat for {1.0,1.0,1.0,1.0}
llvm-svn: 27055
2006-03-24 07:29:17 +00:00
87b1dddb1c
fix spello
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llvm-svn: 27053
2006-03-24 07:15:07 +00:00
f365f5f0c1
Fix spello
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llvm-svn: 27052
2006-03-24 07:14:34 +00:00
5821a6a17a
add the actual cost to the debug info
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llvm-svn: 27051
2006-03-24 07:14:00 +00:00
f5efddf80b
Gabor points out that we can't spell. :)
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llvm-svn: 27049
2006-03-24 07:12:19 +00:00
a91d8a5b43
All v2f64 shuffle cases can be handled.
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llvm-svn: 27044
2006-03-24 06:40:32 +00:00
2595a687da
More efficient v2f64 shuffle using movlhps, movhlps, unpckhpd, and unpcklpd.
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llvm-svn: 27040
2006-03-24 02:58:06 +00:00
6afb3c2de7
A new entry
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llvm-svn: 27039
2006-03-24 02:57:03 +00:00
0eafbc3593
Get JIT/Interpreter working on Windows again.
...
llvm-svn: 27037
2006-03-24 02:53:49 +00:00
a4f6805a86
legalize vbit_convert nodes whose result is a legal type.
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Legalize intrinsic nodes.
llvm-svn: 27036
2006-03-24 02:26:29 +00:00
d96b09a7b9
Lower target intrinsics into an INTRINSIC node
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llvm-svn: 27035
2006-03-24 02:22:33 +00:00
f9c3dcfdc1
Ignore the burg output files.
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llvm-svn: 27033
2006-03-24 02:21:35 +00:00
6b05290922
fix some bogus assertions: noop bitconverts are legal
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llvm-svn: 27032
2006-03-24 02:20:47 +00:00
d27fb3e85e
Handle more shuffle cases with SHUFP* instructions.
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llvm-svn: 27024
2006-03-24 01:18:28 +00:00
1d2e995fc1
Lower BUILD_VECTOR to VECTOR_SHUFFLE if there are two distinct nodes (and if
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the target can handle it). Issue two SCALAR_TO_VECTOR ops followed by a
VECTOR_SHUFFLE to select from the two vectors.
llvm-svn: 27023
2006-03-24 01:17:21 +00:00
ebac9a4adf
Identify the INTRINSIC node
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llvm-svn: 27020
2006-03-24 01:04:30 +00:00
78eaa10f1a
Add new generated files.
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llvm-svn: 27013
2006-03-23 23:48:12 +00:00
4b5b4e373b
Typo
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llvm-svn: 27008
2006-03-23 23:24:51 +00:00
fb39d2a7f7
Unneeded forward.
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llvm-svn: 27004
2006-03-23 23:05:52 +00:00
f7cfa52e7a
Make sure types are allocated in the scope of their use.
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llvm-svn: 27002
2006-03-23 23:02:34 +00:00
cbcfe46556
add a note
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llvm-svn: 27000
2006-03-23 21:28:44 +00:00
d7c4e7d255
add support for splitting casts. This implements
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CodeGen/Generic/vector.ll:test_cast_2.
llvm-svn: 26999
2006-03-23 21:16:34 +00:00
f842ea57bb
Typo
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llvm-svn: 26997
2006-03-23 20:26:04 +00:00
b119990289
Add some more bulletproofing to auto upgrade of llvm.dbg intrinsics.
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llvm-svn: 26996
2006-03-23 20:13:25 +00:00
81137629e0
Add PPC vector bit-convert support
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llvm-svn: 26995
2006-03-23 19:54:27 +00:00
3c43609f1f
Add support to locate local variables in frames (early version.)
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llvm-svn: 26994
2006-03-23 18:12:57 +00:00
8f64426f5c
Strip changes to llvm.dbg intrinsics.
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llvm-svn: 26993
2006-03-23 18:11:33 +00:00
83f99115db
Can't combine anymore - we don't have a chain through llvm.dbg intrinsics.
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llvm-svn: 26992
2006-03-23 18:10:42 +00:00
cf0166fbeb
Change interface to DwarfWriter.
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llvm-svn: 26991
2006-03-23 18:09:44 +00:00
267d39d128
Modify how CBE handles #lines.
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llvm-svn: 26990
2006-03-23 18:08:29 +00:00
2b74656f25
Generate local variable and scope information and equivalent dwarf forms.
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llvm-svn: 26989
2006-03-23 18:07:55 +00:00
a8bdac875d
Handle new forms of llvm.dbg intrinsics.
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llvm-svn: 26988
2006-03-23 18:06:46 +00:00
0cf8ed61cc
Simplify handling of llvm.dbg intrinsic operands to one spot.
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llvm-svn: 26987
2006-03-23 18:05:12 +00:00
01bd749537
Change the argument types of llvm.dbg intrinsics.
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llvm-svn: 26985
2006-03-23 18:03:20 +00:00
ce0206e119
Fix the encodings of these new instructions, hopefully fixing the JIT
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failures from last night
llvm-svn: 26981
2006-03-23 16:13:50 +00:00
82ed4a42f9
Following icc's lead: use movdqa to load / store 128-bit integer vectors
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llvm-svn: 26980
2006-03-23 07:44:07 +00:00
a011ba8a76
prune #includes
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llvm-svn: 26975
2006-03-23 05:43:58 +00:00
6f95ab7abb
Eliminate IntrinsicLowering from TargetMachine.
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Make the CBE and V9 backends create their own, since they're the only ones that use it.
llvm-svn: 26974
2006-03-23 05:43:16 +00:00
9ea1b3f9fd
simplify some code
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llvm-svn: 26972
2006-03-23 05:29:04 +00:00
811dd8d009
remove always-null IntrinsicLowering argument.
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llvm-svn: 26971
2006-03-23 05:28:02 +00:00
0b2de9f2d4
remove the intrinsiclowering hook
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llvm-svn: 26970
2006-03-23 05:22:51 +00:00
7055878170
Add v4i32 <-> v4f32 bitconvert patterns.
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llvm-svn: 26969
2006-03-23 02:36:37 +00:00
b9b0550dc6
Add 128-bit integer vector load and add (for testing).
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llvm-svn: 26967
2006-03-23 01:57:24 +00:00
fb6e02931c
Add support for 8 bit immediates with 16/32 bit cmp instructions
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llvm-svn: 26966
2006-03-23 01:29:48 +00:00
b893d04a67
Fix a typo
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llvm-svn: 26965
2006-03-22 22:20:49 +00:00
021bb7c956
Added a ValueType operand to isShuffleMaskLegal(). For now, x86 will not do
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64-bit vector shuffle.
llvm-svn: 26964
2006-03-22 22:07:06 +00:00
2f4119a608
Implement simple support for vector casting. This can currently only handle
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casts between legal vector types.
llvm-svn: 26961
2006-03-22 20:09:35 +00:00
ed794cd27b
SHUFP* are two address code.
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llvm-svn: 26959
2006-03-22 20:08:18 +00:00
bc04722860
Some clean up.
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llvm-svn: 26957
2006-03-22 19:22:18 +00:00
d4e1557941
- Supposely movlhps is faster / better than unpcklpd.
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- Don't forget pshufd is only available with sse2.
llvm-svn: 26956
2006-03-22 19:16:21 +00:00
68ad48bd1a
- Implement X86ISelLowering::isShuffleMaskLegal(). We currently only support
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splat and PSHUFD cases.
- Clean up shuffle / splat matching code.
llvm-svn: 26954
2006-03-22 18:59:22 +00:00
7d80b4f366
silence a bogus gcc warning
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llvm-svn: 26953
2006-03-22 17:27:24 +00:00
8fdbdf20cd
- VECTOR_SHUFFLE of v4i32 / v4f32 with undef second vector always matches
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PSHUFD. We can make permutes entries which point to the undef pointing
anything we want.
- Change some names to appease Chris.
llvm-svn: 26951
2006-03-22 08:01:21 +00:00
e24cf9dfa1
add a note
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llvm-svn: 26950
2006-03-22 07:33:46 +00:00
3617caf526
Fix PSHUF* and SHUF* jit code emission problems
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llvm-svn: 26949
2006-03-22 07:10:28 +00:00
2d52c1b8b9
Eliminate the dependency of ExecutionEngine on the JIT/Interpreter libraries.
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Now you can build a tool with just the JIT or just the interpreter.
llvm-svn: 26946
2006-03-22 06:07:50 +00:00
eccf46950c
This has been implemented. Tweak it into another note
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llvm-svn: 26944
2006-03-22 05:33:23 +00:00
4a66d69433
When possible, custom lower 32-bit SINT_TO_FP to this:
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_foo2:
extsw r2, r3
std r2, -8(r1)
lfd f0, -8(r1)
fcfid f0, f0
frsp f1, f0
blr
instead of this:
_foo2:
lis r2, ha16(LCPI2_0)
lis r4, 17200
xoris r3, r3, 32768
stw r3, -4(r1)
stw r4, -8(r1)
lfs f0, lo16(LCPI2_0)(r2)
lfd f1, -8(r1)
fsub f0, f1, f0
frsp f1, f0
blr
This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).
llvm-svn: 26943
2006-03-22 05:30:33 +00:00
77373d1bea
Add support for "ri" addressing modes where the immediate is a 14-bit field
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which is shifted left two bits before use. Instructions like STD use this
addressing mode.
llvm-svn: 26942
2006-03-22 05:26:03 +00:00
f5e36c8bc0
fix a warning
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llvm-svn: 26941
2006-03-22 04:18:34 +00:00
d097e67544
Some splat and shuffle support.
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llvm-svn: 26940
2006-03-22 02:53:00 +00:00
b1d3c64d1f
Add a couple more pseudo instructions.
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llvm-svn: 26939
2006-03-22 02:52:03 +00:00
8fa445a89d
Endianness does not affect the order of vector fields. This fixes
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SingleSource/UnitTests/Vector/build.c
llvm-svn: 26936
2006-03-22 01:46:54 +00:00
4e7371758f
Fix the JIT encoding of the VAForm_1 instructions, including vmaddfp
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llvm-svn: 26935
2006-03-22 01:44:36 +00:00
5be4352124
Enclose some variables in a scope to avoid error with some gcc versions
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llvm-svn: 26934
2006-03-22 00:12:37 +00:00
baea59c61c
Didn't mean to check this in. No MMX support yet.
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llvm-svn: 26933
2006-03-21 23:04:23 +00:00
d5e905d762
- Use movaps to store 128-bit vector integers.
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- Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd.
llvm-svn: 26932
2006-03-21 23:01:21 +00:00
340a6b5c26
add expand support for extractelement
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llvm-svn: 26931
2006-03-21 21:02:03 +00:00
00f4683bf6
These targets don't support EXTRACT_VECTOR_ELT, though, in time, X86 will.
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llvm-svn: 26930
2006-03-21 20:51:05 +00:00
7c0cd8cafc
add some trivial support for extractelement.
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llvm-svn: 26928
2006-03-21 20:44:12 +00:00
3a2ae6ad3c
Don't emit pseudo instructions!
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llvm-svn: 26926
2006-03-21 20:19:37 +00:00
672a42d731
Add a hacky workaround for crashes due to vectors live across blocks.
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Note that this code won't work for vectors that aren't legal on the
target. Improvements coming.
llvm-svn: 26925
2006-03-21 19:20:37 +00:00
013127981a
Update readme
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llvm-svn: 26924
2006-03-21 18:58:20 +00:00
139eac5b71
Print absolute memory references like this:
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lwz r2, 8(0)
instead of this:
lwz r2, 8(r0)
This fixes the llc/llc-beta failures on PPC last night.
llvm-svn: 26922
2006-03-21 17:21:13 +00:00
2d819f5fa4
Combine 2 entries
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llvm-svn: 26921
2006-03-21 07:18:26 +00:00
aeebc96099
Add a note about x86 register coallescing
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llvm-svn: 26920
2006-03-21 07:12:57 +00:00
1208d9179a
- Remove scalar to vector pseudo ops. They are just wrong.
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- Handle FR32 to VR128:v4f32 and FR64 to VR128:v2f64 with aliases of MOVAPS
and MOVAPD. Mark them as move instructions and *hope* they will be deleted.
llvm-svn: 26919
2006-03-21 07:09:35 +00:00
bda7310ef7
With Evan's latest tblgen patch, this code is obsolete, thanks Evan!
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llvm-svn: 26917
2006-03-21 06:37:40 +00:00
d2132f87d7
When codegen'ing vector MUL using VFMADD, *add* the 0, don't *mul* the 0.
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llvm-svn: 26913
2006-03-21 00:51:38 +00:00
f194834161
minor note
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llvm-svn: 26912
2006-03-21 00:47:09 +00:00
e4d1416239
x86 ISD::SCALAR_TO_VECTOR support.
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llvm-svn: 26911
2006-03-21 00:33:35 +00:00
fb872b41c0
Junk unused vector register classes.
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llvm-svn: 26910
2006-03-21 00:30:59 +00:00
c8b16d00b9
Handle constant addresses more efficiently, folding the low bits into the
...
disp field of the load/store if possible. This compiles
CodeGen/PowerPC/load-constant-addr.ll to:
_test:
lis r2, 2838
lfs f1, 26848(r2)
blr
instead of:
_test:
lis r2, 2838
ori r2, r2, 26848
lfs f1, 0(r2)
blr
llvm-svn: 26908
2006-03-20 22:38:22 +00:00
6d74b09da7
remove dead variable
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llvm-svn: 26907
2006-03-20 22:37:23 +00:00
a1bc294f0c
Fix a couple of bugs in permute/splat generate, thanks to Nate for actually
...
figuring these out! :)
llvm-svn: 26904
2006-03-20 18:26:51 +00:00
eda030da04
reenable this hack, the tblgen version isn't quite ready
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llvm-svn: 26902
2006-03-20 17:54:43 +00:00
f96d523b8f
Fix the pattern for VADDUWM, add i32 splat
...
llvm-svn: 26901
2006-03-20 17:51:58 +00:00
89f3cff0f5
Use tblgen'd VECTOR_SHUFFLE selection code.
...
llvm-svn: 26900
2006-03-20 08:14:16 +00:00
a9a1313386
Add support for generating vspltw, instead of a vperm instruction with a
...
constant pool load. This generates significantly nicer code for splats.
When tblgen gets bugfixed, we can remove the custom selection code.
llvm-svn: 26898
2006-03-20 06:51:10 +00:00
a8fbb6dd3d
Implement PPC::isSplatShuffleMask and PPC::getVSPLTImmediate.
...
llvm-svn: 26897
2006-03-20 06:37:44 +00:00
ffc475689b
fix duplicate definition errors
...
llvm-svn: 26896
2006-03-20 06:33:01 +00:00
80b6bd2746
Add a build_vector node
...
llvm-svn: 26895
2006-03-20 06:18:01 +00:00
382f356bd9
Check in some intermediate code that adds a skeleton for matching vsplt*
...
instructions
llvm-svn: 26894
2006-03-20 06:15:45 +00:00
e6448448c2
Move a few things around.
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llvm-svn: 26893
2006-03-20 06:04:52 +00:00
e4e1ac37ba
add vector_shuffle
...
llvm-svn: 26891
2006-03-20 05:40:45 +00:00
93d99f9928
fix typo
...
llvm-svn: 26889
2006-03-20 05:05:55 +00:00
366b2514fa
add vsplat instructions, fix sched description for vperm
...
llvm-svn: 26888
2006-03-20 04:47:33 +00:00
a8713b1ee6
Custom lower arbitrary VECTOR_SHUFFLE's to VPERM.
...
TODO: leave specific ones as VECTOR_SHUFFLE's and turn them into specialized
operations like vsplt*
llvm-svn: 26887
2006-03-20 01:53:53 +00:00
0a8b4eaee9
Claim to have v16i8 for perm masks
...
llvm-svn: 26886
2006-03-20 01:53:02 +00:00
21e68c8001
If a target supports splatting with SHUFFLE_VECTOR, lower to it from BUILD_VECTOR(x,x,x,x)
...
llvm-svn: 26885
2006-03-20 01:52:29 +00:00
6b20104410
TargetData doesn't know the alignment of vectors :(
...
llvm-svn: 26884
2006-03-20 01:51:46 +00:00
e7a058de7d
add the vperm instruction
...
llvm-svn: 26883
2006-03-20 01:00:56 +00:00
00f0589bc0
Add very basic support for VECTOR_SHUFFLE
...
llvm-svn: 26880
2006-03-19 23:56:04 +00:00
d16f6fdd49
add a note with a testcase
...
llvm-svn: 26877
2006-03-19 22:27:41 +00:00
169e6238ad
Add a note about the MUL -> FMADD vector bug.
...
llvm-svn: 26874
2006-03-19 22:08:08 +00:00
d783c76c18
Teach cee to propagate through switch statements. This implements
...
Transforms/CorrelatedExprs/switch.ll
Patch contributed by Eric Kidd!
llvm-svn: 26872
2006-03-19 19:37:24 +00:00
f7c2e3628b
Vector undef's
...
llvm-svn: 26870
2006-03-19 09:38:54 +00:00
7e9440a4fc
Custom lower SCALAR_TO_VECTOR into lve*x.
...
llvm-svn: 26868
2006-03-19 06:55:52 +00:00
79fb91cc69
Allow SCALAR_TO_VECTOR to be custom lowered.
...
llvm-svn: 26867
2006-03-19 06:47:21 +00:00
9cdc5a0ce7
Add SCALAR_TO_VECTOR support
...
llvm-svn: 26866
2006-03-19 06:31:19 +00:00
b1ee9c7e24
PPC doesn't have SCALAR_TO_VECTOR
...
llvm-svn: 26865
2006-03-19 06:17:19 +00:00
5b595af956
add support for vector undef
...
llvm-svn: 26863
2006-03-19 06:10:09 +00:00
0a03f789c2
Remind us of exit value substitution
...
llvm-svn: 26862
2006-03-19 06:09:23 +00:00
5111c81a3c
Turning on LSR by default
...
llvm-svn: 26861
2006-03-19 06:08:49 +00:00
66a9c0dea7
Remember which tests are hurt by LSR.
...
llvm-svn: 26860
2006-03-19 06:08:11 +00:00
eb5b2e705c
Don't bother storing undef elements of BUILD_VECTOR's
...
llvm-svn: 26858
2006-03-19 05:46:04 +00:00
0c9eb670bb
minor fixes
...
llvm-svn: 26857
2006-03-19 05:43:01 +00:00
ea6468758d
notes
...
llvm-svn: 26856
2006-03-19 05:33:30 +00:00
431c90c9fa
we don't use lmw/stmw. When we want them they are easy enough to add
...
llvm-svn: 26853
2006-03-19 04:33:37 +00:00
5d3ff12c8f
Implement expand of BUILD_VECTOR containing variable elements.
...
This implements CodeGen/Generic/vector.ll:test_variable_buildvector
llvm-svn: 26852
2006-03-19 04:18:56 +00:00
5336a59e4b
fold insertelement(buildvector) -> buildvector if the inserted element # is
...
a constant. This implements test_constant_insert in CodeGen/Generic/vector.ll
llvm-svn: 26851
2006-03-19 01:27:56 +00:00
29b2301460
implement basic support for INSERT_VECTOR_ELT.
...
llvm-svn: 26849
2006-03-19 01:17:20 +00:00
f7b6e7212f
rename these nodes
...
llvm-svn: 26848
2006-03-19 01:13:28 +00:00
f4e1a53647
Rename ConstantVec -> BUILD_VECTOR and VConstant -> VBUILD_VECTOR. Allow*BUILD_VECTOR to take variable inputs.
...
llvm-svn: 26847
2006-03-19 00:52:58 +00:00
c16b05e67d
implement vector.ll:test_undef
...
llvm-svn: 26845
2006-03-19 00:20:20 +00:00
93640543a9
Fix the remaining bugs in the vector expansion rework I commited yesterday.
...
This fixes CodeGen/Generic/vector.ll
llvm-svn: 26843
2006-03-19 00:07:49 +00:00
c28282bd87
- Fixed a bogus if condition.
...
- Added more debugging info.
- Allow reuse of IV of negative stride. e.g. -4 stride == 2 * iv of -2 stride.
llvm-svn: 26841
2006-03-18 08:03:12 +00:00
32206f54c6
Change the structure of lowering vector stuff. Note: This breaks some
...
things.
llvm-svn: 26840
2006-03-18 01:44:44 +00:00
9bf978dc20
Use the generic vector register classes VR64 / VR128 rather than V4F32,
...
V8I16, etc.
llvm-svn: 26838
2006-03-18 01:23:20 +00:00
f09f0ebd48
Sort StrideOrder so we can process the smallest strides first. This allows
...
for more IV reuses.
llvm-svn: 26837
2006-03-18 00:44:49 +00:00
21f87d0e4c
Fix subfic to match subc by default instead of sub so that it is correctly
...
cost-modeled as producing a flag. This fixes the test I just added for neg
llvm-svn: 26835
2006-03-17 22:41:37 +00:00
b09a56f3a4
Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
...
llvm-svn: 26833
2006-03-17 20:31:41 +00:00
4f674921d6
Move some pattern fragments to the right files.
...
llvm-svn: 26831
2006-03-17 19:55:52 +00:00
98931bc381
add a couple enum values
...
llvm-svn: 26830
2006-03-17 19:53:59 +00:00
4520698820
Allow users of iv / stride to be rewritten with expression that is a multiply
...
of a smaller stride even if they have a common loop invariant expression part.
llvm-svn: 26828
2006-03-17 19:52:23 +00:00
388fc4d9fb
Disable x86 fastcc from passing args in registers
...
llvm-svn: 26824
2006-03-17 17:27:47 +00:00
779c10818c
Fix use of LEVEL.
...
llvm-svn: 26822
2006-03-17 07:39:44 +00:00
ee4b4f55ee
Two fixes:
...
1. Allow building of Intrinsics.gen to work for srcdir != objdir
2. Add a rule for installation of Intrinsics.gen.
llvm-svn: 26819
2006-03-17 06:27:06 +00:00
43798850f9
Parameterize the number of integer arguments to pass in registers
...
llvm-svn: 26818
2006-03-17 05:10:20 +00:00
bfc2e97383
Also fold MOV8r0, MOV16r0, MOV32r0 + store to MOV8mi, MOV16mi, and MOV32mi.
...
llvm-svn: 26817
2006-03-17 02:36:22 +00:00
aca7915b70
Add some missing entries to X86RegisterInfo::foldMemoryOperand(). e.g.
...
ADD32ri8.
llvm-svn: 26816
2006-03-17 02:25:01 +00:00
27750f3287
- Nuke 16-bit SBB instructions. We'll never use them.
...
- Nuke a bogus comment.
llvm-svn: 26815
2006-03-17 02:24:04 +00:00
bb01d4f272
Remove BRTWOWAY*
...
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
llvm-svn: 26814
2006-03-17 01:40:33 +00:00
8bf1c59e7f
remove dead variable
...
llvm-svn: 26813
2006-03-16 23:52:08 +00:00
7ececaad83
Fix a problem fully scalarizing values.
...
llvm-svn: 26811
2006-03-16 23:05:19 +00:00
c11fcceec5
A new entry.
...
llvm-svn: 26810
2006-03-16 22:44:22 +00:00
fb0e36fa56
Notes on how to kill the eeevil brtwoway, and make ppc branch selector
...
more target independant, generate better code, and be less conservative.
llvm-svn: 26809
2006-03-16 22:37:48 +00:00
1e6dfa4c1f
Strangely, calls clobber call-clobbered vector regs. Whodathoughtit?
...
llvm-svn: 26808
2006-03-16 22:35:59 +00:00
325bb46315
add a note
...
llvm-svn: 26807
2006-03-16 22:25:55 +00:00
91400bd413
teach the ppc backend how to spill/reload vector regs
...
llvm-svn: 26806
2006-03-16 22:24:02 +00:00
6e90062416
add callee saved vector regs
...
llvm-svn: 26805
2006-03-16 22:07:06 +00:00
f75555feb9
Bug fix: condition inverted.
...
llvm-svn: 26804
2006-03-16 22:02:48 +00:00
3df447d354
For each loop, keep track of all the IV expressions inserted indexed by
...
stride. For a set of uses of the IV of a stride which is a multiple
of another stride, do not insert a new IV expression. Rather, reuse the
previous IV and rewrite the uses as uses of IV expression multiplied by
the factor.
e.g.
x = 0 ...; x ++
y = 0 ...; y += 4
then use of y can be rewritten as use of 4*x for x86.
llvm-svn: 26803
2006-03-16 21:53:05 +00:00
20931a798e
Added a way for TargetLowering to specify what values can be used as the
...
scale component of the target addressing mode.
llvm-svn: 26802
2006-03-16 21:47:42 +00:00
0b27047a6c
in functions that use a lot of callee saved regs, this can be more than
...
5 instructions away.
llvm-svn: 26801
2006-03-16 21:31:45 +00:00
fd9f3e8ed3
Add support for copying registers. still needed: spilling and reloading them
...
llvm-svn: 26800
2006-03-16 20:03:58 +00:00
8471b15706
Add support for CopyFromReg from vector values. Note: this doesn't support
...
illegal vector types yet!
llvm-svn: 26799
2006-03-16 19:57:50 +00:00
49409cb925
Teach CreateRegForValue how to handle vector types.
...
llvm-svn: 26798
2006-03-16 19:51:18 +00:00
ad74844bfa
set TransformToType correctly for vector types.
...
llvm-svn: 26797
2006-03-16 19:50:01 +00:00
32e73f9881
Another case we could do better on.
...
llvm-svn: 26795
2006-03-16 18:50:44 +00:00
1678a6c477
Save/restore VRSAVE once per function, not once per block.
...
llvm-svn: 26793
2006-03-16 18:25:23 +00:00
4b41e40621
add support for the bitconvert node
...
llvm-svn: 26789
2006-03-16 01:29:53 +00:00
4024c00ce7
add support for vector->vector casts
...
llvm-svn: 26788
2006-03-15 22:19:46 +00:00
cad70c3e46
Add a note, this code should be moved to the dag combiner.
...
llvm-svn: 26787
2006-03-15 22:19:18 +00:00
6d6084fd04
Teach the strip pass to strip type names in addition to value names. This
...
is fallout from the type/value split in the symtab long long ago :)
llvm-svn: 26785
2006-03-15 19:22:41 +00:00
71050ba709
Expand subprogram and added block descriptor.
...
llvm-svn: 26782
2006-03-15 19:09:58 +00:00
b3dae7cfa9
no heap is happening here
...
llvm-svn: 26781
2006-03-15 19:03:16 +00:00
c0b65305f1
remove qsort for now
...
llvm-svn: 26779
2006-03-15 18:32:18 +00:00
fb4df2055f
allow field sensitivity to be a tunable parameter
...
llvm-svn: 26777
2006-03-15 05:43:41 +00:00
2e1fde7c5c
Update scheduling info for vrsave instruction
...
llvm-svn: 26776
2006-03-15 05:25:05 +00:00
3196422df0
Handle one offset with growth case seen in povray. Namely, if we have an offset,
...
and the offset lands at a field boundary in the old type, construct a new type,
copying the fields masked by the offset from the old type, and unify with that.
llvm-svn: 26775
2006-03-15 04:04:21 +00:00
c254e5b180
improve mem intrinsics and add a few things povray uses
...
llvm-svn: 26774
2006-03-15 03:43:59 +00:00
6995470323
Bugfix, unbreaking CodeGen/PowerPC/cttz.ll
...
llvm-svn: 26764
2006-03-14 19:49:57 +00:00
6d4a221d80
Fix an et-forest memory leak. Patch by Daniel Berlin.
...
llvm-svn: 26763
2006-03-14 19:41:45 +00:00
5271a1f9b5
add a note
...
llvm-svn: 26762
2006-03-14 19:31:24 +00:00
b8e155567a
1. Use null for serialized empty strings.
...
2. Allow for user defined debug descriptors.
3. Allow for user augmented fields on debug descriptors.
llvm-svn: 26760
2006-03-14 18:37:57 +00:00
ab1ed2aa96
Fix an off by one error that caused PPC LLC failures last night.
...
llvm-svn: 26758
2006-03-14 17:56:49 +00:00
c5f866bb4a
Implement a FIXME, recusively reassociating
...
A*A*B + A*A*C --> A*(A*B+A*C) --> A*(A*(B+C))
This implements Reassociate/mul-factor3.ll
llvm-svn: 26757
2006-03-14 16:04:29 +00:00
2fc319d444
extract some code into a method, no functionality change
...
llvm-svn: 26755
2006-03-14 07:11:11 +00:00
30402be175
transformation implemented
...
llvm-svn: 26754
2006-03-14 06:57:34 +00:00
d6bde46d85
Promote shifts by a constant to multiplies so that we can reassociate
...
(x<<1)+(y<<1) -> (X+Y)<<1. This implements
Transforms/Reassociate/shift-factor.ll
llvm-svn: 26753
2006-03-14 06:55:18 +00:00
c67a060a51
Convert llvm.cs.uiuc.edu -> llvm.org
...
llvm-svn: 26748
2006-03-14 05:54:52 +00:00
cf0bdffe6d
1. Handle removal of all arguments for a morphed intrinsic.
...
2. Remove the declaration of llvm.dbg.declare.
llvm-svn: 26745
2006-03-14 02:00:35 +00:00
0f9d6534f5
PPC LSR pass should use target lowering hooks.
...
llvm-svn: 26743
2006-03-13 23:56:51 +00:00
2dd2c652b2
Added getTargetLowering() to TargetMachine. Refactored targets to support this.
...
llvm-svn: 26742
2006-03-13 23:20:37 +00:00
60f495100a
Update
...
llvm-svn: 26741
2006-03-13 23:19:10 +00:00
af598d2461
Add LSR hooks.
...
llvm-svn: 26740
2006-03-13 23:18:16 +00:00
c567c4efbb
Added target lowering hooks which LSR consults to make more intelligent
...
transformation decisions.
llvm-svn: 26738
2006-03-13 23:14:23 +00:00
2b8eb375d7
Handle builtins that directly correspond to GCC builtins.
...
llvm-svn: 26737
2006-03-13 23:09:05 +00:00
02e2c18c9c
For functions that use vector registers, save VRSAVE, mark used
...
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
llvm-svn: 26733
2006-03-13 21:52:10 +00:00
68ac09d5cb
make sure dead token factor nodes are removed by the dag combiner.
...
llvm-svn: 26731
2006-03-13 18:37:30 +00:00
611f965820
Bring makefile back into compliance with standard by using
...
$(Echo) instead of @echo
llvm-svn: 26730
2006-03-13 17:57:31 +00:00
acb6e34277
Handle the removal of the debug chain.
...
llvm-svn: 26729
2006-03-13 13:07:37 +00:00
fe4c7fb7ae
remove two implemented items
...
llvm-svn: 26728
2006-03-13 06:52:22 +00:00
d8c2a48d58
Fold X+Y -> X|Y when safe. This implements:
...
Regression/CodeGen/PowerPC/and_add.ll
a case that occurs with dynamic allocas of constant size.
llvm-svn: 26727
2006-03-13 06:51:27 +00:00
3d761b6211
I can't convince myself that this is safe, remove the recursive call.
...
llvm-svn: 26725
2006-03-13 06:42:16 +00:00
8bb6cb7d7b
add a couple of missing folds
...
llvm-svn: 26724
2006-03-13 06:26:26 +00:00
994d8e6bd4
For targets with FABS/FNEG support, lower copysign to an integer load,
...
a select and FABS/FNEG.
This speeds up a trivial (aka stupid) copysign benchmark I wrote from 6.73s
to 2.64s, woo.
llvm-svn: 26723
2006-03-13 06:08:38 +00:00
ec9d0bc3ec
Fix a couple of bugs that broke the alpha tester build
...
llvm-svn: 26722
2006-03-13 05:23:59 +00:00
4fbb612685
Handle cracked instructions in dispatch group formation.
...
llvm-svn: 26721
2006-03-13 05:20:04 +00:00
7579cfb1a0
Mark instructions that are cracked by the PPC970 decoder as such.
...
llvm-svn: 26720
2006-03-13 05:15:10 +00:00
51348c5f27
Several big changes:
...
1. Use flags on the instructions in the .td file to indicate the PPC970 unit
type instead of a table in the .cpp file. Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
accurately.
llvm-svn: 26719
2006-03-12 09:13:49 +00:00
a767dbf197
Don't advance the hazard recognizer when there are no hazards and no instructions
...
to be emitted.
Don't add one to the latency of a completed instruction if the latency of the
op is 0.
llvm-svn: 26718
2006-03-12 09:01:41 +00:00
86a9b60a25
Chain operands aren't real uses: they don't require the full latency of the
...
predecessor to finish before they can start.
llvm-svn: 26717
2006-03-12 03:52:09 +00:00
572003ca15
As a pending queue data structure to keep track of instructions whose
...
operands have all issued, but whose results are not yet available. This
allows us to compile:
int G;
int test(int A, int B, int* P) {
return (G+A)*(B+1);
}
to:
_test:
lis r2, ha16(L_G$non_lazy_ptr)
addi r4, r4, 1
lwz r2, lo16(L_G$non_lazy_ptr)(r2)
lwz r2, 0(r2)
add r2, r2, r3
mullw r3, r2, r4
blr
instead of this, which has a stall between the lis/lwz:
_test:
lis r2, ha16(L_G$non_lazy_ptr)
lwz r2, lo16(L_G$non_lazy_ptr)(r2)
addi r4, r4, 1
lwz r2, 0(r2)
add r2, r2, r3
mullw r3, r2, r4
blr
llvm-svn: 26716
2006-03-12 00:38:57 +00:00
356183d91e
rename priorityqueue -> availablequeue. When a node is scheduled, remember
...
which cycle it lands on.
llvm-svn: 26714
2006-03-11 22:44:37 +00:00
063086b0f4
Make CurrCycle a local var instead of an instance var
...
llvm-svn: 26713
2006-03-11 22:34:41 +00:00
9995a0c019
Move some methods around so that BU specific code is together, TD specific code
...
is together, and direction independent code is together.
llvm-svn: 26712
2006-03-11 22:28:35 +00:00
Chris Lattner