Commit Graph

6 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen 5b5abb4ea1 Don't run this test through -regalloc=basic.
The basic allocator is really bad about hinting, so it doesn't eliminate all
copies when physreg joining is disabled.

llvm-svn: 130817
2011-05-04 01:01:44 +00:00
Akira Hatanaka 2cb3aa30dd Re-enable test o32_cc_vararg.ll.
llvm-svn: 129616
2011-04-15 22:23:09 +00:00
Akira Hatanaka 279169771b Add pass that expands pseudo instructions into target instructions after register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions.
llvm-svn: 129594
2011-04-15 19:52:08 +00:00
Andrew Trick b53a00d2cb Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency.
Additional fixes:
Do something reasonable for subtargets with generic
itineraries by handle node latency the same as for an empty
itinerary. Now nodes default to unit latency unless an itinerary
explicitly specifies a zero cycle stage or it is a TokenFactor chain.

Original fixes:
UnitsSharePred was a source of randomness in the scheduler: node
priority depended on the queue data structure. I rewrote the recent
VRegCycle heuristics to completely replace the old heuristic without
any randomness. To make the ndoe latency adjustments work, I also
needed to do something a little more reasonable with TokenFactor. I
gave it zero latency to its consumers and always schedule it as low as
possible.

llvm-svn: 129421
2011-04-13 00:38:32 +00:00
Jakob Stoklund Olesen f4c9754d5c Fix Mips, Sparc, and XCore tests that were dependent on register allocation.
Add an extra run with -regalloc=basic to keep them honest.

llvm-svn: 128654
2011-03-31 18:42:43 +00:00
Bruno Cardoso Lopes 048ffabe78 Improve varags handling, with testcases. Patch by Sasa Stankovic
llvm-svn: 127349
2011-03-09 19:22:22 +00:00