b7c2962d20
MC machine encoding for simple aritmetic instructions that use a shifted
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register operand.
llvm-svn: 116259
2010-10-11 23:16:21 +00:00
c43c930690
Implement a few more binary encoding bits. Still very early stage proof-of-
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concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.
This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.
llvm-svn: 116112
2010-10-08 21:45:55 +00:00
b770c00610
Reapply 116059, this time without the fatfingered pasto at the top.
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''const'ify getMachineOpValue() and associated helpers.'
llvm-svn: 116067
2010-10-08 17:45:54 +00:00
00351b7731
Reverting 116059. Bots are unhappy with it.
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llvm-svn: 116064
2010-10-08 17:28:40 +00:00
e2d30cd4b5
'const'ify getMachineOpValue() and associated helpers.
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llvm-svn: 116059
2010-10-08 16:52:44 +00:00
0bb2f9afa9
Enable binary encoding of some simple instructions.
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llvm-svn: 116022
2010-10-08 00:39:21 +00:00
a7b6d58f45
Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.
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llvm-svn: 116018
2010-10-08 00:21:28 +00:00
91029094e0
Trivial MC code emitter shell. No instruction forms actually handled yet.
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llvm-svn: 115993
2010-10-07 22:12:50 +00:00
8aed386d82
Include the auto-generated bits for machine encoding.
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llvm-svn: 115987
2010-10-07 21:57:55 +00:00
07b5b1802e
ARM instruction don't have instruction prefixes, so remove the helper functions
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for them from the MCCodeEmitter.
llvm-svn: 115975
2010-10-07 20:41:30 +00:00
abf60e3421
Fix build.
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llvm-svn: 114292
2010-09-18 17:54:37 +00:00
1287f4f3b8
Add skeleton infrastructure for the ARMMCCodeEmitter class. Patch by Jason Kim!
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llvm-svn: 114195
2010-09-17 18:46:17 +00:00
Jim Grosbach